Dissertation Report

on

Gate Stacked GaN-FinFET with BaTiO3 Oxide for

High Performance and High-Power Applications
Submitted in the partial fulfillment of the requirement for the degree of
Master of Science in Electronics
by
SUJAL JAIN
Exam. Roll No. 21251749029

Under the supervision of

Dr. Yogesh Pratap

Assistant Professor
Department of Electronic Science
University of Delhi South Campus

Department of Electronic Science

University of Delhi South Campus
New Delhi-110021
June-2023

1
 CERTIFICATE

This is to certify that, the report on Dissertation work entitled “Gate Stacked
GaN-FinFET with BaTiO3 Oxide for High Performance and High-Power
Applications” is carried out by Mr. Sujal Jain under the guidance of the
undersigned. This project is done as a partial fulfillment for the award of degree
“Master of Science in Electronics” from University of Delhi South Campus,
New Delhi during January-May-2023.This report embodies original work of the
candidate and has not been submitted in full or any part to other university for
the award of any other diploma and degree.

Dr. Yogesh Pratap Dr. P. Koteswara Rao

Assistant Professor Assistant Professor

(Project Guide) (Project Coordinator)

Dr. Harsupreet Kaur

Head of Department
Department of Electronic Science
University of Delhi,
South Campus
New Delhi
 DECLARATION

I “Sujal Jain” hereby declare that the dissertation entitled “Gate Stacked
GaN-FinFET with BaTiO3 Oxide for High Performance and High-Power
Applications” in partial fulfillment for the award of the degree of Master of
Science in Electronics from the Department of Electronic Science,
University of Delhi, South Campus is an original record of the work carried
out by me under the guidance and supervision of Dr. Yogesh Pratap from
January, 2023 – May 2023. The matter embodied in this dissertation has not
been submitted elsewhere for the award of degree or diploma.

I would also like to mention that the dissertation is well documented. In case,
any grammatical error is found, I should be held responsible for the same.

Sujal Jain
M.Sc. Electronics
(IV Sem.)
Roll No.: 21251749029

Department of Electronic Science

University of Delhi
New Delhi-110021

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 ACKNOWLEDGMENT

I would like to express my sincere gratitude and appreciation to all

those who have contributed to the successful completion of this
project.
First and foremost, I would like to thank my supervisor, Dr. Yogesh
Pratap for their valuable guidance, unwavering support, and insightful
feedback throughout the course of this project. Their expertise and
encouragement have greatly influenced and shaped this project work.
I am proud to acknowledge the invaluable opportunity I had to work
with an exceptionally experienced professor like him.
I am also grateful to Dr. P. Koteswara Rao the project coordinator, for
their assistance in coordinating and facilitating the project activities.
Their organizational skills and dedication have been invaluable in
ensuring the smooth progress of the project.
I extend my heartfelt thanks specially to the head of the Department
of Electronic Dr. Harsupreet Kaur, for their support and
encouragement. Their visionary leadership and commitment to
academic excellence have created an inspiring learning environment
for students.
I would also like to express my gratitude to the faculty members of the
Department of Electronic, University of Delhi for their knowledge
sharing and providing a conducive academic environment for learning
and exploration.

Sujal Jain

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 Abstract

Gallium nitride (GaN) is a semiconductor material that has gained significant

attention in recent years due to its unique properties and numerous
applications in various industries.
Gallium nitride (GaN) semiconductors offer significant benefits in high-
temperature and high-frequency power electronic devices due to their
distinctive characteristics. These include a wide bandgap, high electron
saturation velocity, strong breakdown field, and high electron conductivity of
the two-dimensional electron gas (2DEG) in AlGaN/GaN heterostructures.
This study focuses on the design and analysis of a Gallium Nitride (GaN) FinFET
for high-power applications. The gate oxide stack consists of Bati03 oxide
stacked with SiO2, Al2O3, and HfO2. The main objective of this research is to
assess the compatibility of the gate oxide stack with the GaN FinFET structure
Gate oxide stacked FinFET are the better choice for higher drive current,
reasonable leakage current, good transconductance and excellent RF
performance at the same time.
Overall, this research presents a comprehensive study on the design of a GaN
FinFET for high-power applications. The investigation covers the compatibility
of the Bati03 oxide stack with GaN, as well as the analysis of electrical
characteristics with length variation. The findings of this study will contribute
to the development of high-performance GaN-based devices for power
electronics applications.

Keywords : Cut-off frequency (Ft), Transconductance (gm) , Drain Current (ID),

Drain to Source Voltage (Vds ), Gate To Source Voltage (Vgs), Micro (µ),

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 Table of Content
Page no :
Certificate………………………………………………………………………………….…………………………….…….…2
Declaration………………………………………………………………..…………………………………….………..…….3
Acknowledgment…………………………………………………………………………....………………………….……4
Abstract………………………………………………………………………..………………………………….………….....5
List of Figure………………………………………………………………….……………………………………...………...7
CHAPTER 1 INTRODUCTION………………………………………………………………………..……...……….9-37
1.1 Origin of MOSFET……………………………………………………………………………………..…………………….9
1.2 Need of MOSFET………………………………………………………………………………………..
………………….10
1.1 Structures of Mosfet………………………………………………………..………….……………………..…….…
11
1.2 Short Channel Effect……………………………………..…………………………………………….
……………....16
1.3 Gate Engineering……………………………………………………………..…………………………….……………22
1.4 GaN crystal structure and electrical properties……………………………………………….….
………...23
1.5 BaTiO3 crystal structure and electrical properties……………………………………..…….….….……
28
1.6 FinFet /multigate mosfet Technology……………………………………..…………….…………….
………..31
1.7 Advantages of Finfet………………………………………………………………….……………………………..
….34
1.8 Conclusion…………………………………………………………..…………..……………………………..………....37
CHAPTER 2 3D Modelling for FinFET………………………..…………..………………………….…………38-49
2.1 Proposed analytical model………………………………..………………..……………….
……………………..38
2.2 Surface potential…………………………………………………………………..…………….………………..
…….49

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CHAPTER 3 Gate Stacked GaN-FinFET with BaTiO3 Oxide for High Performance and High
Power Applications……………. …………………………………….……….……………….…………………….50-58
3.1 Purpose of simulation…………………………………………………….………………….……………..….
…….50
3.2 3 D structure of finfet.………………………………..….….……………..………………..
………………….......51
3.3 Simulation Results…………………………………………………..…..………………..…………………..
……….51
CHAPTER 4 Conclusion and Future Scope………………………………………………..……………….…59-
60
References………………………………………………………..………………….…………….………………..………..61
Appendix……………………………………………….………………………..………………….……………….………..64

List of Figures

S.No Figure Page

No
1 Fig 1.1 Classical structure of MOSFET 8
2 Fig 1.2 Biaxial (left) vs. Uniaxial (right) Strain Techniques 10

3 Fig 1.3 (a) Triple gate FinFET (b) pi-gate FinFET (c) omega gate 11
FinFET

4 Fig 1.4 A typical circular nanowire FET with its cross-sectional 12

view.
5 Fig 1.5 The energy band diagram of a MOSFET, b TFET for ON- 12
state and OFF-state conditions, and c comparative transfer
characteristics of well-designed MOSFET and TFET. c Schematic
representation of BTBT in the tunneling junction of TFET.
6 Fig 1.6 Threshold voltage of MOSFET versus channel length 14
7 Fig 1.7 Drain-induced barrier lower in mosfet 15
8 Fig 1.8 (a) gate stack in FinFET (b) multiple material gate in 21
FinFET

9 Fig 1.9 Crystal structure of (a) Wurzite GaN and (b) Zinc-blende 24
GaN

10 Fig 1.9 Structure of cubic BaTiO3. The red spheres are oxide 25
centres, blue are Ti4+ cations, and the green spheres are Ba2+.

7
11 Fig 1.10 Construction of (a) SOI FinFET and (b) Bulk FinFET. 29

12 Fig 1.11 π-gate and Ω-gate structure of FinFET 30

13 Fig 2.1 FinFET structure having length, width, and height in x, z 36
and y direction respectively where L G is gate length, Wfin is
width of FinFET and Hfin is height of FinFET

14 Fig 2.2 Surface potential with different channel lengths for SiO2 46
gate oxide with device parameter: Wfin = 5 nm, Hfin = 20 nm at
y = Hfin/2 , z = Wfin/2 position, Vd = 0V.
15 Fig 3.1 3D finfet structure gate length(L g)=1µm, fin 50
width(Wfin)=0.5 µm, fin height(Hfin)=1 µm

16 Fig 3.2 Surface Potential versus gate length 50

17 Fig 3.3 drain current versus gate voltage at drain voltage of 5 51

volts

18 Fig 3.4 drain current versus drain voltage at gate voltage of 3 51

volts

19 Fig 3.5 Transconductance versus gate voltage for oxide stack of 52

HfO2, Al2O3, and SiO2 with BaTiO3

20 Fig 3.6 gate to source capacitance versus gate voltage for oxide 52
stack of HfO2, Al2O3, and SiO2 with BaTiO3

21 Fig 3.7 gate to drain capacitance versus gate voltage for oxide 53
stack of HfO2, Al2O3, and SiO2 with BaTiO3

22 Fig 3.8 Cut-off frequency versus gate voltage for oxide stack of 53
HfO2, Al2O3, and SiO2 with BaTiO3

23 Fig 3.10 (a) input reflection coefficient (S11) versus gate voltage 56
(b) reverse voltage gain (S12) versus gate voltage (c) forward
voltage gain (S21) versus gate voltage (d) output reflection
coefficient (S22) versus gate voltage

24 Fig 3.11 (a) input impedance (H11) versus gate voltage (b) 57
forward current gain (H21) versus gate voltage

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 CHAPTER : 1
INTRODUCTION
Origin of MOSFET
The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) was invented in the late
1950s by a team of researchers at Bell Labs, led by Dawon Kahng and Martin Atalla. Atalla is
widely credited with the development of the MOSFET.
The origins of the MOSFET can be traced back to the earlier development of the Metal-
Oxide-Semiconductor (MOS) structure by Egyptian engineer Mohamed M. Atalla in the late
1950s. Atalla recognized the potential of using a thin layer of silicon dioxide (SiO2) as a
stable insulating layer between a metal gate electrode and a semiconductor material, such
as silicon.
Atalla's MOS structure was a significant advancement over the existing technology at the
time, which primarily used metal gates with thicker insulating layers that suffered from high
leakage currents and poor performance. The introduction of the silicon dioxide layer
provided improved insulation, lower leakage, and better control over the channel current in
the semiconductor material.
Building upon Atalla's MOS structure, the team at Bell Labs, including researchers John
Atalla, John McCaldin, and their supervisor, Dawon Kahng, further developed the concept by
introducing the concept of a "field-effect" transistor. They demonstrated that by applying a
voltage to the metal gate electrode, they could control the flow of current through the
semiconductor channel beneath it.

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In 1960, the team filed a patent for the MOSFET, and it was granted in 1963. The MOSFET
quickly gained attention for its advantages over other transistor technologies of the time,
such as the bipolar junction transistor (BJT). MOSFETs offered low power consumption, high
input impedance, and the ability to integrate large numbers of transistors on a single chip,
paving the way for the development of modern integrated circuits (ICs).
Since its invention, the MOSFET has undergone numerous advancements, leading to various
subtypes and improved performance characteristics. Today, MOSFETs are the most widely
used transistor technology in the semiconductor industry, forming the foundation of modern
digital electronics and playing a crucial role in devices such as microprocessors, memory
chips, and power amplifiers.

Need Of MOSFET
The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a fundamental
component in modern electronics and has several key advantages that make it essential in
many applications. Here are some of the primary reasons for the widespread use and need
for MOSFETs:
1. Switching and Amplification: MOSFETs are excellent for switching and amplifying
electronic signals. They can effectively control the flow of current through a
semiconductor channel by varying the voltage applied to the gate terminal. This
property makes them essential for various digital and analog applications, including
logic circuits, power amplifiers, audio systems, and communication devices.
2. Low Power Consumption: MOSFETs are known for their low power consumption
compared to other transistor technologies, such as bipolar junction transistors (BJTs).
In digital circuits, MOSFETs operate in a voltage-driven mode, meaning they consume
power only during state transitions, resulting in efficient power utilization. This
characteristic is crucial for portable devices, battery-powered electronics, and
energy-efficient applications.
3. High Integration Density: MOSFETs enable high integration density on
semiconductor chips. Their small size and ability to be scaled down allow for the
fabrication of densely packed transistors on integrated circuits (ICs). This capability
has led to the development of complex microprocessors, memory chips, and other
integrated circuits with millions or even billions of MOSFETs on a single chip.
4. Noise Immunity: MOSFETs offer high immunity to noise and interference. Due to
their insulated gate structure, MOSFETs are less susceptible to electromagnetic
interference and can maintain signal integrity even in noisy environments. This
feature is crucial in applications where signal quality and reliability are essential, such
as communication systems and data transmission.
5. Voltage Compatibility: MOSFETs can operate at various voltage levels, ranging from
low voltages (e.g., a few volts) to high voltages (hundreds of volts or more). This
versatility makes them suitable for a wide range of applications, including consumer
electronics, power electronics, automotive systems, and industrial equipment.

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 6. Scalability and Manufacturing Efficiency: MOSFETs have undergone continuous
advancements and scaling down in size, enabling higher transistor density and
improved performance. These advancements, along with mature manufacturing
processes, have made MOSFETs cost-effective and readily available for mass
production, supporting the growth of the semiconductor industry.

Structure of Mosfets
There are two types of structure in mosfet
 Classical structure
 Non-classical structure
Classical structure of Mosfet

Fi
g 1.1 Classical structure of mosfet
Source: Capacitance Optimization and Ballistic Modeling of Nanowire
Transistors
The classical structure of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)
consists of three main regions: the source, the drain, and the channel. The channel is the
region where the current flows, and it is controlled by the voltage applied to the gate
terminal. Let's explore each component in more detail:
1. Source: The source terminal is where the current enters the MOSFET. It is typically
heavily doped with a specific type of impurity to facilitate the flow of charge carriers
(electrons for n-channel MOSFETs or holes for p-channel MOSFETs) from the source
to the channel.

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 2. Drain: The drain terminal is where the current exits the MOSFET. Similar to the
source, it is also heavily doped to enhance the current flow in the opposite direction
of the source. The drain is typically maintained at a higher voltage than the source
for proper operation of the MOSFET.
3. Channel: The channel is the region between the source and the drain where the
current flows. It is formed by a thin layer of semiconductor material, such as silicon,
and is isolated from the gate terminal by a layer of insulating material called gate
oxide. The conductivity of the channel can be controlled by applying a voltage to the
gate terminal.
4. Gate: The gate terminal is separated from the channel by the gate oxide and is
responsible for controlling the conductivity of the channel. By applying a voltage to
the gate terminal, an electric field is created across the gate oxide, which modulates
the charge carrier concentration in the channel, thereby controlling the flow of
current.
In summary, the classical structure of a MOSFET comprises the source and drain regions,
connected by a channel that can be controlled by the voltage applied to the gate terminal.
This arrangement allows the MOSFET to function as a voltage-controlled switch or amplifier
in electronic circuits.

Non-classical structure
The classical structure of a MOSFET is based on the basic principles and design that have
been widely used for many years. However, there have been advancements and variations in
MOSFET structures to improve their performance and address specific requirements. Some
of the non-classical structures of MOSFETs include:
1. High-K Gate Dielectric:
In the classical MOSFET, the gate oxide is typically made of silicon dioxide (SiO2).
However, non-classical MOSFETs use high-k dielectric materials with higher dielectric
constants than SiO2. High-k gate dielectrics help reduce gate leakage current and
allow for the further scaling of MOSFETs while maintaining good control over the
channel.
2. Strained-Silicon MOSFETs:
In strained-Silicon MOSFETs, a layer of silicon is grown on a substrate with a different
lattice constant, causing strain in the silicon crystal lattice. This strain modifies the
band structure of silicon, improving carrier mobility and hence enhancing MOSFET
performance.

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 Fig 1.2 Biaxial (left) vs. Uniaxial (right) Strain Techniques
Source: The Invention of Uniaxial Strained Silicon Transistors at Intel

3. FinFETs (Tri-Gate MOSFETs):

FinFETs are non-classical MOSFETs that feature a three-dimensional channel
structure instead of the traditional planar channel. The channel is formed by a thin,
vertical silicon fin surrounded by gate material on three sides, providing better
electrostatic control and reduced leakage current. FinFETs offer improved
performance and scalability compared to planar MOSFETs.

13
 Fig 1.3 (a) Triple gate FinFET (b) pi-gate FinFET (c) omega gate FinFET
Source: Basics of Compact Model Development by: Sivakumar P
Mudanai
4. Nanowire MOSFETs: Nanowire MOSFETs are MOSFETs with channel regions that are
constructed using semiconductor nanowires, such as silicon or III-V compound
semiconductors. These nanowires have diameters in the nanometer range and offer
advantages such as better electrostatic control, reduced short-channel effects, and
improved performance.

Fig 1.4 A typical circular nanowire FET with its cross-sectional view.
Source : Gate length scaling of Si nanowire FET: A NEGF study
5. Tunnel FETs (TFETs): Tunnel FETs are a type of non-classical MOSFET that utilize
quantum tunneling for current flow. Unlike classical MOSFETs that rely on the
modulation of charge carriers in the channel, TFETs operate by tunneling electrons or
holes through a barrier. TFETs have the potential for low-power operation due to
reduced subthreshold slope and are being explored for energy-efficient applications.

14
Fig 1.5 The energy band diagram of a MOSFET, b TFET for ON-state and OFF-state
conditions, and c comparative transfer characteristics of well-designed MOSFET and TFET.
c Schematic representation of BTBT in the tunneling junction of TFET.
Source : 2D materials-based nanoscale tunneling field effect transistors: current
developments and future prospects
These non-classical MOSFET structures demonstrate advancements and innovations in
device design, materials, and fabrication techniques, aiming to overcome limitations of
classical MOSFETs and achieve improved performance, reduced power consumption, and
enhanced scalability in modern electronic devices.

Short Channel Effects

The gate length (Lg) of a MOSFET represents the physical length of the gate, while the actual
channel length (L) is obtained by subtracting the lateral diffusions of the source and drain
junctions from Lg. Lg is typically greater than L, and L tracks Lg, although the precise
difference (Lg − L) cannot be precisely quantified. In order to increase operational speed and
accommodate more components per chip, the channel length L is continuously reduced.
When the channel length is reduced to a certain extent, the short-channel effects occur.
These effects are named as such because they explicitly arise due to the shortened channel
length. A short channel is defined when the channel length becomes comparable to the
widths of the depletion layers (xdD, xdS) surrounding the drain and source junctions. Short-
channel effects refer to the changes in behavior that occur in a MOSFET with a short channel
compared to a long-channel MOSFET.
The short-channel effects arise due to several factors. Firstly, high electric fields are
generated in the channel region. Secondly, the two-dimensional potential distribution in this

15
region, influenced by the transverse field Ex controlled by the gate voltage and the bias
applied to the back surface, plays a role. Additionally, the longitudinal field Ey resulting from
the drain bias also contributes. The two-dimensional potential distribution affects the
threshold behavior of the device, causing the threshold voltage (VTh) to depend on the
channel length and biasing voltages. This variability in VTh with device dimensions and
biasing voltages can be concerning for circuit designers who prefer stable and predictable
behavior.

Threshold Voltage Roll-off

As the channel length of a MOSFET decreases, the amount of bulk charge terminating on the
gate electrode also decreases. This reduction in charge leads to a decrease in the threshold
voltage. To understand this reduction, let's consider that the formation of an inversion layer
beneath the gate dielectric is preceded by the depletion of this region up to a depth
represented by Wd. The responsibility for this depletion is shared by the gate, source, and
drain. While the gate contributes significantly to the depletion, the source and drain
junctions also play a role. These junctions assist in balancing a small portion of the depletion
layer charge, effectively reducing the amount of gate charge required for depletion. This
reduction in gate charge due to source and drain effects leads to a decrease in the threshold
voltage (DVTh). In long-channel MOSFETs, DVTh is negligible, but it becomes noticeable in
short-channel devices. Moreover, even in the same wafer or die, transistors with different
channel lengths will have different threshold voltages. This reduction in threshold voltage
due to decreased channel length is known as VTh roll-off.

Fig 1.6 Threshold voltage of mosfet versus channel length

Source : Design optimization of gate-all-around (GAA) MOSFETs
Drain-Induced Barrier Lowering (DIBL)

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Another effect that occurs in short-channel MOSFETs is drain-induced barrier lowering
(DIBL). DIBL refers to the decrease in threshold voltage caused by high drain voltages. It
arises from the electrostatic coupling between the drain and the source. This coupling leads
to the depression of the potential barrier at the source-to-channel junction, allowing
electrons to be more easily injected into the channel region. Consequently, the transistor
requires less gate voltage to deplete the substrate beneath the gate dielectric, resulting in a
decrease in the threshold voltage. DIBL occurs more prominently in short-channel devices
due to the relatively pronounced charge sharing effect between the channel depletion
region and the source/drain depletion regions, compared to long-channel devices.

Fig 1.7 Drain induced barrier lower in mosfet

Source: MOSFET(5) - Vt roll-off, drain-induced barrier lowering (DIBL), FinFET
structure
In a classical long-channel MOSFET, the barrier at the source end is situated far away from
the drain contact and is electrostatically shielded from the drain by the combination of the
substrate and gate voltages. As a result, the threshold voltage remains independent of the
drain voltage. However, in the presence of source and drain effects, the depletion region
formed by the gate takes on a trapezoidal shape instead of the rectangular shape observed
in the absence of these effects.
In summary, the decrease in channel length of a MOSFET leads to a reduction in bulk charge
on the gate, resulting in a decrease in the threshold voltage. This reduction is caused by
source and drain effects, as well as drain-induced barrier lowering. These effects affect the
control of the gate over the channel current and can lead to variations in threshold voltage
between transistors with different channel lengths.
Velocity Saturation
When the gate length of a MOSFET is reduced to smaller values, the longitudinal electric
field (Ex) between the source and drain increases significantly. The carrier velocity (vd) of the
electrons or holes in the channel depends on this electric field. At low values of Ex, the
carrier velocity is proportional to Ex. However, as Ex exceeds certain thresholds (3x10^4
V/cm for electrons and 10^5 V/cm for holes), the proportionality relationship is no longer
valid.

17
At higher values of Ex, the carrier velocity saturates at specific values: vsat = 10 7 cm/s for
electrons and vsat = 6x106cm/s for holes. This saturation occurs due to increased scattering
of carriers at high electric fields. The scattering events limit the carrier mobility and prevent
further acceleration, resulting in a constant carrier velocity.
Due to the saturation of carrier velocity, the current through the MOSFET (IDS) is no longer a
quadratic function of the gate-to-source voltage (VGS). Instead, IDS increases linearly with
(VGS - VTh), where VTh represents the threshold voltage. It is important to note that this
saturation behavior is independent of the channel length.
IDsat=Vsat W Cox (Vds-Vth)
As a consequence of the saturation effect, the short-channel MOSFET exhibits a lower
saturation current compared to a long-channel MOSFET. This reduction in current drive
capability is one of the challenges faced in short-channel MOSFET designs. Additionally, the
short-channel MOSFET saturates at a lower drain-to-source voltage (VDS) value, limiting the
maximum voltage at which the device can operate.
Impact Ionization
In a short-channel NMOS transistor, the large longitudinal electric field accelerates electrons
to high velocities, causing them to collide with silicon atoms. These collisions result in the
liberation of electrons from the outermost shells of the silicon atoms. These newly released
electrons also acquire high velocities and participate in subsequent collisions, generating
additional electron-hole pairs.
The electrons that are ejected from their original positions are attracted to the drain
terminal, while the resulting holes move towards the P-substrate region. This process sets
off a chain reaction, leading to an avalanche of free carriers. The overall behavior resembles
that of an NPN transistor, where the N+-source-P-substrate-N+-drain configuration acts as a
transistor structure.
If the aforementioned holes are collected by the source terminal and the resulting hole
current creates a voltage drop in the substrate, the source-substrate junction becomes
forward-biased. As a result, electron injection starts from the source and flows into the
substrate. These injected electrons can then move towards the drain, further creating
electron-hole pairs and exacerbating the situation.
This multiplication process, driven by the large electric field, can lead to a significant
increase in the number of carriers in the device, causing potential reliability and
performance issues. It is one of the challenges associated with short-channel MOSFETs and
needs to be carefully considered in their design and operation.
Hot Carrier Effects
As the feature size of MOSFET devices decreases, the electric field in their channel regions
increases. This high electric field can accelerate charged particles, either electrons or holes,
to very high kinetic energies, resulting in what is known as hot carriers. These hot carriers

18
have significantly higher energies compared to typical carriers found in semiconductor
devices.
Due to their high energies, hot carriers have the ability to migrate into and move around
areas of the device where they are not intended to be, such as the gate dielectric and
substrate of a transistor. Their presence in these unintended regions can lead to undesirable
effects, including shifts in the threshold voltage of the device and degradation of its
transconductance, which is a measure of its ability to amplify signals.
Hot carrier injection is typically more severe in N-channel MOSFETs compared to P-channel
devices. This is because electrons, being negatively charged carriers, have higher mobility
than holes in the semiconductor material. As a result, electrons acquire higher energies and
become hotter compared to holes. Additionally, the energy barrier for electrons to traverse
certain regions is lower than that for holes, making electron-induced hot carrier effects more
significant in N-channel devices.
These hot carrier effects need to be carefully considered and mitigated in the design and
operation of MOSFET devices, especially as the feature sizes continue to shrink. Techniques
such as device engineering, material selection, and process optimization are employed to
minimize the impact of hot carriers and ensure the reliable and efficient operation of the
devices.

Substrate Hot Electron (SHE) Injection

When the substrate or body of a MOSFET is subjected to excessively high positive or
negative voltages, it can trigger a phenomenon called substrate hot electron (SHE) injection.
This occurs due to the intense electric field within the substrate, which propels charge
carriers of one type (either electrons or holes) towards the interface between the silicon (Si)
substrate and the silicon dioxide (SiO2) gate oxide.
As these charge carriers move through the substrate under the influence of the substrate
field, they gain significant kinetic energy. Subsequently, they are forcefully propelled into the
SiO2 layer adjacent to the interface, a process known as SHE injection.
However, the injection of these high-energy charge carriers into the SiO2 layer can have
adverse effects on the MOSFET device's performance and reliability. It can cause damage to
the gate oxide, resulting in threshold voltage shifts, degradation of device characteristics,
and even potential device failure.
To prevent or mitigate SHE injection, various design techniques are employed. These include
optimizing device structures, selecting appropriate materials, and implementing robust
fabrication processes. By implementing these measures, MOSFET devices can maintain
reliable and stable operation, even under conditions of extremely high voltage stress.
Channel Hot Electron (CHE) Injection

19
When both VGS and VDS are very high, some electrons are driven toward the gate oxide.

Gate Engineering
Gate engineering in MOSFET refers to the deliberate modification of the gate structure and
composition to enhance the device's performance and optimize its operation. The gate
region of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) plays a crucial role
in controlling the flow of current between the source and drain terminals by manipulating
the voltage applied to the gate.
Gate engineering involves several techniques and strategies to improve the transistor's
electrical characteristics and overall performance. Some common approaches in gate
engineering include:
1. Gate Oxide Thickness: Modifying the thickness of the gate oxide layer can influence
the device's threshold voltage, capacitance, and leakage current. A thinner oxide
layer can increase device speed but may also result in higher leakage. On the other
hand, a thicker oxide layer may reduce leakage but can adversely impact the device's
speed.
2. Gate Dielectric Materials: Choosing suitable gate dielectric materials, such as silicon
dioxide (SiO2), high-k dielectrics (e.g., HfO2, Al2O3), or their combinations, can affect
the device's capacitance, threshold voltage, and leakage current. High-k dielectrics
allow for thicker gate oxides, reducing leakage while maintaining desirable
capacitance.

20
 3. Gate Electrode Materials: Selecting appropriate gate electrode materials, such as
polysilicon, metal, or their combinations, can influence the device's resistance,
threshold voltage, and work function. Different materials offer varying levels of
performance in terms of current handling, speed, and thermal stability.
4. Gate Doping: Modulating the doping concentration in the gate region can affect the
transistor's threshold voltage, subthreshold slope, and overall performance.
Adjusting the doping level allows for control over the device's electrical
characteristics.
5. Gate Length Scaling: Reducing the gate length helps improve transistor performance
by enhancing switching speed, reducing resistance, and decreasing parasitic
capacitance. Gate length scaling is a fundamental aspect of technology scaling and is
crucial for achieving higher transistor density and improved performance in
integrated circuits.
By employing gate engineering techniques, MOSFET designers can optimize the transistor's
performance for specific applications, balancing factors such as speed, power consumption,
leakage current, and reliability.
One important aspect of gate engineering is the choice of gate dielectric material. Traditional
MOSFETs utilize silicon dioxide (SiO2) as the gate dielectric, but as technology advances and
gate lengths shrink, alternative high-k dielectric materials, such as hafnium dioxide (HfO2) or
aluminum oxide (Al2O3), are employed. These high-k dielectrics have higher dielectric
constants, allowing for better control of the gate voltage and reducing gate leakage currents.
Another aspect of gate engineering is the optimization of the gate electrode. The gate
electrode material, typically polysilicon or metal, affects the gate resistance, capacitance,
and work function, which impact the device's threshold voltage, switching speed, and power
consumption. The choice of gate electrode material is determined by factors such as
compatibility with the fabrication process, work function engineering for optimal device
performance, and resistance to electromigration.
Additionally, advanced gate engineering techniques include strain engineering, where the
lattice structure of the silicon substrate is modified to introduce strain and enhance carrier
mobility, and dual or multiple gate designs, such as FinFETs or nanowire transistors, which
offer improved control of the channel and reduced leakage currents.
Overall, gate engineering plays a crucial role in the development of high-performance
MOSFETs. It aims to optimize the gate region's materials, structure, and properties to
enhance device characteristics, improve power efficiency, and enable the continued scaling
of transistor technology.

21
 (a)

(b)
Fig 1.8 (a) gate stack in FinFET (b) multiple material gate in FinFET
Source : (a) Interfacial layer dependence of High-K gate stack based Conventional tri-gate
FinFET concerning analog/RF performance (b) TCAD Simulation Study of Single-, Double-,
and Triple-Material Gate Engineered Trigate FinFETs

22
Gallium Nitride Structure and Electrical Properties
Gallium Nitride
Gallium nitride (GaN) has emerged as a promising material for power applications due to its
unique properties that make it well-suited for high-power and high-frequency devices. Here
are some key reasons why GaN is considered advantageous for power applications:

Wide Bandgap: GaN possesses a wide bandgap of approximately 3.4 electron volts (eV),
which is significantly larger than conventional silicon (Si) and even silicon carbide (SiC). The
wide bandgap enables GaN devices to operate at higher voltages, leading to lower power
losses and higher energy efficiency. GaN-based power devices can handle high breakdown
voltages, allowing them to operate in demanding power conversion applications.

23
High Electron Mobility: GaN exhibits high electron mobility, which refers to how quickly and
efficiently electrons can move through the material. This high mobility allows for faster
switching speeds in GaN power devices, reducing switching losses and enabling higher
frequency operation. GaN-based devices can switch on and off more rapidly, resulting in
improved power conversion efficiency and reduced power dissipation.

Low On-Resistance: GaN devices offer low on-resistance, meaning they can achieve high
current-carrying capabilities while minimizing power losses. The low on-resistance is a result
of GaN's material properties and the ability to design GaN-based power transistors with low
channel resistance. GaN power devices can handle higher current densities, leading to
smaller and more compact device designs.

High Thermal Conductivity: GaN possesses excellent thermal conductivity, allowing for
efficient heat dissipation. This is crucial in power applications where high power densities
generate heat. GaN-based power devices can handle high temperatures without significant
degradation, leading to improved reliability and longer device lifetimes.

Reduced Switching Losses: GaN devices exhibit minimal switching losses due to their fast
switching speed and low capacitance. The low capacitance allows for faster charging and
discharging of the device, resulting in reduced energy losses during switching transitions.
GaN-based power devices are particularly advantageous in applications requiring high-
frequency switching, such as wireless power transfer and RF power amplifiers.

Overall, GaN's wide bandgap, high electron mobility, low on-resistance, high thermal
conductivity, and reduced switching losses make it highly suitable for power applications.
GaN-based power devices have the potential to deliver higher efficiency, higher power
density, and increased operating frequency, enabling more energy-efficient power
electronics systems across various industries, including automotive, renewable energy,
consumer electronics, and telecommunications.
Structures of Gallium Nitride
Gallium nitride (GaN) is a well-known and extensively studied compound with several crystal
structures, depending on the growth conditions and substrate used. The most common
crystal structures of GaN are hexagonal wurtzite and cubic zinc-blende.

Hexagonal Wurtzite Structure: This is the most commonly observed structure for GaN. In
the wurtzite structure, GaN forms a hexagonal lattice. The lattice consists of alternating
gallium (Ga) and nitrogen (N) atoms, with each gallium atom bonded to three neighboring

24
nitrogen atoms and vice versa. The wurtzite structure exhibits a strong polarity along the c-
axis due to the difference in electronegativity between gallium and nitrogen atoms.

Cubic Zinc-Blende Structure: Under certain growth conditions, GaN can also adopt a cubic
zinc-blende structure, similar to that of diamond. In this structure, each gallium atom is
bonded to four nitrogen atoms, and each nitrogen atom is bonded to four gallium atoms.
The cubic structure has a higher symmetry compared to the wurtzite structure and does not
exhibit polarity.

Fig 1.9 Crystal structure of (a) Wurzite GaN and (b) Zinc-blende GaN
Source : Gallium nitride nanostructures: Synthesis, characterization and applications
It is worth noting that GaN can also exist in other crystal structures, such as the cubic rock
salt structure and the rhombohedral structure. However, these structures are less commonly
observed and are typically obtained under specific growth conditions or when GaN is alloyed
with other elements.

The choice of crystal structure has a significant impact on the properties and applications of
GaN. For example, wurtzite GaN is often preferred for optoelectronic devices such as light-
emitting diodes (LEDs) and laser diodes, while cubic GaN is more suitable for certain
electronic applications.

In recent years, the development of GaN-based heterostructures, such as AlGaN/GaN and

InGaN/GaN, has further expanded the range of applications and functionalities of GaN-
based devices, enabling high-performance electronics and optoelectronics.

25
BaTiO3 Structure and Electrical Properties
Introduction to BaTiO3
Barium titanate (BaTiO3) is an inorganic compound that belongs to the perovskite family of
materials. It is widely recognized for its unique ferroelectric properties and has been
extensively studied for its applications in various fields, including electronics,
telecommunications, and energy storage.
Structure:
The solid exists in one of four polymorphs depending on temperature. From high to low
temperature, these crystal symmetries of the four polymorphs are cubic, tetragonal,
orthorhombic and rhombohedral crystal structure. All of these phases exhibit the
ferroelectric effect apart from the cubic phase. The high temperature cubic phase is easiest
to describe, as it consists of regular corner-sharing octahedral TiO6 units that define a cube
with O vertices and Ti-O-Ti edges. In the cubic phase, Ba2+ is located at the center of the

26
cube, with a nominal coordination number of 12. Lower symmetry phases are stabilized at
lower temperatures and involve movement of the Ti4+ to off-center positions. The
remarkable properties of this material arise from the cooperative behavior of the Ti4+
distortions.

Fig 1.9 Structure of cubic BaTiO3. The red spheres are oxide centres, blue are
Ti4+ cations, and the green spheres are Ba2+.
Source : Barium titanate wikipedia
Above the melting point, the liquid has a remarkably different local structure to the solid
forms, with the majority of Ti4+ coordinated to
Ferroelectric Properties:
Barium titanate exhibits a spontaneous electric polarization that can be reversed by the
application of an external electric field, making it a ferroelectric material. This polarization
arises due to the reorientation of the TiO6 octahedra in response to an electric field. The
ability to switch the polarization direction makes barium titanate valuable for various
electronic applications.
Dielectric Properties:
Barium titanate is known for its high dielectric constant (εr), which refers to its ability to
store electrical energy in an electric field. The dielectric constant of barium titanate can vary
depending on factors such as temperature, crystal orientation, and frequency of the applied
electric field. At room temperature, the dielectric constant of barium titanate is typically in
the range of 1000 to 3000, but it can reach values as high as 10,000 at certain temperatures.
Dielectric Loss:

27
 Barium titanate also exhibits low dielectric losses, indicated by a low tangent of the
dielectric loss angle (tan δ). Low dielectric losses are desirable in applications where high
efficiency and minimal energy dissipation are required.
Curie Temperature:
Barium titanate undergoes a phase transition at a specific temperature called the Curie
temperature (Tc). Above this temperature, the material loses its ferroelectric properties and
becomes paraelectric. The Curie temperature of barium titanate is approximately 120°C, but
it can be modified through doping or composition adjustments.
Temperature Dependence:
The dielectric properties of barium titanate, such as the dielectric constant and dielectric
loss, are temperature-dependent. These properties can exhibit anomalies or peaks at
specific temperatures associated with structural phase transitions.
Applications:
Barium titanate finds numerous applications due to its ferroelectric and dielectric properties.
It is commonly used in capacitors, where its high dielectric constant enables increased
energy storage capacity. Barium titanate is also utilized in electromechanical transducers,
such as piezoelectric actuators and sensors, where its ability to convert electrical energy into
mechanical motion is valuable. Additionally, it has applications in nonlinear optics, optical
modulators, and memory devices.
In summary, barium titanate is a ferroelectric material with remarkable dielectric properties,
including a high dielectric constant and low dielectric losses. Its ability to switch polarization
and store electrical energy makes it suitable for various electronic and energy storage
applications. Understanding the dielectric properties of barium titanate is crucial for
harnessing its potential in different fields of science and technology.

FinFet/Multi-gate MOSFET Technology

A FinFET is a specific type of multi-gate Metal-Oxide-Semiconductor Field-Effect Transistor

(MOSFET) that was first developed at the University of California, Berkeley by Chenming Hu
and his colleagues. Unlike traditional MOSFETs with a single gate, a FinFET incorporates
multiple gates into a single device, resulting in improved performance and reduced leakage
current.
The name "FinFET" is derived from its unique structure, which resembles a set of fins when
viewed from above. The body of a FinFET consists of a thin silicon film that wraps around the

28
conducting channel, forming multiple vertical fins. The thickness of the device determines
the effective channel length, which is the distance between the source and drain junctions.
There are two main types of FinFETs: Bulk FinFETs and Silicon-On-Insulator (SOI) FinFETs.
1. Bulk FinFET: The Bulk FinFET is based on a traditional bulk silicon wafer substrate.
The fins and the gate material are formed on top of the silicon substrate, and the
device operates on the bulk silicon. It offers improved electrostatic control and
reduced short-channel effects compared to planar bulk MOSFETs.
2. SOI FinFET: The SOI FinFET is based on a Silicon-On-Insulator substrate, where a thin
layer of silicon is sandwiched between a silicon dioxide (SiO2) insulator layer and a
bulk silicon substrate. The fins and gates are formed on top of the thin silicon layer,
resulting in improved control over the channel and reduced leakage current.
Both types of FinFETs share the common feature of having multiple gates, which allows for
better control of the channel and improved transistor performance. FinFET technology has
become widely adopted in modern semiconductor manufacturing processes due to its
superior scalability, reduced power consumption, and improved transistor characteristics
compared to traditional planar MOSFET designs.

Fig 1.10 Construction of (a) SOI FinFET and (b) Bulk FinFET.
Source : Comparing FinFETs: SOI Vs Bulk: Process variability, process cost, and
device performance

π-gate and Ω-gate devices

The π-gate and Ω-gate devices are variations of the three-gate FinFET structure in which the
sidewall sections underneath the channel are extended, creating additional gate regions.
These modifications increase the effective number of gates from three to four, resulting in
enhanced electrostatic control and improved device performance.

29
In the π-gate device (Figure 5), the sidewall sections on either side of the channel are
elongated to form an additional gate region, resembling the shape of the Greek letter "π".
This extra gate provides additional control over the channel, allowing for improved
suppression of leakage currents and enhanced transistor performance.
Similarly, the Ω-gate device (Figure 6) extends the sidewall sections further, creating an
additional gate region that wraps around the channel in the shape of the Greek letter "Ω".
The Ω-gate structure offers even greater electrostatic integrity and control over the channel,
leading to improved device characteristics such as reduced leakage current and enhanced
switching speed.
Both the π-gate and Ω-gate devices are advanced variations of the FinFET architecture,
designed to overcome limitations of traditional three-gate FinFETs by providing additional
gates for better electrostatic control. These innovations contribute to the continuous
improvement of transistor performance, enabling the development of more efficient and
powerful integrated circuits in various electronic applications.

π-gate Ω-gate
Fig 1.11 π-gate and Ω-gate structure of FinFET
Source : A Comparison of FinFET Configurations

Advantage of Finfet Over planar mosfet and GAAFet

FINFET VS MOSFET
FinFETs offer several advantages over traditional MOSFETs, which contribute to improved
device performance and power efficiency. Here are some key advantages of FinFETs:
1. Better control of short-channel effects: As the channel length of MOSFETs continues
to shrink, short-channel effects become more pronounced, leading to reduced
control over the transistor behavior. FinFETs, with their three-dimensional fin-like
structure, provide improved control over these effects by effectively increasing the

30
 channel width. This results in reduced leakage current and enhanced electrostatic
control, allowing for better device performance even at smaller channel lengths.
2. Reduced subthreshold leakage: FinFETs exhibit significantly lower subthreshold
leakage current compared to traditional MOSFETs. The improved electrostatic control
provided by the three-dimensional fin structure helps in better suppression of
leakage current, resulting in lower power consumption and improved energy
efficiency.
3. Improved scalability: FinFETs have better scalability than MOSFETs, allowing for
continued device miniaturization and integration of more components on a single
chip. The three-dimensional structure of FinFETs provides enhanced control over the
channel, enabling the realization of smaller channel lengths without sacrificing
performance.
4. Lower power consumption: Due to their reduced leakage current and improved
electrostatic control, FinFETs consume less power compared to MOSFETs. This makes
them suitable for low-power applications, such as mobile devices and Internet of
Things (IoT) devices, where power efficiency is crucial.
5. Higher performance: FinFETs offer improved transistor performance, including faster
switching speed and higher drive current capabilities. The enhanced electrostatic
control and reduced leakage current contribute to faster and more efficient
operation, allowing for higher performance in digital circuits.
Overall, FinFETs provide better control over short-channel effects, lower leakage current,
improved scalability, lower power consumption, and higher performance compared to
traditional MOSFETs. These advantages make FinFETs a preferred choice for advanced
semiconductor technologies and enable the development of more efficient and powerful
electronic devices.
FINFET VS GAA-FET
Gate-All-Around Field-Effect Transistors (GAA-FETs) are a type of transistor architecture that
offers superior electrostatic control and reduced short-channel effects compared to
conventional FinFET or planar transistor structures. However, like any technology, GAA-FETs
can also have their own set of challenges. Here are a few common problems associated with
GAA-FETs:
1. Fabrication Complexity: GAA-FETs require complex manufacturing processes
compared to traditional transistor designs. The fabrication involves precise nanowire
patterning and gate material deposition, which can be challenging and expensive.
2. Scaling Limitations: Although GAA-FETs offer improved electrostatic control, scaling
them down to smaller dimensions becomes increasingly challenging. As the channel
dimensions shrink, issues like process variations, reliability, and leakage currents
become more prominent.

31
 3. Integration Challenges: Integrating GAA-FETs into existing semiconductor processes
and technologies can be a complex task. The compatibility with other components,
such as interconnects and memory cells, needs to be carefully addressed to ensure
optimal performance.

As the Gate all around is very new technology as compared to FinFET, So much research is
required to improve the electrical properties and overcome its problems and fabrication
complexity

CONCLUSION

In the previous chapter, we covered the fundamentals of MOSFETs and the challenges
associated with scaling down device parameters. We then explored the basic FinFET
technology, which has emerged as a promising solution to overcome these challenges.
FinFETs offer several advantages over traditional planar MOSFETs and gate-all-around

32
structures. These advantages include better control over short-channel effects, reduced
leakage current, improved electrostatic control, enhanced performance at lower supply
voltages, and higher drive current. The unique three-dimensional architecture of FinFETs
allows for better gate control and helps mitigate the issues faced by planar MOSFETs, making
them a compelling choice for advanced semiconductor devices..
In the upcoming chapters, we will delve deeper into the analytical model of FinFETs, which is
a crucial aspect in understanding their behavior and performance. We will explore how the
various parameters of FinFETs can be modeled analytically, enabling us to predict their
electrical characteristics accurately. Additionally, we will examine TCAD (Technology
Computer-Aided Design) simulation results for different gate oxide stack combinations. TCAD
simulations allow us to simulate the behavior of FinFETs under different operating conditions
and investigate the impact of various design parameters. By studying both the analytical
model and TCAD simulation results, we will gain valuable insights into the performance and
optimization of FinFET devices.

CHAPTER : 2
3D Modelling for FinFET
Proposed Analytical Model

33
The FinFET device consists of a silicon fin with a certain width (Wfin), height (Hfin), and
channel length (L). The device structure includes a gate electrode and a gate oxide layer on
top of the silicon body, where the gate oxide thickness is denoted as tox. Additionally, there
is a substrate thickness (toxb). In an ideal situation, the flat band voltage is considered to be
zero, and the surface potential is calculated accordingly.
To analyze the DG-FinFET device, both symmetric and asymmetric configurations are
considered. For the symmetric DG-FinFET, the analysis is done in the z and x directions, while
for the asymmetric DG-FinFET, it is done in the y and x directions.
The surface potential and threshold voltage of the DG-FinFET are determined by solving the
2-D Poisson's equation separately for the symmetric and asymmetric configurations. The
solutions obtained from these configurations are then combined using the perimeter-
weighted sum method to calculate the surface potential for the TG-FinFET.
It's important to note that the asymmetric DG-FinFET is considered in the x and y directions,
meaning the analysis takes into account the variations along these axes. On the other hand,
the symmetric DG-FinFET is considered in the y and z directions, focusing on variations in
these dimensions.
By employing the concept of DGMOSFET (Double-Gate Metal-Oxide-Semiconductor Field-
Effect Transistor), the potential distribution in the weak inversion region of the silicon
channel in the symmetric DG-FinFET can be expressed. This potential distribution helps in
understanding the behavior and characteristics of the device during weak inversion.

2 2
∂ ∅ ( z , x) ∂ ∅ (z , x) q N A
+ = (1)
∂ z2 ∂ x2 ε si

and for asymmetric DG-FinFET, the Poisson’s equation is,

2 2
∂ ∅ ( y , x) ∂ ∅ (z , x ) q N A
+ =
∂ y2 ∂ x2 ε si

34
 (2)

Fig 2.1 FinFET structure having length, width, and height in x, z and y direction respectively
where LG is gate length, Wfin is width of FinFET and Hfin is height of FinFET

(i) Surface potential for symmetric gates

2
∅ ( z , y )=C 0 ( x ) +C 1 ( x ) z+C 2 ( x ) z (3)

(ii) Surface potential for asymmetric gates

2
∅ ( x , y )=C 0 ( x ) +C 1 ( x ) y+ C2 ( x ) y (4)

The coefficients C0, C1 and C2 are the function of x only. Due to symmetric configuration,
the forward-facing potential ∅ (0, x) and back potential ∅ (Wfin, y) are considered as same. So,
∅ s(y) = ∅ (0, x) = ∅ (Wfin, x). Applying Gauss’s law, boundary conditions of the electric field at
the channel and oxide interface can be written as,

,z = 0 (5)

,z = Wfin (6)

Vg’ = Vg – Vfb

35
Vfb = ∅ ms -
kT
q
N
ln A
kT( )
Vfb = flat band voltage
∅ ms=metal semiconductor work function

kT
Vth = q

Vg = Voltage at front and back gates of symmetric structures

tox = thickness of oxide
ε ox= permittivity of oxide

Applying boundary condition (5),(6) on (3)

∅ ( 0 , x )=C 0 ( x )=∅ s (7)
∂ ∅ (z , x)
=C 1+ 2C 2 z (8)
∂z
At z=0

(8.1)
At z=W fin

(8.2)

(9)

36
 (10)

(11)

(12)

37
(12.1)

(12.2)

38
39
(15.3)

40
(19)

41
42
43
asymmetric and symmetric DG-FinFET respectively. It is also reported that the physical
length of the surround gate is less than the physical length of the DG-MOSFET and it is
condensed through the factor of the square root of 2 . Hence, the modified physical lengths
of the TG-FinFET will be,

44
Fig 2.2 Surface potential with different channel lengths for SiO2 gate oxide with device
parameter: Wfin = 5 nm, Hfin = 20 nm at y = H fin/2 , z = Wfin/2 position, Vd = 0V. Reference
analytical model is taken from [30]

45
 CHAPTER : 3
Gate Stacked GaN-FinFET with BaTiO3 Oxide for High Performance and High-
Power Applications
Purpose of TCAD simulation
Gate stack simulation
For design finfet for high power application, the GaN based finfet is chosen and dimension of
structure is taken in micro meter rage the gate length is 1 µm , width of fin is 0.5 µm, and
height of fin is 1 µm. the buried oxide is SiO 2 .the workfunction of gate is 4.8 eV and of
Source and Drain is 3.9 eV that are comparable to copper and aluminium respectively .
In the simulation ,the oxide stack of BaTiO 3 is taken with three most used oxide materials
that are SiO2, Al2O3 , and HfO2 . As BaTiO3 cannot be used directly with channel so BaTiO3 is
placed above the second oxide . In this part we analyze
1. Surface Potential
2. Drain current vs gate voltage
3. Drain current vs drain voltage
4. Transconductance
5. gate to source capacitance
6. gate to drain capacitance
7. cut-off frequency
8. Unilateral power gain
9. S-parameters
10. H-parameters
After investigating the above results we can conclude which oxide combination is better
choice for gate stack with BaTiO3 in GaN based Finfet

46
3D structure of FinFET

Fig 3.1 3D finfet structure gate length(L g)=1µm, fin width(Wfin)=0.5 µm, fin height(Hfin)=1
µm

SIMULATION RESULTS

Fig 3.2 Surface Potential versus gate length

47
Fig 3.3 drain current versus gate voltage at drain voltage of 5 volts

Fig 3.4 drain current versus drain voltage at gate voltage of 3 volts

48
Fig 3.5 Transconductance versus gate voltage for oxide stack of HfO2, Al2O3,
and SiO2 with BaTiO3

Fig 3.6 gate to source capacitance versus gate voltage for oxide stack of HfO2, Al2O3, and
SiO2 with BaTiO3

49
Fig 3.7 gate to drain capacitance versus gate voltage for oxide stack of HfO2, Al2O3, and
SiO2 with BaTiO3

Fig 3.8 Cut-off frequency versus gate voltage for oxide stack of HfO2, Al2O3, and SiO2 with
BaTiO3

50
Fig 3.9 Unilateral Power Gain versus gate voltage for oxide stack of HfO2, Al2O3, and SiO2
with BaTiO3

(a)

51
(b)

(c)

52
 (d)
Fig 3.10 (a) input reflection coefficient (S11) versus gate voltage (b) reverse voltage gain
(S12) versus gate voltage (c) forward voltage gain (S21) versus gate voltage (d) output
reflection coefficient (S22) versus gate voltage

53
 (a)

(b)
Fig 3.11 (a) input impedance (H11) versus gate voltage (b) forward current gain (H21)
versus gate voltage

54
 CHAPTER : 4
CONCLUSION AND FUTURE SCOPE
CONCLUSION

Parameters HfO2 Al2O3 SiO2

DRAIN CURRENT (ID) HIGH MEDIUM LOW

INPUT REFLECTION LOW MEDIUM HIGH

COEFFICIENT(S11)
REVERSE VOLTAGE GAIN HIGH MEDIUM LOW
(S12)
FORWARD VOLTAGE GAIN HIGH MEDIUM LOW
(S21)
OUTPUT REFLECTION LOW MEDIUM HIGH
COEFFICIENT(S22)
UNILATERAL POWER LITTLE LESS MEDIUM LITTLE HIGH
GAIN
TRANSCONDUCTANCE HIGH MEDIUM LOW
(gm)
GATE TO SOURCE HIGH MEDIUM LOW
CAPACITANCE (Cgs)
GATE TO DRAIN HIGH MEDIUM LOW
CAPACITANCE (Cgd)
CUT-OFF FREQUENCY (Ft) LITTLE LESS MEDIUM LITTLE HIGH
SURFACE POTENTIAL HIGH MEDIUM LOW

The high dielectric value of HfO2 (Hafnium Oxide) at 25, coupled with its superior electrical
properties, makes it an ideal choice for gate stack applications. Experimental results have
demonstrated that HfO2 exhibits exceptional performance across various parameters. It
showcases the best drain current, reflection coefficient, forward voltage gain (S11),
transconductance, and surface potential. Moreover, HfO2's cut-off frequency and unilateral
power gain are comparable to other gate stack materials like Al2O3 and SiO2. Considering
the excellent electrical properties, including drain current, transconductance, and
comparable cut-off frequency, the optimal combination for gate stacking involves pairing
HfO2 with BaTiO3. This combination offers the best overall performance and is preferred for
achieving desirable outcomes.

55
Future Scope
 Use more combinations of gate stack to further improve the the electrical
conductivity of finfet .

 Make junction less channel to reduce the channel length modulation and increase
the conductivity and cut-off frequency

 Improve the cut-off frequency by reducing the gate length

 Analyze the variation with gate workfunction to improve the gate controllability on
drain current

 Modify the structure of finfet for achieving high gain and power

56
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IEEE Transactions on Electron Devices 49(8):1411 - 1419

[20] Dawei, Zhang, Tian Lilin, and Yu Zhiping. "Compact Threshold Voltage Model for
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Concentration in a FinFET using 3D TCAD." International Journal of Computer Applications
975 (2014): 8887.

[22] FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm Digh Hisamoto,

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Himangi Sood1 , Viranjay M. Srivastava2 , Ghanshyam Singh1

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59
Appendix

Silvaco TCAD Simulated Code

go atlas simflags="-p 10"

#Mesh Defining
MESH THREE.D
#FinFET length
X.MESH LOC=-1 SPAC=0.05
X.MESH LOC=-0.9 SPAC=0.1
X.MESH LOC=-0.7 SPAC=0.1
X.MESH LOC=-0.5 SPAC=0.1
X.MESH LOC=-0.2 SPAC=0.1
X.MESH LOC=0.00 SPAC=0.04
X.MESH LOC=0.2 SPAC=0.1
X.MESH LOC=0.5 SPAC=0.1
X.MESH LOC=0.7 SPAC=0.1
X.MESH LOC=0.9 SPAC=0.1
X.MESH LOC=1 SPAC=0.05

###########################################################################
#########

#FinFET Height
Y.MESH LOC=0.00 SPAC=0.4
Y.MESH LOC=0.002 SPAC=0.4
Y.MESH LOC=0.048 SPAC=0.4
Y.MESH LOC=0.05 SPAC=0.05
Y.MESH LOC=0.052 SPAC=0.4
Y.MESH LOC=0.10 SPAC=0.4
Y.MESH LOC=0.5 SPAC=0.1
Y.MESH LOC=0.7 SPAC=0.1
Y.MESH LOC=1.3 SPAC=0.1
Y.MESH LOC=1.48 SPAC=0.4
Y.MESH LOC=1.5 SPAC=0.05
Y.MESH LOC=1.52 SPAC=0.2
Y.MESH LOC=1.6 SPAC=0.1
Y.MESH LOC=1.7 SPAC=0.05
Y.MESH LOC=1.72 SPAC=0.4

60
Y.MESH LOC=1.9 SPAC=0.4

###################################################################

#FinFET Width

Z.MESH LOC=0.00 SPAC=0.4

Z.MESH LOC=0.18 SPAC=0.4
Z.MESH LOC=0.2 SPAC=0.05
Z.MESH LOC=0.22 SPAC=0.4
Z.MESH LOC=0.3 SPAC=0.1
Z.MESH LOC=0.38 SPAC=0.1
Z.MESH LOC=0.4 SPAC=0.05
Z.MESH LOC=0.42 SPAC=0.05
Z.MESH LOC=0.51 SPAC=0.2
Z.MESH LOC=0.88 SPAC=0.4
Z.MESH LOC=0.9 SPAC=0.05
Z.MESH LOC=0.92 SPAC=0.1
Z.MESH LOC=1.0 SPAC=0.1
Z.MESH LOC=1.08 SPAC=0.1
Z.MESH LOC=1.1 SPAC=0.05
Z.MESH LOC=1.12 SPAC=0.4
Z.MESH LOC=1.3 SPAC=0.4
###########################################################################
##############################

#Defining different region of FinFET

REGION NUM=1 MATERIAL=SiO2 X.MIN=-1 X.MAX=1 Y.MIN=0.0 Y.MAX=0.5

Z.MIN=0.00 Z.MAX=1.3
REGION NUM=2 MATERIAL=GaN X.MIN=-0.9 X.MAX=0.9 Y.MIN=0.5 Y.MAX=1.5
Z.MIN=0.4 Z.MAX=0.9
REGION NUM=3 MATERIAL=SiO2 X.MIN=-0.5 X.MAX=0.5 Y.MIN=1.5 Y.MAX=1.6
Z.MIN=0.3 Z.MAX=1.0
REGION NUM=4 MATERIAL=oxide X.MIN=-0.5 X.MAX=0.5 Y.MIN=1.6 Y.MAX=1.7
Z.MIN=0.2 Z.MAX=1.1
REGION NUM=5 MATERIAL=SiO2 X.MIN=-0.5 X.MAX=0.5 Y.MIN=0.5 Y.MAX=1.5
Z.MIN=0.3 Z.MAX=0.4
REGION NUM=6 MATERIAL=oxide X.MIN=-0.5 X.MAX=0.5 Y.MIN=0.5 Y.MAX=1.6
Z.MIN=0.2 Z.MAX=0.3
REGION NUM=7 MATERIAL=SiO2 X.MIN=-0.5 X.MAX=0.5 Y.MIN=0.5 Y.MAX=1.5
Z.MIN=0.9 Z.MAX=1.0
REGION NUM=8 MATERIAL=oxide X.MIN=-0.5 X.MAX=0.5 Y.MIN=0.5 Y.MAX=1.6
Z.MIN=1.0 Z.MAX=1.1

#Defining Gate electrodes

61
ELECTRODE NAME=GATE X.MIN=-0.5 X.MAX=0.5 Y.MIN=1.7 Y.MAX=1.9 Z.MIN=0.2
Z.MAX=1.1
ELECTRODE NAME=GATE1 X.MIN=-0.5 X.MAX=0.5 Y.MIN=0.5 Y.MAX=1.9 Z.MIN=0.00
Z.MAX=0.2
ELECTRODE NAME=GATE2 X.MIN=-0.5 X.MAX=0.5 Y.MIN=0.5 Y.MAX=1.9 Z.MIN=1.1
Z.MAX=1.3

#Defining Drain and Source

ELECTRODE NAME=DRAIN X.MIN=-1 X.MAX=-0.9 Y.MIN=0.5 Y.MAX=1.5 Z.MIN=0.4

Z.MAX=0.9
ELECTRODE NAME=SOURCE X.MIN= 0.9 X.MAX=1 Y.MIN=0.5 Y.MAX=1.5 Z.MIN=0.4
Z.MAX=0.9

#Defining doping concentration

DOPING UNIFORM CONCENTRATION=5E19 N.TYPE X.MIN=-0.9 X.MAX=-0.5 Y.MIN=0.5

Y.MAX=1.5 Z.MIN=0.4 Z.MAX=0.9
DOPING UNIFORM CONCENTRATION=1E16 P.TYPE X.MIN=-0.5 X.MAX=0.5 Y.MIN=0.5
Y.MAX=1.5 Z.MIN=0.4 Z.MAX=0.9
DOPING UNIFORM CONCENTRATION=5E19 N.TYPE X.MIN= 0.5 X.MAX=0.9 Y.MIN=0.5
Y.MAX=1.5 Z.MIN=0.4 Z.MAX=0.9

#Defining permitivity of BaTiO3

MATERIAL REGION=4 PERMITTIVITY=2000

MATERIAL REGION=6 PERMITTIVITY=2000
MATERIAL REGION=8 PERMITTIVITY=2000

#Defining workfunction of gate, drain and source

CONTACT NAME=GATE WORKFUNCTION=4.8

CONTACT NAME=GATE1 WORKFUNCTION=4.8 COMMON=GATE
CONTACT NAME=GATE2 WORKFUNCTION=4.8 COMMON=GATE

CONTACT NAME=DRAIN WORKFUNCTION=3.9

CONTACT NAME=SOURCE WORKFUNCTION=3.9

#defining models for GanFET

models auger srh conmob fldmob b.electrons=2 b.holes=1 evsatmod=0 hvsatmod=0 \

cvt boltzman bgn print numcarr=2 temperature=300

#defining mobility parameters for GanFET

mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000 cp.cvt=884200 \

taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5 gamp.cvt=2.2 \

62
 mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4 mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17 csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71 betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14 delp.cvt=2.0546e+14

#defining method for simulation

method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4 autonr \

nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03 maxinner=25
output e.field j.electron j.hole j.conduc j.total e.velocity h.velocity \
ex.field ey.field flowlines e.mobility h.mobility qss e.temp h.temp \
charge recomb val.band con.band qfn j.disp photogen impact tot.doping

Solve init
save outf=FinFET.str

###############################AC
Analysis####################################
solve vdrain=0.1
solve vdrain=0.2
solve vdrain=0.5
solve vdrain=1
solve vdrain=5
#log outfile= AC(1e9)(vds-.1)-Conventional-Fin-FET.log
log outf=FinFETa(HfO2_1).log master gains s.params h.params inport=gate outport=drain
width=0.5
solve ac freq=1e9 vgate=0 vstep=0.2 vfinal=8 name=gate
extract init inf="FinFETa(HfO2_1).log"
extract name="vt" (xintercept(maxslope(curve(abs(v."gate"),abs(i."drain")))) \
- abs(ave(v."drain"))/2.0)
extract name="transconductance" deriv(v."gate", i."drain", 1) outfile="gma.dat"
extract name="ft-total" curve(v."gate",((abs(g."drain""gate"))/(6.28*(c."gate""source"))))
outfile="Ft-Fin-FET.dat"
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")))))
extract name="gm1" deriv(v."gate",i."drain") outfile= "gm1.dat"

extract name="gm2" deriv(v."gate",i."drain",2) outfile= "gm2.dat"

extract name="gm3" deriv(v."gate",i."drain",3) outfile= "gm3.dat"

quit

#####################################################id-vd#################
SOLVE Vgate=0
solve vgate=0.1

63
solve vgate=0.5
solve vgate=1
solve vgate=3
#solve vgate=5
LOG OUTFILE=id_vds.log
SOLVE NAME=drain Vdrain=0.0 VFINAL=10 VSTEP=0.2
extract init inf = "id_vds.log"
extract name="gd" deriv(abs(v."drain"),abs(i."drain")) outfile= "gdFin-FET.dat"
###########################################################################
quit
extract name="vt1"x.val from curve(abs(v."gate"),abs(i."drain")) where \
y.val=1e-7

##################SUBTHRESHOLD SLOPE############

extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")))))

quit

64
List of Models used in simulation

models : This specifies the physical models to be used in the simulation.

auger : Auger recombination model.

Srh : Shockley-Read-Hall recombination model.
Conmob : Model for impact ionization.
Fldmob : Model for the electric field dependence of mobility.
b.electrons=2 : Band model for electrons is parabolic.
b.holes=1 : Band model for holes is non-parabolic.
evsatmod=0 : Electric field dependence of saturation velocity is not used.
hvsatmod=0 : Hole velocity saturation model is not used.
Cvt : Model for high-field velocity saturation effect.
Boltzman : Boltzmann transport model.
Bgn : Bandgap narrowing effect is considered.
Print : Model debugging information will be printed.
numcarr=2 : Two carrier types (electrons and holes) will be considered.
temperature=300: The simulation temperature is set to 300 Kelvin.

Mobility : This defines the mobility parameters for the simulation.

bn.cvt : Electron mobility coefficient for the CVT model.

bp.cvt : Hole mobility coefficient for the CVT model.
cn.cvt : Electron mobility coefficient for the CVT model.
cp.cvt : Hole mobility coefficient for the CVT model.
taun.cvt : Electron lifetime for the CVT model.
taup.cvt : Hole lifetime for the CVT model.
gamn.cvt : Electron capture cross section for the CVT model.
gamp.cvt : Hole capture cross section for the CVT model.
mu0n.cvt : Low-field electron mobility coefficient for the CVT model.
mu0p.cvt : Low-field hole mobility coefficient for the CVT model.
mu1n.cvt : High-field electron mobility coefficient for the CVT model.
mu1p.cvt : High-field hole mobility coefficient for the CVT model.
mumaxn.cvt: Maximum electron mobility coefficient for the CVT model.
mumaxp.cvt: Maximum hole mobility coefficient for the CVT model.
crn.cvt : Electron capture coefficient for the CVT model.
crp.cvt : Hole capture coefficient for the CVT model.
csn.cvt : Electron scattering coefficient for the CVT model.
csp.cvt : Hole scattering coefficient for the CVT model.
alphn.cvt : Electron velocity saturation parameter for the CVT model.
alphp.cvt : Hole velocity saturation parameter for the CVT model.
betan.cvt : Electron velocity saturation parameter for the CVT model.
betap.cvt : Hole velocity saturation parameter for the CVT model.
pcn.cvt : Electron phonon scattering parameter for the CVT model.
pcp.cvt : Hole phonon scattering parameter for the CVT model.

65
deln.cvt : Electron deformation potential parameter for the CVT model.
delp.cvt : Hole deformation potential parameter for the CVT model.

66