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SRM VALLIAMMAI ENGINEERING COLLEGE

(An Autonomous Institution)
SRM Nagar, Kattankulathur – 603 203

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
QUESTION BANK

VII SEMESTER
EC8791 - EMBEDDED AND REAL TIME SYSTEMS

Regulation – 2017

Academic Year 2020 – 2021

Prepared by
Dr.J.Mohan, Associate Professor
Mr.C.Saravana Kumar, Assistant Professor
Ms K.Arthi, Assistant Professor

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SRM VALLIAMMAI ENGINEERING COLLEGE

(An Autonomous Institution)
SRM Nagar, Kattankulathur – 603 203.

DEPARTMENT OF ECE

Question Bank
SUBJECT : EC8791 – EMBEDDED AND REAL TIME
SYSTEMS. SEM / YEAR : VII / IV-Year B.E.
UNIT I - INTRODUCTION TO EMBEDDEDSYSTEM DESIGN
Complex systems and microprocessors– Embedded system design process –Design example: Model train
controller- Design methodologies- Design flows - Requirement Analysis – Specifications-System analysis
and architecture design – Quality Assurance techniques - Designing with computing platforms – consumer
electronics architecture – platform-level performance analysis.
Q.No Questions BT Domain
Level
PART – A
1 What is an Embedded computer system? BTL 1 Remembering
2 Enumerate various issue in real time computing BTL5 Evaluating
3 Illustrate the various embedded system design modeling in refining BTL3 Applying
or partitioning?
4 Why microprocessor is used in embedded system? BTL 6 Creating
5 Mention the challenges in embedded computing system design. BTL 1 Remembering
6 Formulate the importance of design methodology. BTL3 Applying
7 Describe the major steps in embedded system design process. BTL 2 Understanding
8 List the non-functional requirements of an Embedded Architecture. BTL 1 Remembering
9 Identify the various issues in real time computing. BTL 2 Understanding
10 Assess the characteristics of embedded computing. BTL 4 Analyzing
11 Summarize the challenges in embedded computing system design. BTL 2 Understanding
12 State the major goals of embedded system design. BTL 1 Remembering
13 Can you elaborate, Quality Assurance Techniques? BTL 6 Creating
14 Justify, how the state bar chart used to state based system BTL5 Evaluating
specification analysis.
15 Categories the steeps involved in system analysis using CRC card. BTL 4 Analyzing
16 Estimate about the function quality management of ISO 9000? BTL 2 Understanding
17 Analyze, how the design review is help to review a particular BTL 4 Analyzing
component of system.
18 What are the services to be provided by consumer electronics? BTL 1 Remembering

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19 Develop the functional architecture diagram of multimedia player. BTL3 Applying
20 What you mean by wear-leveling flash file system? BTL 1 Remembering
PART – B
1 (i) What are the factors to be considered while designing an BTL 1 Remembering
Embedded System Process? (8)
(ii) State the importance of Structural and Behavioral description in
detail. (5)
2 (i) Analyze in detail about the challenges in embedded computing BTL 4 Analyzing
system design. (8)
(ii) Find out how characters are copied from input to output using
interrupts and buffers with the help of a program segment. (5)
3 (i) Mention the requirements for designing a GPS moving map in BTL 1 Remembering
embedded system design process. (8)
(ii) Write down the major operations and data flows of a GPS
moving map and draw its Architecture (5)
4 Write short note on following BTL 2 Understanding
(i) Control-Oriented Specification Languages, (7)
(ii) Quality Assurance Techniques. (6)
5 Define acronym of CRC. Make the use of a CRC card Layout to BTL 1 Remembering
explain the system analysis and architecture design. (13)
6 (i) Explain in detail the characteristics of embedded computing BTL 4 Analyzing
applications. (5)
(ii) Conclude about supervisor mode, exception and traps in detail.
(8)
7 Evaluate system design using requirements and illustrate the type of BT 5 Evaluating
design and explain. (13)
8 Analyze the hierarchical design flow for an embedded system with BTL 4 Analyzing
suitable diagrams. (13)
9 Construct system design methods using water fall, spiral and rain fall BTL 3 Applying
method and also give the differences. (13)
10 Demonstrate the goal of design methodology in detail. (13) BTL 2 Understanding
11 Develop a model that would change system design using hardware BTL 3 Applying
software design system method. (13)
12 (i) Design in detail a Model Train Controller with suitable diagrams. BTL 6 Creating
(8)
(ii) Formulate design steps of Model Train Controller in detail. (5)
13 Describe the performance of embedded computing systems. (13) BTL 2 Understanding
14 Write short note on the following in terms of consumer electronics BTL 1 Remembering
system architecture

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(i). Use Cases and Requirements, (5)
(ii). Platforms and Operating Systems, (5)
(iii). Flash File Systems. (3)
PART – C
1 Develop the requirement, specification and state diagram of a model BTL 6 Creating
train controller with necessary illustrations. (15)
2 Elaborate following in detail as per system level design analysis. BTL 6 Creating
(i). Consumer electronics architecture, (5)
(ii). Quality Assurance techniques, (5)
(iii). Architecture design. (5)
3 Evaluate the deferent factors involved in embedded system design BTL5 Evaluating
process. (15)
4 Justify poor specifications lead to poor quality code—do aspects of a BTL5 Evaluating
poorly-constructed specification necessarily lead to bad software?
(15)

UNIT II ARM PROCESSOR AND PERIPHERALS

ARM Architecture Versions – ARM Architecture – Instruction Set – Stacks and Subroutines – Features of
the LPC 214X Family – Peripherals – The Timer Unit – Pulse Width Modulation Unit – UART – Block
Diagram of ARM9 and ARM Cortex M3 MCU.

PART A
Q. No Questions BT Level Competence

1 What is Code density? BTL 2 Remembering

2 Illustrate the three different profiles of ARM cortex Processor BTL 1 Understanding
3 Evaluate the important features that make ARM ideal for BTL 5 Evaluating
embedded applications.
4 Name the registers set of ARM processor BTL 1 Remembering
5 Develop the differences between MULS and MULSEQ BTL 3 Applying
6 Explain the execution of instruction MOV R11, R2 BTL 6 Creating
7 Write down the significance of TST instruction BTL 1 Remembering
8 Outline the significance of TEQ instruction. BTL 2 Understanding
9 State the usage of EQU directive in programming. BTL 1 Remembering
Examine the maximum size of the constant that can be used in BTL 3 Applying
10
the immediate mode?
11 Explain how the literal pool is accessed? BTL 5 Evaluating
12 Draw the sequence of actions needed for a nested procedure BTL 1 Remembering
13 What is meant by idle mode? BTL 1 Remembering
14 Find the methods to terminate the power down mode. BTL 3 Applying

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15 Mention the features of LPC214x. BTL 2 Understanding
16 Summarize any five peripherals in the LPC 2148 MCU. BTL 2 Understanding
17 Compare PCLK and CCLK BTL 4 Analyzing
18 For a GPIO pin to be made to act as an ON/OFF switch, which BTL 4 Analyzing
are the registers to be used.
19 How does the prescalar in a timer unit function?. BTL 6 Creating
20 Distinguish between single and double edged PWM. BTL 4 Analyzing
PART – B
1 Demonstrate the advanced features of the ARM Core . (13) BTL 2 Understanding
2 From the fundamentals, draw the architecture of ARM processor (13) BTL4 Analyzing
with relevant explanation.
3 (i) Point out the operating modes of ARM (7)
(ii) Briefly explain the Register set of ARM BTL 1 Remembering
(6)
Examine the interrupt vector table by providing the vector (13)
4 BTL 4 Analyzing
address of each interrupt supported by ARM.
(i) Classify the ARM instruction set (3)
5 BTL 1 Remembering
(ii) Explain any one type of instruction set with example (10)
6 The content of registers is given as below BTL 3 Applying
R1 = 0xEF00DE12,
R12 = 0x0456123F,
R5 = 4, R6 = 28.
Find the result in the destination register when the following
instructions are executed (5)
i) LSL R1, #8 (5)
ii) ASR R1,R5 (3)
iii) ROR R2,R6
7 Give the general structure of an Assembly language line and (13) BTL 2 Understanding
provide examples for each directive.
8 Analyze the following indexed addressing mode with a sample
instruction
BTL 4 Analyzing
i) Pre indexed Addressing mode (7)
ii) Post indexed Addressing mode (6)
9 Discuss about the types of stacks and subroutines supported by (13) BTL 1 Remembering
ARM processor
10 Demonstrate the GPIO peripheral used in LPC214x family. (13) BTL 3 Applying
11 Investigate the working of a UART in LPC214x (13) BTL 6 Creating
12 Outline the concepts behind single edge controlled PWM (13) BTL 2 Understanding
13 (i) Calculate the value of the value to be given in PWMMR0 (7) BTL 5 Evaluating
and PWMMR3 to get a pulse train of period 5 ms and duty
cycle of 25%.

(ii) Evaluate the features of LPC 214x processor (6)

14 Draw the architecture of ARM Cortex processor and describe its (13) BTL 1 Remembering
functional units.
PART – C
1 Write a program to find the sum of 3X + 4Y + 9Z, where X = 2, (15) BTL6 Creating
Y = 3 and Z = 4 using ARM Processor instruction set.

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2 Generate the program using ARM instruction to calculate 3X2 + (15) BTL 5 Evaluating
5Y2, where X = 8 and Y = 5
3 Discuss on the procedure to generate the square wave from Timer (15)
BTL 6 Creating
unit in LPC214x chip with an example code.
4 Evaluate the values to be entered in the PWMPCR register for (15) BTL 5 Evaluating
the following situations?
i) Single edge control for PWM3
ii) Double edge control for PWM3
iii) Single edge control for PWM1, 2 and 3

UNIT III EMBEDDED PROGRAMMING

Components for embedded programs- Models of programs- Assembly, linking and loading – compilation
techniques- Program level performance analysis – Software performance optimization – Program level energy
and power analysis and optimization – Analysis and optimization of program size- Program validation and
testing.
PART A
Q. No Questions BT Competence
Level
1 Mention the different components for embedded programs. BTL 1 Remembering
2 Evaluate the importance of circular buffer. BTL 5 Evaluating
3 Compare enqueueing and dequeueing BTL 4 Analyzing
4 Describe about state machine. BTL 6 Creating
5 Develop the differences between loop fusion and loop tiling BTL 3 Applying
6 Outline the significance of CDFG. BTL 2 Understanding
Construct a Data Flow Graph and Control/ Data Flow Graph (CDFG) BTL 3 Applying
7 with an example.
Design a Data Flow Graph for the block shown below: BTL 6 Creating
8
r = a+b-c; s = a*r ; t = b-d; r = d+e;
9 State the basic principle of compilation technique. BTL 1 Remembering
Name any two techniques used to optimize execution time of BTL 1 Remembering
10 program
11 Explain how power can be optimized at the program level? BTL 5 Evaluating
12 Mention the various compilation techniques. BTL 1 Remembering
13 What does a linker do? BTL 1 Remembering
14 Find the limitation of polling techniques. BTL 3 Applying
15 Illustrate the need of symbol table in Assemblers. BTL 2 Understanding
Summarize the two ways used for performing input and output BTL 2 Understanding
16 operations
17 Discuss about the elements of program performance. BTL 2 Understanding
18 Differentiate compiler and cross compiler. BTL 4 Analyzing
State the difference between program location counter and program BTL 1 Remembering
19 counter.
20 Interpret the importance of Boot-block flash. BTL 4 Analyzing
PART – B
1 Analyze the components of embedded program and discuss in (13) BTL 2 Understanding
detail about each component.

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2 Describe about stream-oriented programming and circular (13) BTL4 Analyzing
buffer with example.
3 (i) List the different models of Program
(3)
(ii) Briefly explain with neat diagrams on various models of BTL 1 Remembering
(10)
program
4 Examine the Data flow graph with the help of an example. (13) BTL 2 Understanding
Illustrate the Code/Data flow graph for a While loop with (13)
5 BTL 1 Remembering
necessary diagrams
6 In compilation process, Elaborate the role of BTL 2 Understanding
i) Assemblers (7)
ii) Linkers (6)
7 With the help of a flow chart describe the basic compilation (13) BTL 3 Applying
process
8 For the given conditional code snippet, generate the code (13)
if (a + b > 0)
x = 5; BTL 4 Analyzing
else
x = 7;
9 Discuss about the Procedure and Data structure with respect to (13) BTL 1 Remembering
compilers
10 Demonstrate the dead code elimination to optimize the program (13) BTL 3 Applying
with a code snippet.
11 Investigate the Loop transformation techniques for optimization (13) BTL 6 Creating
of code.
12 Outline the Program level energy and power analysis and (13)
optimization BTL 4 Analyzing
13 Write about BTL 1 Remembering
i) Black box Testing (7)
ii) White box Testing (6)
14 (i) Illustrate with necessary diagrams about the program level (7) BTL 5 Evaluating
performance analysis.
(ii) Frame the key features of clear box testing. (6)
PART – C
1 Create a symbol table for the following code snippet (15) BTL6 Creating

ORG 100
label1 ADR r4,c
LDR r0,[r4]
label2 ADR r4,d
LDR r1,[r4]
label3 SUB r0,r0,r1
2 Generate the statement translation into ARM instruction for the (15) BTL 5 Evaluating
expression a*b + 5*(c-d)
3 Explain the steps for Program generation from compilation (15)
through loading. BTL 6 Creating
4 Evaluate the different techniques used in software performance (15) BTL 5 Evaluating
optimization.

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UNIT IV REAL TIME SYSTEMS
Structure of a Real Time System –– Estimating program run times – Task Assignment and Scheduling – Fault
Tolerance Techniques – Reliability, Evaluation – Clock Synchronisation.
PART – A
Q.No Questions BT Competence
Level
1 List out the two RM scheduling conditions. BTL 1 Remembering
2 Outline the uniprocessor scheduling algorithms. BTL 1 Remembering
3 Define Performance measures for real time systems.. BTL 1 Remembering
4 What is mean by hardware and software fault? BTL 1 Remembering
5 Show the limitation of RM algorithm. BTL 1 Remembering
6 Outline the definition for a schedule as a function. BTL 1 Remembering
7 Summarize the two steps of tasks for developing a multiprocessor BTL 2 Understanding
schedule.
8 Discuss the performance degradation of a fault tolerant system BTL 2 Understanding
9 Explain the forward and backward error recovery. BTL 2 Understanding
10 Classify the partitioning of the intervote interval. BTL 2 Understanding
11 Illustrate the role of static priority algorithm. BTL 3 Applying
12 Sketch the frequency response of an ideal VCO. BTL 3 Applying
13 How will you distinguish static priority algorithm & dynamic priority BTL 3 Applying
algorithm?
14 Analyze the causes of preemptive and non-preemptive schedule. BTL 4 Analyzing
15 Categorize the difference between between release time and deadline. BTL 4 Analyzing
16 Choose some of the fault types based on temporal behavior BTL 4 Analyzing
classification.
17 Briefly explain how a task assignment is said to be feasible. BTL 5 Evaluating
18 What are the features that discriminates offline and online scheduling? BTL 5 Evaluating
19 Discuss about malicious or byzantine failures. BTL 6 Creating
20 Elaborate about periodic, sporadic and aperiodic tasks. BTL 6 Creating
PART – B
1 Write short notes on BTL 1 Remembering
a) Introduction of transient faults. (7)
b) use of state aggregation (6)

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2 i) List out the sequence of events resulting in triad failure. (6) BTL 1 Remembering
ii) Explain the methodology to choose the best distribution. (7)
3 Explain the typical designs for voter reliability with the example of BTL 1 Remembering
poisson failures. (13)
4 Mention the classification of faults according to their temporal behavior BTL 1 Remembering
and output behavior. (13)
5 Give a detail notes on mathematical understanding of the priority ceiling BTL 2 Understanding
algorithm using a series of results. (13)
6 Summarize the important points on : BTL 2 Understanding
a) obtaining device failure rates (6)
b) measuring error propagation times (7)
7 i) Give a brief note on loss of synchrony. (7) BTL 2 Understanding
ii) Explain the principle of clocks in basic level. (6)
8 i) Explain the permanent faults in series parallel systems. (7) BTL 3 Applying
ii) What are the performance measures for real time systems?
Summarize. (6)
9 Apply the knowledge of uniprocessor scheduling algorithms in BTL 3 Applying
developing a multiprocessor schedule. (13)
10 i) What would be multiprocessor scheduling? (5) BTL 4 Analyzing
ii) Inspect how the clocks are synchronized if the times are close to each
other. (8)
11 (i) Compare independent failure and correlated failure. (3) BTL 4 Analyzing
(ii) Examine the process of completely connected zero propagation
system. (10)
12 Examine the exponentially distributed fault latency with the condition BTL 4 Analyzing
mean 1/µ. (13)
13 Criticize on reliability models for hardware redundancy. (13) BTL 5 Creating
14 Determine the more general model assuming that the failure process was BTL 6 Evaluating
Poisson and fault latencies were exponentially distributed. (13)
PART – C
1 Estimate the Techniques for allocating and scheduling tasks on BTL 6 Creating
processors to ensure that deadlines are met. (15)
2 Discuss the preemptive earliest deadline first algorithm. (15) BTL 6 Creating
3 Evaluate utilization bound for the RM algorithm and explain it in detail. BTL 5 Evaluating
(15)

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4 Construct the reliability models for hardware redundancy. (15) BTL 5 Evaluating

UNIT V PROCESSES AND OPERATING SYSTEMS

Introduction – Multiple tasks and multiple processes – Multirate systems- Preemptive real-time operating
systems- Priority based scheduling- Interprocess communication mechanisms – Evaluating operating system
performance- power optimization strategies for processes – Example Real time operating systems-POSIX-
Windows CE. - Distributed embedded systems – MPSoCs and shared memory multiprocessors. – Design
Example - Audio player, Engine control unit – Video accelerator.
PART – A
Q.No Questions BT Competence
Level
1 Mention the networks for distributed embedded systems. BTL1 Remembering
2 Compare between a process and thread. BTL4 Analyzing
3 Differentiate between initiation time and completion time BTL4 Analyzing
4 Summarize the essential criteria’s of rate monolithic scheduling. BTL2 Understanding
5 Explain priority inversion briefly. BTL2 Understanding
6 Recognize the term time quantum? BTL1 Remembering
7 Outline the various scheduling states of a process. BTL2 Understanding
8 Investigate the organization of scheduling policy. BTL6 Creating
9 Draw the block diagram of Distributed embedded systems BTL3 Applying
10 What is Semaphore? BTL1 Remembering
11 Enumerate the priority inversion? BTL1 Remembering
12 Evaluate the communication among processes which runs at different
BTL5 Evaluating
rates.
13 List the advantages and limitations of Priority based process scheduling. BTL1 Remembering
14 Analyze the multi-processing systems. BTL4 Analyzing
15 Determine the important characteristics of Multitasking. BTL5 Evaluating
16 Design a hard-real-time operating system with an example. BTL6 Creating
17 Identify the principle of multi rate embedded system by quoting three
BTL3 Applying
examples
18 Give examples of blocking and Non-blocking inter process
BTL2 Understanding
communication
19 State the major function of POSIX RTOS? BTL1 Remembering
20 Frame the two different styles used for inter process communication. BTL3 Applying

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PART – B
1 i) Outline about priority-based scheduling in detail. (7) BTL4 Analyzing
ii) With the help of an example, explain that the knowledge of data
dependencies can help to use the CPU more efficiently. (6)
2 i) Discuss in detail multitasking and multiprocessing. (9) BTL2 Understanding
ii) Illustrate process state and scheduling. (4)
3 i) Summarize the preemptive real time operating systems in detail. (7) BTL4 Analyzing
ii) Analyze the special characteristics of Processes and Internet with the
help of a suitable diagram. (6)
4 Explain the concepts of Multiprocessor System-On-Chip (MPSoC) and BTL4 Analyzing
Shared memory multiprocessor are used in embedded applications. (13)
5 Infer in detail about the BTL2 Understanding
i) Characteristics of distributed embedded System. (7)
ii) Architecture of Distributed Embedded System with neat sketches. (6)
6 i) Enumerate the context switch mechanism for moving the CPU from BTL1 Remembering
one executing process to another. (7)
ii) State how the Kernel determines the order of the processes which has
to be executed. (6)
7 i) Evaluate operating system performance. (5) BTL5 Evaluating
ii) Compare the principle, merits and limitations of inter-process
communication mechanisms. (8)
8 i) Demonstrate in detail about power optimization strategies for CPU BT3 Applying
operation. (7)
ii) Identify how the Predictive shut down technique proved itself as
more sophisticated. (6)
9 i) Enumerate why an automobile engine requires multi rate BTL1 Remembering
control (4)
ii) Recall the performance of the Earliest – Deadline – First
scheduling with other scheduling algorithms with suitable
example. (9)
10 (i) Describe the real time operating system called POSIX in detail. (7) BTL1 Remembering
(ii) Write short notes on power optimization strategies in embedded
system. (6)
11 (i) Predict the services of operating system in handling multiple tasks BTL2 Understanding
and multiple processes. (7)
ii) Identify the features of preemptive execution with the help of a
sequence diagram. (6)

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12 i) Investigate this statement with the help of an example. The timing BTL6 Creating
requirements on a set of process can strongly influence the type of
appropriate scheduling. (7)
ii) Write about a critical section using semaphores in operating system.
(6)
13 i) Develop an approach for cooperative multitasking in the PIC16F with BTL3 Applying
the help of a program. What would happen if we put the tasks into Time
Handler? (10)
ii) Manipulate about CPU usage metrics. (3)
14 i) Mention in detail about Shared Resources. (7) BTL1 Remembering
ii) Explain about Windows CE with a neat diagram. (6)
PART C
1 From design flow analysis to architectural design, illustrate video BTL6 Creating
accelerator using UML methodology. (15)
2 Formulate the working of Engine control unit in detail. BTL5 Evaluating
i). Theory of operations and requirements, (4)
ii). Specification, (4)
iii). System Architecture, (3)
iv). Component designing and testing, (2)
v). System integration and testing. (2)
3 Explain in detail how shared memory and message passing mechanisms BTL5 Evaluating
are used for interprocess communication. (15)
4 Develop the Multirate system using condition of multi task and BTL6 Creating
processes? explain with suitable example and its necessary conditions.
(15)

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