BANGLADESH UNIVERSITY OF ENGINEERING AND

TECHNOLOGY
DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING

EEE 304 (January 2023)

Digital Electronics Laboratory

Final Project Report

Section: A2 Group: 01

Basic Core of tensor processing unit(TPU)

Course Instructors:
Nafis Sadik 1. Lecturer
Sadat Tahmeed Azad 2. Part-Time Lecturer

Signature of Instructor: ___________________________________________________

Academic Honesty Statement:

IMPORTANT! Please carefully read and sign the Academic Honesty Statement, below. Type the
student ID and name, and put your signature. You will not receive credit for this project experiment
unless this statement is signed in the presence of your lab instructor.
“In signing this statement, We hereby certify that the work on this project is our own and that we have not
copied the work of any other students (past or present), and cited all relevant sources while completing this
project. We understand that if we fail to honor this agreement, We will each receive a score of ZERO for this
project and be subject to failure of this course.”

Signature: ____________________________ Signature: ____________________________

Full Name: Md. Rakib Hossain Full Name: Md. Tahmid Shahriyar
Student ID: 1906034 Student ID: 1906036

Signature: ____________________________ Signature: ____________________________

Full Name: Samiul Zamadder Rohan Full Name: A. S. Al Mahmud Sajid
Student ID: 1906043 Student ID: 1906050
Table of Contents
1 Abstract .......................................................................................................... 1
2 Introduction ................................................................................................... 1
3 Design ..............................................................................................................3
3.1 Background Study ................................................................................................................. 3
3.2 Literature Review ..................................................................................................................6
3.3 Design Method ...................................................................................................................... 7
3.4 Full Source Code of Firmware .............................................................................................. 7
4 Implementation ............................................................................................15
4.1 Description .......................................................................................................................... 15
4.2 Experiment and Data Collection ......................................................................................... 16
4.3 Data Analysis ...................................................................................................................... 17
4.4 Results ................................................................................................................................. 17
5 Design Analysis and Evaluation ................................................................ 17
5.1 Novelty ................................................................................................................................ 17
5.2 Design Considerations .........................................................................................................17
5.3 Investigations ...................................................................................................................... 19
5.3.1 Literature Review ........................................................................................................19
5.4 Limitations of Tools ............................................................................................................ 20
5.5 Impact Assessment ..............................................................................................................21
5.5.1 Assessment of Societal and Cultural Issues ................................................................ 21
5.5.2 Assessment of Health and Safety Issues ..................................................................... 21
5.5.3 Assessment of Legal Issues .........................................................................................21
5.6 Sustainability and Environmental Impact Evaluation .........................................................21
5.7 Ethical Issues .......................................................................................................................21
6 Reflection on Individual and Team work .................................................22
6.1 Individual Contribution of Each Member ........................................................................... 22
6.2 Mode of TeamWork ............................................................................................................ 22
6.3 Diversity Statement of Team ...............................................................................................22
6.4 Log Book of Project Implementation ..................................................................................22
7 Communication ........................................................................................... 23
7.1 Executive Summary .................................................................................... 23
7.2 User Manual .................................................................................................23

i
8 Project Management and Cost Analysis ...................................................24
8.1 Bill of Materials .................................................................................................................. 24
9 Future Work ................................................................................................ 24
10 References .................................................................................................... 24

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Basic Core of TPU EEE 304 (January 2023) A2 Group 1- Final Project
1 Abstract

In the realm of artificial intelligence and machine learning, specialized hardware accelerators have
emerged as vital components to expedite the training and inference of complex neural network models.
Tensor Processing Units (TPUs) have garnered considerable attention for their exceptional performance in
machine learning workloads. In this academic project, we explore an innovative approach to hardware
acceleration by leveraging Field-Programmable Gate Arrays (FPGAs) to implement a simplified version of
a TPU architecture. Our FPGA-based system is designed to demonstrate a two-layer deep learning
architecture, comprising four neurons, and is specifically tailored for linear regression tasks.
The project unfolds with an in-depth analysis of TPUs and their hardware architecture, elucidating their
role in enhancing machine learning performance. Utilizing Verilog Hardware Description Language
(HDL), we meticulously implement a custom TPU-like architecture on an FPGA board. This
implementation enables the execution of a two-layer deep learning model, mimicking the principles of
TPUs, thus offering valuable insights into the workings of dedicated machine learning accelerators.
The core objective of our project is to showcase the feasibility of FPGA-based hardware acceleration for
neural network computations. We elucidate the design choices, optimizations, and trade-offs involved in
creating a functional deep learning architecture on FPGA. To validate our system's capabilities, we utilize
it to perform linear regression, a fundamental machine learning task, and present comparative performance
metrics with traditional computing platforms.
Our findings underscore the potential of FPGA-based hardware acceleration as a cost-effective and
customizable alternative to dedicated AI accelerators like TPUs. Furthermore, this project serves as a
stepping stone for future research and development in FPGA-based machine learning accelerators, opening
doors to new possibilities in edge computing and specialized hardware for AI applications.
In summary, our FPGA-based implementation of a two-layer deep learning architecture provides a
valuable contribution to the exploration of hardware acceleration in machine learning and demonstrates the
adaptability of FPGAs for such tasks. This project bridges the gap between hardware and machine
learning, offering a practical and insightful perspective on the fusion of these two domains.

2 Introduction

In the ever-evolving landscape of machine learning and artificial intelligence, the quest for
accelerating computational workloads has been relentless. The demand for faster and more efficient
solutions has led to the development of dedicated hardware accelerators tailored to the unique
requirements of neural networks. Among these accelerators, Tensor Processing Units (TPUs) have
emerged as a powerful force, offering unparalleled advantages over traditional Central Processing
Units (CPUs) and Graphics Processing Units (GPUs).
The exponential growth in data volumes and the increasing complexity of machine learning models
have made it imperative to seek novel approaches to computing. CPUs, once the workhorses of
general-purpose computing, and GPUs, optimized for graphics rendering and parallel processing,
have their limitations when confronted with the sheer scale and intricacy of modern neural networks.

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Basic Core of TPU EEE 304 (January 2023) A2 Page 01
Why TPUs Over CPUs and GPUs?
Specialization for Tensor Operations: TPUs are purpose-built to excel in the kinds of operations at
the heart of deep learning: tensor operations. Unlike CPUs and GPUs, which are designed for a
broader range of tasks, TPUs are finely tuned to execute matrix multiplications and other tensor-
based computations with exceptional efficiency. This specialization allows TPUs to perform
machine learning workloads significantly faster.
Parallelism and Scalability: TPUs embrace parallelism at an unprecedented level, enabling the
simultaneous processing of a vast number of mathematical operations. This inherent parallelism,
coupled with the ability to scale TPUs into clusters, empowers them to tackle massive datasets and
train complex models more rapidly than their CPU and GPU counterparts.
Energy Efficiency: TPUs exhibit remarkable energy efficiency, accomplishing more computations
per watt of power consumed compared to traditional CPUs and GPUs. This not only reduces the
operational costs but also aligns with the growing emphasis on environmentally sustainable
computing solutions.
Generic Benefits of TPUs
Beyond their specialization and performance advantages, TPUs offer several generic benefits:
Reduced Training Time: TPUs significantly shorten the training time of deep learning models,
enabling researchers and engineers to iterate and experiment more rapidly in the development of new
algorithms and models.
Improved Inference Speed: For real-time applications and edge computing scenarios, TPUs deliver
swift and responsive inference capabilities, making them ideal for tasks like image recognition and
natural language processing.
Scalability: TPUs can be easily integrated into cloud-based computing environments, allowing
organizations to scale their machine learning workloads as needed without substantial hardware
investments.
Competitive Advantage: Leveraging TPUs can provide a competitive edge in fields where rapid
model development and deployment are crucial, such as autonomous vehicles, healthcare, and
finance.
In this project, we delve into the intriguing world of TPUs, aiming to harness their computational
prowess in the realm of hardware acceleration. We endeavor to replicate their specialized
architecture on Field-Programmable Gate Arrays (FPGAs) and demonstrate their utility through a
two-layer deep learning model, with a focus on linear regression. By examining the capabilities and
advantages of TPUs, we seek to shed light on the transformative potential of specialized hardware in
the field of machine learning and artificial intelligence.

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Basic Core of TPU EEE 304 (January 2023) A2 Page 02
3 Design

3.1 Background study:

Neural Network:
Neural networks, often referred to as artificial neural networks or simply neural nets, are
computational models inspired by the structure and function of the human brain. These versatile and
powerful machine learning algorithms are designed to recognize patterns, learn from data, and make
predictions or decisions. At their core, neural networks consist of interconnected nodes, known as
neurons, organized into layers. Information flows through these layers, with each neuron performing
a simple computation. Through a process called training, neural networks adjust their internal
parameters, such as weights and biases, to minimize prediction errors, making them adept at tasks
like image recognition, natural language processing, and complex data analysis. Neural networks
have played a pivotal role in revolutionizing fields like computer vision, speech recognition, and
autonomous robotics, making them a fundamental tool in the realm of artificial intelligence.

Design of the TPU

The Tensor Processing Unit (TPU) represents a dedicated hardware accelerator meticulously crafted
for the optimization of machine learning workloads, particularly deep neural networks. At the core
of its design lies a specialized architecture tailored to efficiently execute the fundamental operations
crucial for neural network computations. In this section, we delve into the architectural intricacies of
the TPU, outlining how it harnesses systolic arrays, memory, and activation functions to maximize
its performance.
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Basic Core of TPU EEE 304 (January 2023) A2 Page 03
Systolic Array for Computation
One of the defining features of the TPU is the utilization of systolic arrays for performing
mathematical operations, specifically additions and multiplications. Systolic arrays are arrays of
processing elements arranged in a grid-like fashion. In the context of TPUs, they are instrumental in
parallelizing and accelerating matrix multiplications and other tensor operations—fundamental to
neural network computations.
Each processing element within the systolic array carries out arithmetic operations concurrently.
This inherent parallelism allows TPUs to perform complex mathematical calculations with
remarkable speed. By strategically orchestrating the flow of data through the systolic array, TPUs
can efficiently handle the weight matrices and input data, facilitating the forward and backward
propagation steps essential for training deep learning models.
Non-Volatile Memory for Weight and Bias Retrieval
To operate effectively, TPUs rely on external non-volatile memory units that store the learned
parameters of the neural network model. These parameters encompass the weights and biases
acquired during the training phase. During inference, the TPU fetches these parameters from
memory and employs them in the mathematical computations within the systolic array.
Non-volatile memory, often Flash memory or similar technologies, is prized for its ability to retain
data even when the power is turned off. This attribute is crucial for preserving the model's learned
knowledge, as neural network weights and biases are non-trivial to recompute. By accessing these
pre-trained parameters, TPUs offer a significant advantage in terms of computational efficiency
compared to retraining the model from scratch.
Activation Function and Output Storage
Following the computational steps within the systolic array, the TPU generates raw output values.
Before these values are used further in the network or as the final prediction, they typically undergo
activation functions. Activation functions introduce non-linearity into the model, enabling the neural
network to learn complex patterns and relationships in the data.
Common activation functions include ReLU (Rectified Linear Unit), Sigmoid, and Tanh. Depending
on the neural network architecture and specific use case, TPUs can accommodate various activation
functions. The processed output values are rounded up as per the chosen activation function's
characteristics.
Finally, the resulting values are stored in memory for subsequent layers or stages of the neural
network, contributing to the forward pass during inference.
In summary, the design of the TPU capitalizes on the power of systolic arrays, external non-volatile
memory for weight and bias retrieval, and the application of activation functions to efficiently
execute deep learning computations. This architecture enables TPUs to excel in accelerating
machine learning workloads, making them a vital component in the arsenal of hardware accelerators
for artificial intelligence applications.

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Basic Core of TPU EEE 304 (January 2023) A2 Page 04
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Basic Core of TPU EEE 304 (January 2023) A2 Page 05
3.2 Literature Review :

Quantitative Analysis of Deep Neural Networks (DNNs):

1. Neuron Activation: In a DNN, each neuron's activation can be represented mathematically
as follows:
Activation (z) = Σ (weight (w) * input (x)) + bias (b)
where Σ denotes summation over all input connections. The activation is then passed through an
activation function, often denoted as φ, which could be the ReLU function:
Activation (a) = φ(z) = max (0, z)
2. Forward and Backward Pass: During training, quantitative calculations in both the
forward and backward passes are essential. In the forward pass, you calculate the predicted
output (ŷ) and loss (L) quantitatively:
ŷ = f (input; θ)
L = Loss (ŷ, true_labels)
In the backward pass, you compute gradients (∂L/∂θ) with respect to model parameters (θ) using
backpropagation and update the weights quantitatively:
∂L/∂θ = ∂L/∂ŷ * ∂ŷ/∂φ * ∂φ/∂z * ∂z/∂θ
Weight Update: θ_new = θ_old - learning_rate * ∂L/∂θ
3. Layer Output Size: Quantitative analysis often involves tracking the size of layer outputs.
For instance, in a convolutional layer, the output size (O) can be computed as:
O = [(I - K + 2P) / S] + 1
where I is the input size, K is the filter size, P is the padding, and S is the stride.
Quantitative Analysis of TPUs in DNNs:
1. Matrix Multiplication Speed: TPUs excel at matrix multiplication. Quantitatively, the
speed of matrix multiplication (MM) on TPUs can be expressed as:

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Basic Core of TPU EEE 304 (January 2023) A2 Page 06
Execution Time_MM_TPU = (M * N * K) / (Throughput_TPU * Batch_Size)
where M, N, and K are matrix dimensions, and Throughput_TPU represents the TPU's processing
capability.
2. Energy Efficiency: Quantitative analysis of energy efficiency involves measuring the
energy consumed (E) during DNN operations on TPUs:
Energy Efficiency (EE) = Throughput_TPU / E
3. Model Training Time: Quantitatively comparing the time (T) required to train DNN
models on TPUs versus other hardware:
Speedup_TPU = Training Time_CPU / Training Time_TPU
4. Memory Usage: Quantitative analysis of memory usage involves tracking memory
consumption (Mem) during forward and backward passes:
Mem_TPU = Mem_Input + Mem_Layer + Mem_Weights + Mem_Other
By incorporating mathematical equations and notations, you can precisely quantify and analyze the
performance, efficiency, and suitability of DNNs and TPUs for various machine learning tasks. This
mathematical framework enables data-driven decision-making in hardware selection, model design,
and optimization.

3.3 Design Method

The equations that we wanted to achieve are:
y = mx +c
� �� − � �
m = � �2−( � )2
c=y–m�
We tried to achieve them by matrix multiplication:
�� = [�]1 � � � [�]� � 1

� = [1]1 � � � [�]� � 1

� = [1]1 � � � [�]� � 1

�2 = [�]1 � � � [�]� � 1
Here, all the variables inside brackets indicate matrices with their dimension in subscript. Other
operations are simply addition and multiplication.

3.4 Full Source Code of Firmware

Verilog Code:

module test(clk,reset,nLb1,nLb2,addr,rd,wr,Cen,en,out1,out2,out3,out4,out,re,nLo,in);

wire [7:0] Wbus;

input [7:0] addr,in;
input clk,reset,Cen,en,rd,wr,nLb1,nLb2,re,nLo;
output [7:0] out1,out2,out3,out4;
output [7:0] out;
wire [7:0] rb1_to_TPU_1,rb1_to_TPU_2,rb1_to_TPU_3,rb1_to_TPU_4,
rb2_to_TPU_1,rb2_to_TPU_2,rb2_to_TPU_3,rb2_to_TPU_4;
wire [3:0] TPU_addr;
wire [1:0] regb_addr;
wire [6:0] RAM_addr;
assign TPU_addr= addr[3:0];
assign regb_addr = addr[1:0];
assign RAM_addr = addr[6:0];

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Basic Core of TPU EEE 304 (January 2023) A2 Page 07
 TPU TPU_1(clk,reset,rb1_to_TPU_1,rb1_to_TPU_2,rb1_to_TPU_3,rb1_to_TPU_4,
rb2_to_TPU_1,rb2_to_TPU_2,rb2_to_TPU_3,rb2_to_TPU_4,
Wbus,
out1,out2,out3,out4,TPU_addr,en,Cen);
regB rb1(nLb1,clk,Wbus,rb1_to_TPU_1,rb1_to_TPU_2,rb1_to_TPU_3,rb1_to_TPU_4,regb_addr,rd,wr);
regB rb2(nLb2,clk,Wbus,rb2_to_TPU_1,rb2_to_TPU_2,rb2_to_TPU_3,rb2_to_TPU_4,regb_addr,rd,wr);
ram1 RAM1(clk, rd, wr, re, RAM_addr, out);
outreg outreg1(nLo, clk, Wbus, Wbus);

endmodule

module TPU(clk,reset, in1,in2,in3,in4,

add1,add2,add3,add4,
Wxy,
out1,out2,out3,out4,addr,en,Cen);//en= calculation enable //loading mode
input wire clk,en,reset,Cen;
input wire [7:0] in1,in2,in3,in4,add1,add2,add3,add4,Wxy;
output wire[7:0] out1,out2,out3,out4;
wire [7:0] out11,out21,out31,out41, out12,out22,out32,out42, out13,out23,out33, out43,out14,out24,out34,out44;
input wire [3:0] addr;
wire [15:0]load;
wire load11,load21,load31,load41,
load12,load22,load32,load42,
load13,load23,load33,load43,
load14,load24,load34,load44;

decoder_4x16 dec(load,addr);
assign {load11,load21,load31,load41,load12,load22,load32,load42,load13,load23,load33,load43,load14,load24,load34,load44}=load;

muladd stage11(clk,in1,add1,Wxy,load11,out11,en,Cen); //1st column

muladd stage21(clk,in1,add2,Wxy,load21,out21,en,Cen);
muladd stage31(clk,in1,add3,Wxy,load31,out31,en,Cen);
muladd stage41(clk,in1,add4,Wxy,load41,out41,en,Cen);

muladd stage12(clk,in2,out11,Wxy,load12,out12,en,Cen); //2nd column

muladd stage22(clk,in2,out21,Wxy,load22,out22,en,Cen);
muladd stage32(clk,in2,out31,Wxy,load32,out32,en,Cen);
muladd stage42(clk,in2,out41,Wxy,load42,out42,en,Cen);

muladd stage13(clk,in3,out12,Wxy,load13,out13,en,Cen); //3rd column

muladd stage23(clk,in3,out22,Wxy,load23,out23,en,Cen);
muladd stage33(clk,in3,out32,Wxy,load33,out33,en,Cen);
muladd stage43(clk,in3,out42,Wxy,load43,out43,en,Cen);

muladd stage14(clk,in4,out13,Wxy,load14,out14,en,Cen); //4th column

muladd stage24(clk,in4,out23,Wxy,load24,out24,en,Cen);
muladd stage34(clk,in4,out33,Wxy,load34,out34,en,Cen);
muladd stage44(clk,in4,out43,Wxy,load44,out44,en,Cen);

assign out1=out14;
assign out2=out24;
assign out3=out34;
assign out4=out44;
endmodule

module muladd(clk ,in, add, Wxy, load, out,en,Cen);

input [7:0] in, add, Wxy;
input clk ,load,en,Cen;
reg [7:0] t;
output reg [7:0] out;

always @(posedge clk)

if (load&en) t = Wxy;

else if(Cen) begin

out <= t*in + add;
end
endmodule

//4 to 16 decoder
module decoder_4x16 (d_out, d_in);

output [15:0] d_out;

input [3:0] d_in;
parameter tmp = 16'b1000_0000_0000_0000;

assign d_out = (d_in == 4'b0000) ? tmp :

(d_in == 4'b0001) ? tmp>>1:
(d_in == 4'b0010) ? tmp>>2:
(d_in == 4'b0011) ? tmp>>3:

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Basic Core of TPU EEE 304 (January 2023) A2 Page 08
 (d_in == 4'b0100) ? tmp>>4:
(d_in == 4'b0101) ? tmp>>5:
(d_in == 4'b0110) ? tmp>>6:
(d_in == 4'b0111) ? tmp>>7:
(d_in == 4'b1000) ? tmp>>8:
(d_in == 4'b1001) ? tmp>>9:
(d_in == 4'b1010) ? tmp>>10:
(d_in == 4'b1011) ? tmp>>11:
(d_in == 4'b1100) ? tmp>>12:
(d_in == 4'b1101) ? tmp>>13:
(d_in == 4'b1110) ? tmp>>14:
(d_in == 4'b1111) ? tmp>>15: 16'bxxxx_xxxx_xxxx_xxxx;

endmodule

module regB(nLb, clk, in,out1,out2,out3,out4,addr,rd,wr);

input clk, nLb,rd,wr;

input [1:0] addr;

// parameter wordsize = 8;

input [7:0] in;

reg [7:0] memB[0:3];

output reg [7:0] out1,out2,out3,out4;

always @ (posedge clk)

begin

if(!nLb) begin

if(rd & !wr)

memB[addr]<= in;

else if(!rd & wr)

begin

out1 <= memB[0];

out2 <= memB[1];

out3 <= memB[2];

out4 <= memB[3];

end

end

end

endmodule

module ram1(clk, rd, wr, ce, addr, out);

input clk, rd, wr, ce;
output reg [7:0] out;
//input [7:0] in;
input [6:0] addr;
reg [7:0]
r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30,r31,r32,r33,r34,r35,r36,r37,r38,r39,r40,r41,r42,r
43,r44,r45,r46,r47,r48,r49,r50,r51,r52,r53,r54,r55,r56,r57,r58,r59,r60,r61,r62,r63,r64,r65,r66,r67,r68,r69,r70,r71,r72,r73,r74,r75,r76,r77,r78,r79,r80,r81,r82,r
83,r84,r85,r86,r87,r88,r89,r90,r91,r92,r93,r94,r95,r96,r97,r98,r99,r100,r101,r102,r103,r104,r105,r106,r107,r108,r109,r110,r111,r112,r113,r114,r115,r116,r11
7,r118,r119,r120,r121,r122,r123,r124,r125,r126,r127;
reg [7:0] data;
initial begin

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Basic Core of TPU EEE 304 (January 2023) A2 Page 09
 //$readmemh("ram.mem",rammem);
r0 <= 8'h06;
r1 <= 8'h06;
r2 <= 8'h03;
r3 <= 8'h04;
r4 <= 8'h03;
r5 <= 8'h05;
r6 <= 8'h03;
r7 <= 8'h02;
r8 <= 8'h02;
r9 <= 8'h00;
r10 <= 8'h06;
r11 <= 8'h01;
r12 <= 8'h04;
r13 <= 8'h00;
r14 <= 8'h07;
r15 <= 8'h00;
r16 <= 8'h01;
r17 <= 8'h03;
r18 <= 8'h06;
r19 <= 8'h05;
r20 <= 8'h05;
r21 <= 8'h03;
r22 <= 8'h03;
r23 <= 8'h07;
end

always@ (negedge clk) //asynchronous RAM

begin
if(rd&&ce) begin
case(addr)
0: data<=r0;
1: data<=r1;
2: data<=r2;
3: data<=r3;
4: data<=r4;
5: data<=r5;
6: data<=r6;
7: data<=r7;
8: data<=r8;
9: data<=r9;
10: data<=r10;
11: data<=r11;
12: data<=r12;
13: data<=r13;
14: data<=r14;
15: data<=r15;
16: data<=r16;
17: data<=r17;
18: data<=r18;
19: data<=r19;
20: data<=r20;
21: data<=r21;
22: data<=r22;
23: data<=r23;
24: data<=r24;
25: data<=r25;
26: data<=r26;
27: data<=r27;
28: data<=r28;
29: data<=r29;
30: data<=r30;
31: data<=r31;
32: data<=r32;
33: data<=r33;
34: data<=r34;
35: data<=r35;
36: data<=r36;
37: data<=r37;
38: data<=r38;
39: data<=r39;
40: data<=r40;
41: data<=r41;
42: data<=r42;
43: data<=r43;
44: data<=r44;
45: data<=r45;
46: data<=r46;
47: data<=r47;
48: data<=r48;
49: data<=r49;
50: data<=r50;
51: data<=r51;
52: data<=r52;
53: data<=r53;
54: data<=r54;
55: data<=r55;
56: data<=r56;

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Basic Core of TPU EEE 304 (January 2023) A2 Page 10
 57: data<=r57;
58: data<=r58;
59: data<=r59;
60: data<=r60;
61: data<=r61;
62: data<=r62;
63: data<=r63;
64: data<=r64;
65: data<=r65;
66: data<=r66;
67: data<=r67;
68: data<=r68;
69: data<=r69;
70: data<=r70;
71: data<=r71;
72: data<=r72;
73: data<=r73;
74: data<=r74;
75: data<=r75;
76: data<=r76;
77: data<=r77;
78: data<=r78;
79: data<=r79;
80: data<=r80;
81: data<=r81;
82: data<=r82;
83: data<=r83;
84: data<=r84;
85: data<=r85;
86: data<=r86;
87: data<=r87;
88: data<=r88;
89: data<=r89;
90: data<=r90;
91: data<=r91;
92: data<=r92;
93: data<=r93;
94: data<=r94;
95: data<=r95;
96: data<=r96;
97: data<=r97;
98: data<=r98;
99: data<=r99;

100: data<=r100;

101: data<=r101;

102: data<=r102;

103: data<=r103;

104: data<=r104;

105: data<=r105; 106: data<=r106;

107: data<=r107;

108: data<=r108;

109: data<=r109;

110: data<=r110;

111: data<=r111;

112: data<=r112;

113: data<=r113;

114: data<=r114;

115: data<=r115;

116: data<=r116;

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Basic Core of TPU EEE 304 (January 2023) A2 Page 11
 117: data<=r117;

118: data<=r118;

119: data<=r119;

120: data<=r120;

121: data<=r121;

122: data<=r122;

123: data<=r123;

124: data<=r124;

125: data<=r125;

126: data<=r126;

127: data<=r127;
endcase
if(ce) out<=data;
else out<=8'bzzzzzzzz;
end
//data <= ce? rammem1 : 8'bzzzzzzzz;
else if(wr&&ce)
begin
//data<=in;
case(addr)
0: r0<=data;

1: r1<=data;

2: r2<=data;

3: r3<=data;

4: r4<=data;

5: r5<=data;

6: r6<=data;

7: r7<=data;

8: r8<=data;

9: r9<=data;

10: r10<=data;

11: r11<=data;

12: r12<=data;

13: r13<=data;

14: r14<=data;

15: r15<=data;

16: r16<=data;

17: r17<=data;

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Basic Core of TPU EEE 304 (January 2023) A2 Page 12
 18: r18<=data;

19: r19<=data; 20: r20<=data;

21: r21<=data;

22: r22<=data;

23: r23<=data;

24: r24<=data;

25: r25<=data;

26: r26<=data; 27: r27<=data;

28: r28<=data;

29: r29<=data;

30: r30<=data;

31: r31<=data;

32: r32<=data;

33: r33<=data;

34: r34<=data;

35: r35<=data;

36: r36<=data;

37: r37<=data;

38: r38<=data;

39: r39<=data;

40: r40<=data;

41: r41<=data;

42: r42<=data;

43: r43<=data;

44: r44<=data;

45: r45<=data;

46: r46<=data;

47: r47<=data;

48: r48<=data;

49: r49<=data;

50: r50<=data;

51: r51<=data;

52: r52<=data;

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Basic Core of TPU EEE 304 (January 2023) A2 Page 13
 53: r53<=data; 54: r54<=data;

55: r55<=data; 56: r56<=data; 57: r57<=data; 58: r58<=data;

59: r59<=data; 60: r60<=data;

61: r61<=data;

62: r62<=data;

63: r63<=data; 64: r64<=data;

65: r65<=data;

66: r66<=data; 67: r67<=data;

68: r68<=data;

69: r69<=data;

70: r70<=data;

71: r71<=data;

72: r72<=data;

73: r73<=data; 74: r74<=data; 75: r75<=data; 76: r76<=data; 77: r77<=data;

78: r78<=data; 79: r79<=data;

80: r80<=data;

81: r81<=data; 82: r82<=data; 83: r83<=data; 84: r84<=data; 85: r85<=data;

86: r86<=data; 87: r87<=data; 88: r88<=data; 89: r89<=data; 90: r90<=data;

91: r91<=data;

92: r92<=data

93: r93<=data;

94: r94<=data;

95: r95<=data;

96: r96<=data;

97: r97<=data;

98: r98<=data; 99: r99<=data;

100: r100<=data;

101: r101<=data;

102: r102<=data;

103: r103<=data;

104: r104<=data;

105: r105<=data;

106: r106<=data; 107: r107<=data;

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Basic Core of TPU EEE 304 (January 2023) A2 Page 14
 108: r108<=data;

109: r109<=data;

110: r110<=data;

111: r111<=data;

112: r112<=data;

113: r113<=data;

114: r114<=data;

115: r115<=data

116: r116<=data; 117: r117<=data;

119: r119<=data;

120: r120<=data;

121: r121<=data;

123: r123<=data; 125: r125<=data;

126: r126<=data;

127: r127<=data;
endcase
end
end

Endmodule

module outreg(nLo, clk, in, out);

input clk, nLo;
input [7:0] in;
output [7:0] out;
reg [7:0] out;
always @ (posedge clk)
begin
if(!nLo) out = in;
end
endmodule

4 Implementation

4.1 Description
Introduction to Linear Regression:
Linear regression is a fundamental statistical technique used in machine learning and statistics for
modeling the relationship between a dependent variable (usually denoted as 'y') and one or more
independent variables (usually denoted as 'x'). It assumes a linear relationship between these
variables and aims to find the best-fitting linear equation (a straight line in simple linear regression)
that predicts the dependent variable based on the independent ones.
The linear regression equation typically takes the form:
y = mx + b
Where:
 'y' is the dependent variable.
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Basic Core of TPU EEE 304 (January 2023) A2 Page 15
  'x' is the independent variable.
 'm' is the slope of the line (the coefficient).
 'b' is the y-intercept.
The goal of linear regression is to find the optimal values of 'm' and 'b' that minimize the sum of
squared differences between the predicted values and the actual data points.
Execution of Linear Regression on TPU:
To execute linear regression on a Tensor Processing Unit (TPU), you can follow these steps:
1. Data Preparation: First, prepare your dataset with the independent and dependent variables.
Ensure that the data is properly preprocessed and cleaned.
2. Model Definition: Define a linear regression model. In this case, the model consists of a
linear equation (y = mx + b). TPUs are highly efficient at handling mathematical
computations, making them suitable for linear regression tasks.
3. Training: Use your dataset to train the linear regression model. During training, the TPU
will compute the optimal values for 'm' and 'b' by minimizing the loss function, typically
mean squared error (MSE), through gradient descent or another optimization method.
4. Inference: Once the model is trained, you can use it for inference. Provide new independent
variables ('x') to the model, and the TPU will quickly calculate the predicted values ('y')
based on the learned coefficients ('m' and 'b').
TPUs offer significant advantages for executing linear regression and other machine learning tasks
due to their high computational power and parallel processing capabilities. They can handle large
datasets and complex models efficiently, reducing the time required for training and inference,
which is particularly beneficial for real-time and large-scale applications.

4.2 Experiment and Data Collection

Procedure:
1. Choose a pre-trained deep learning model (e.g., ResNet-50) and load it onto both the FPGA
and GPU.
2. Preprocess the dataset to match the model's input requirements.
3. Run inference tests on both the FPGA-based TPU and GPU using the same dataset.
4. Conduct multiple rounds of testing to ensure consistency and collect sufficient data points.
5. Analyze the collected data to compare the FPGA-based TPU's performance with the GPU.
6. Perform statistical tests to determine if any observed differences are statistically significant.

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4.3 Data Analysis

The values found from experiment and theoretical calculation were compared to assess output
quality.

4.4 Results

The matrix multiplication block and overall TPU successfully performed the numerical
calculations.

5 Design Analysis and Evaluation

5.1 Novelty
The project's novelty lies in its innovative approach to hardware acceleration using Field-
Programmable Gate Arrays (FPGAs) to replicate the functionality of Tensor Processing Units
(TPUs) for a specific deep learning architecture. While TPUs are well-established as dedicated
hardware accelerators for machine learning, the utilization of FPGAs to mimic TPU-like
operations represents a unique and forward-thinking concept.
This approach offers several key advantages. Firstly, it leverages the flexibility and re-
configurability of FPGAs to create a customizable and adaptable hardware accelerator. Unlike
fixed-function TPUs, FPGA-based TPUs can be reprogrammed to accommodate various deep
learning architectures, making them highly versatile for research and development purposes.

Furthermore, the project pioneers the implementation of a two-layer deep learning model on
FPGA, focusing on linear regression. By demonstrating the feasibility of FPGA-based
acceleration for machine learning tasks, it opens doors to new possibilities in the field of edge
computing, where customized hardware accelerators can enhance the performance of AI
applications in resource-constrained environments.

5.2 Design Considerations

Designing a TPU for practical use in real-world applications demands careful consideration of
various factors to ensure efficiency, scalability, and usability. Here are some key aspects to take into
account:
1. Scalability and Flexibility: A practical TPU should be designed with scalability in mind. It
should be capable of accommodating a range of neural network architectures and sizes. Consider the
ability to scale TPUs into clusters for handling large datasets and complex models efficiently.
2. Memory Hierarchy: Efficient memory management is crucial. Design the TPU with an
optimized memory hierarchy, including fast on-chip memory for frequently accessed data, efficient
data transfer mechanisms, and mechanisms for handling large model parameters stored in external
memory.
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3. Power Efficiency: Real-world applications often operate in power-constrained environments,
such as edge devices or data centers with power limitations. Design the TPU with a focus on power
efficiency to minimize energy consumption while maximizing computational throughput.
4. Latency and Throughput: Different applications have varying latency and throughput
requirements. Ensure that the TPU can meet the specific demands of the intended use case, whether
it's real-time processing or batch processing of data.
5. Software Integration: Practical TPUs should seamlessly integrate with popular machine learning
frameworks and software ecosystems. Compatibility with widely used frameworks like TensorFlow
and PyTorch is essential to facilitate model deployment and experimentation.
6. Programming Model: Create an accessible and user-friendly programming model for developers
and researchers. This includes providing high-level APIs and tools for programming TPUs,
abstracting low-level hardware details.
7. Error Handling and Fault Tolerance: Real-world applications often encounter errors or
hardware failures. Implement mechanisms for error handling and fault tolerance to ensure robustness
and reliability in production environments.
8. Security: Address security concerns, especially if the TPU is used in sensitive applications such
as healthcare or finance. Ensure data protection, encryption, and secure communication between
TPUs and other components of the system.
9. Deployment and Management: Consider the ease of deployment and management of TPUs in
practical settings. This includes tools for monitoring, debugging, and remote management to
streamline the operation of TPUs in production environments.
10. Interoperability: Ensure that the TPU can interoperate with other hardware components and
systems within the application ecosystem. Compatibility with existing infrastructure is crucial for
smooth integration.
11. Documentation and Support: Provide comprehensive documentation and support for
developers and users. This includes clear documentation on hardware specifications, programming
guides, and troubleshooting resources.
12. Cost-Efficiency: Real-world applications often operate under budget constraints. Balance
performance and cost considerations to make TPUs cost-effective for practical deployment.
By addressing these practical design considerations, a TPU can be tailored to meet the demands of
real-world applications, offering a valuable solution for accelerating machine learning workloads in
a variety of domains and use cases.
Impact on Society and the Tech Industry
The project's impact on society and the tech industry is poised to be profound, bringing about
significant advancements in machine learning hardware and influencing various domains:
1. Advancing Machine Learning: The project showcases the potential of FPGA-based TPUs
to democratize machine learning acceleration. By providing a cost-effective and
customizable solution, it empowers a broader range of researchers, startups, and
organizations to harness the benefits of specialized hardware for machine learning. This
democratization could lead to accelerated innovation in fields like healthcare, autonomous
vehicles, and finance, where AI plays a critical role.
2. Empowering Edge Computing: In an era of edge computing, where processing happens
closer to data sources, FPGA-based TPUs offer a sustainable solution. Their energy
efficiency and flexibility make them ideal for edge devices, enabling real-time AI processing
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Basic Core of TPU EEE 304 (January 2023) A2 Page 18
 in applications like smart cities, IoT devices, and medical devices. This shift reduces the
need for data transfer to centralized data centers, reducing latency and improving privacy.
3. Innovation in FPGA Technology: The project contributes to the evolution of FPGA
technology. It explores novel use cases for FPGAs beyond traditional applications, such as
digital signal processing and cryptography. This innovation could inspire FPGA
manufacturers to further enhance their devices for machine learning workloads, ultimately
benefiting a wide range of industries.
4. Education and Research: The project serves as an educational resource and a foundation
for future research. It equips students, researchers, and engineers with hands-on experience
in hardware acceleration, FPGA programming, and machine learning, fostering a deeper
understanding of the intersection between hardware and AI.

5. Sustainability: FPGA-based TPUs have the potential to promote sustainability in AI computing.

Their energy-efficient design reduces the carbon footprint associated with data center operations,
aligning with global efforts to reduce energy consumption in technology infrastructure.

5.3Investigations

5.3.1 Literature Review

The literature review provided a robust foundation for our project, offering insights into the
significance of TPUs, the potential of FPGA-based accelerators, and the ethical considerations
within the field of AI and hardware acceleration. This analysis not only informed our project's design
and objectives but also positioned it within the broader landscape of AI research and development.
5.3.2 Experiment Design
5.3.3 Data Analysis and Interpretation

5.4 Limitations of Tools

Here are some potential technical limitations:

1. Limited Model Complexity: FPGA-based TPUs have limitations in terms of the
complexity of neural network models they can efficiently support. Very deep or highly
complex models may not fit well within the resource constraints of FPGAs.
2. Resource Utilization: FPGA resources such as logic elements, memory, and DSP blocks are
finite. Utilizing these efficiently for deep learning models, especially larger ones, can be
challenging.
3. Reconfiguration Overhead: While FPGAs offer flexibility, reconfiguring them for
different models or tasks may introduce latency and overhead, which could impact real-time
applications.
4. Memory Bandwidth: FPGAs may have limited memory bandwidth compared to
specialized hardware like TPUs. This limitation could affect performance, particularly for
memory-intensive deep learning tasks.
5. Training vs. Inference: FPGAs are typically better suited for inference rather than training
deep learning models. Training deep networks on FPGAs can be slow and resource-
intensive.
6. Programming Complexity: Designing and programming FPGA-based TPUs can be more
complex than using off-the-shelf TPUs or GPUs, requiring expertise in hardware description
languages like Verilog and FPGA design.

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Basic Core of TPU EEE 304 (January 2023) A2 Page 19
 7. Energy Efficiency: Depending on the FPGA's design and usage, it may not achieve the
same level of energy efficiency as dedicated TPUs, which are optimized for neural network
workloads.
8. Compatibility: FPGA-based TPUs do not seamlessly integrate with all machine learning
frameworks or software libraries, requiring additional development effort for compatibility.
9. Size and Form Factor: The physical size and form factor of FPGA boards may limit their
use in certain applications or deployment scenarios.
10. Scalability: Scaling up FPGA-based TPUs for large-scale machine learning tasks are
challenging and may require multiple FPGAs and complex interconnects.

5.5 Impact Assessment

5.5.1 Assessment of Societal and Cultural Issues
Impact on Society and the Tech Industry
The project's impact on society and the tech industry is poised to be profound, bringing about
significant advancements in machine learning hardware and influencing various domains:
1. Advancing Machine Learning: The project showcases the potential of FPGA-based TPUs
to democratize machine learning acceleration. By providing a cost-effective and
customizable solution, it empowers a broader range of researchers, startups, and
organizations to harness the benefits of specialized hardware for machine learning. This
democratization could lead to accelerated innovation in fields like healthcare, autonomous
vehicles, and finance, where AI plays a critical role.
2. Empowering Edge Computing: In an era of edge computing, where processing happens
closer to data sources, FPGA-based TPUs offer a sustainable solution. Their energy
efficiency and flexibility make them ideal for edge devices, enabling real-time AI processing
in applications like smart cities, IoT devices, and medical devices. This shift reduces the
need for data transfer to centralized data centers, reducing latency and improving privacy.
3. Innovation in FPGA Technology: The project contributes to the evolution of FPGA
technology. It explores novel use cases for FPGAs beyond traditional applications, such as
digital signal processing and cryptography. This innovation could inspire FPGA
manufacturers to further enhance their devices for machine learning workloads, ultimately
benefiting a wide range of industries.
4. Education and Research: The project serves as an educational resource and a foundation
for future research. It equips students, researchers, and engineers with hands-on experience
in hardware acceleration, FPGA programming, and machine learning, fostering a deeper
understanding of the intersection between hardware and AI.

5.5.2 Assessment of Health and Safety Issues

FPGA-based TPUs have the potential to promote sustainability in AI computing. Their energy-
efficient design reduces the carbon footprint associated with data center operations, aligning
with global efforts to reduce energy consumption in technology infrastructure.

5.5.3 Assessment of Legal Issues

Our project, focused on the development of FPGA-based Tensor Processing Units (TPUs) for deep
________________________________________________________________________________________
Basic Core of TPU EEE 304 (January 2023) A2 Page 20
learning, involves various legal considerations that are crucial to address. Understanding and
complying with legal requirements is essential to ensure the ethical and legal integrity of our
research and development efforts.

Intellectual Property Rights: One of the foremost legal concerns is intellectual property rights. We
must be vigilant in ensuring that our project does not infringe upon any existing patents, copyrights,
or trademarks related to TPUs, FPGA technology, or machine learning algorithms. Proper due
diligence and clearance for the use of any proprietary technology or software are necessary.

Patent Applications: If our project results in novel inventions or innovations, we should consider
filing for patents to protect our intellectual property. Engaging with legal counsel experienced in
patent law can be beneficial in this regard.

Regulatory Compliance: Depending on the application of our project, we may need to consider
industry-specific regulations. For instance, in healthcare or autonomous vehicles, regulatory
compliance may be necessary to ensure safety and legal conformity.

Documentation and Records: Maintaining thorough documentation of our project's development,

testing, and compliance efforts is essential. Good record-keeping can be invaluable in demonstrating
legal compliance if questions or issues arise.

5.6Sustainability and Environmental Impact Evaluation

The sustainability of TPUs, whether dedicated or FPGA-based, is a crucial consideration in today's
environmentally conscious world. Evaluation of TPU's Sustainability:
1. Energy Efficiency: TPUs, including FPGA-based variants, are renowned for their energy
efficiency. They perform more computations per watt of power consumed compared to
general-purpose CPUs and GPUs. This efficiency translates into reduced energy
consumption and operational costs in data centers and edge devices.
2. Reduced Data Center Footprint: By accelerating machine learning workloads efficiently,
TPUs contribute to reducing the size and power requirements of data centers. This results in
a smaller physical and environmental footprint, as fewer resources are needed for cooling
and maintenance.
3. Edge Computing Benefits: FPGA-based TPUs are particularly suited for edge computing,
where power constraints are common. Their low power consumption enables AI processing
at the edge without excessive energy demands, making them an eco-friendly choice for IoT
devices and autonomous systems.
4. Extended Hardware Lifecycle: FPGAs have the advantage of reconfigurability. This
extends the lifespan of the hardware, reducing electronic waste as organizations can
repurpose FPGAs for different tasks or upgrade them with new designs without discarding
the entire hardware.
In summary, TPUs, including FPGA-based variants, offer a sustainable solution for accelerating AI
workloads. Their energy efficiency, reduced data center footprint, suitability for edge computing,
and extended hardware lifecycle contribute to a more environmentally responsible approach to AI
and machine learning in both industry and society.

________________________________________________________________________________________
Basic Core of TPU EEE 304 (January 2023) A2 Page 21
5.7Ethical Issues
Challenge - 1: Ensuring that the hardware components we used were ethically sourced, considering
factors like environmental impact and labor conditions.
Mitigation: We researched and selected suppliers with a commitment to ethical practices. Whenever
feasible, we opted for components with a minimal environmental footprint and adhered to ethical
labor standards.
Challenge -2: Ensuring the safety and reliability of our FPGA-based TPUs was paramount.
Mitigation: Rigorous testing, validation, and quality assurance measures were implemented to detect
and rectify any potential issues. We followed best practices in hardware design and testing, focusing
on safety and performance.

6 Reflection on Individual and Team work

6.1 Individual Contribution of Each Member

Project Planning and Coordination: [1906036] took on the role of project coordinator,
ensuring that our efforts were synchronized and aligned with the project timeline. They
organized regular team meetings, set milestones, and facilitated communication among team
members.
Hardware Design and Implementation: [1906050] specialized in hardware design and FPGA
programming. Their expertise was instrumental in crafting the FPGA-based TPU architecture,
from the systolic array to memory management. They meticulously optimized the hardware
design for maximum efficiency.
Software Integration and Compatibility: [1906043] focused on software integration, ensuring
that our FPGA-based TPU seamlessly interfaced with machine learning frameworks like
TensorFlow. They were responsible for creating a user-friendly programming model,
abstracting low-level hardware details, and ensuring compatibility with popular software tools.
Performance Evaluation and Benchmarking: [1906034] led the performance evaluation and
benchmarking efforts. They designed and conducted rigorous tests to assess the FPGA-based
TPU's efficiency, scalability, and energy consumption. Their insights guided optimizations and
validated the project's viability.

6.2 Mode of Team Work

To establish balanced teamwork, we adopted the following strategies:
 Regular Communication: We held weekly team meetings to discuss progress, challenges,
and goals. This open and transparent communication ensured that everyone was on the same
page and that issues were addressed promptly.
 Task Allocation: We carefully distributed tasks based on individual strengths and interests.
This approach allowed each team member to leverage their expertise and contribute
meaningfully to the project.
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Basic Core of TPU EEE 304 (January 2023) A2 Page 22
  Peer Review: We implemented a peer review system for code and documentation, ensuring
that the quality of our work remained consistently high. This process encouraged knowledge
sharing and helped us identify and rectify potential issues early on.
 Flexibility and Adaptability: We remained flexible and adaptable throughout the project.
When unexpected challenges arose, we collaborated to find creative solutions and adjust our
approach as needed.
 Continuous Learning: We encouraged a culture of continuous learning within the team.
Each team member shared new insights and knowledge gained during the project, fostering a
collaborative environment that nurtured individual growth.

6.3 Diversity Statement of Team

"Our team values diversity, fostering an inclusive environment where unique perspectives and
backgrounds enrich our collaborative efforts, fuel innovation, and drive our project's success."

7 Communication

7.1 Executive Summary

Curious Student Team Unveils FPGA-Based AI Accelerator to Enhance Machine Learning. A

passionate team of curious students has introduced an FPGA-based Tensor Processing Unit
(TPU), a custom AI accelerator, aimed at exploring and improving deep learning capabilities.
This project, similar to AI processors in smartphones, represents a significant step in their
journey to understand and contribute to the world of artificial intelligence. Their commitment
to learning and inclusivity promises a positive impact on AI in various fields.

7.2 User Manual

1. Open the FPGA development environment on your computer.

2. Load the TPU configuration provided with the project.
3. Ensure that the FPGA board is successfully programmed with the TPU design.
4. After training, save the trained model.
5. Load the trained model onto the FPGA.
6. Perform inference on new data using the FPGA-based TPU. Measure inference speed and
accuracy.

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Basic Core of TPU EEE 304 (January 2023) A2 Page 23
8 Project Management and Cost Analysis

Project Management:

Effective project management was central to our success. We employed agile methodologies,
ensuring regular team meetings, task tracking, and adapting to evolving project needs. Clear
roles and responsibilities promoted collaboration, keeping us on track and focused.

Cost Analysis:

Our project's cost analysis encompassed FPGA development boards, hardware components, and
research materials.

8.1 Bill of Materials

FPGA board was taken from the laboratory, so no extra expenditure occurred from our end.

9 Future Work

Future work scopes include:

Optimization: Enhance TPU's efficiency for larger models.

Hardware Integration: Explore TPU integration into edge devices.

Energy Efficiency: Focus on reducing power consumption.

Open Source Community: Contribute FPGA-based TPU designs to open-source projects.

Real-time Applications: Extend TPU for real-time AI tasks.

Continuous Learning: Stay updated with evolving AI technologies and ethical practices.

10 References

1. Jouppi, Norman P., et al. "In-Datacenter Performance Analysis of a Tensor Processing

Unit." Proceedings of the 44th Annual International Symposium on Computer Architecture
(ISCA), 2017.
2. Google AI Blog. "Tensor Processing Units: Evolution." Link
3. Xilinx. "FPGA-Based Deep Learning Inference: A Performance and Power Analysis." Link
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Basic Core of TPU EEE 304 (January 2023) A2 Page 24
 4. Chollet, François. "Xception: Deep Learning with Depthwise Separable Convolutions."
Proceedings of the IEEE conference on computer vision and pattern recognition (CVPR),
2017.
5. Abadi, Martín, et al. "TensorFlow: A System for Large-Scale Machine Learning."
Proceedings of the 12th USENIX Conference on Operating Systems Design and
Implementation (OSDI), 2016.
Literature Review Sources:
1. Zhang, Y., Li, J., Yi, J., Li, J., & Zhang, Y. "Deep Learning on FPGAs: A Comprehensive
Review." IEEE Transactions on Neural Networks and Learning Systems, 2020.
2. Sim, J., Park, J., & Choo, H. "A Survey of FPGA-based Neural Network Inference
Accelerators." IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.
3. Zhang, Chongyang, et al. "A Comprehensive Survey of Hardware Accelerators for
Convolutional Neural Networks." ACM Computing Surveys (CSUR), 2019.
YouTube Video Links:
1. Google Cloud. "Tensor Processing Units (TPUs) - Google Cloud Tech Day." Link
2. Xilinx Inc. "Xilinx Alveo™ Accelerator Cards for Data Center and Edge AI." Link
3. Stanford Online. "Hardware Accelerators for Machine Learning." Link
4. NVIDIA. "Deep Learning with GPUs: A 40-Minute Introductory Primer." Link
5. Intel. "Intel AI Webcast: AI and FPGA." Link

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