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Edc Assignment 3

EDC ASSIGNMENT

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Aritra Ghosh
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19 views9 pages

Edc Assignment 3

EDC ASSIGNMENT

Uploaded by

Aritra Ghosh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Expt. No.

3
Date:__// CLAMPING CIRCUITS (Hardware)

Aim
To design, set up and study various clamping circuits using diodes.

COMPONENETS AND EQUIPMENT REQUIRED

Sl.no Item Specifications Quantity

1 Diode 1N4001 1
2 Resistor 1kΩ 1
3 VRPS (0- 30 V) 1
4 DSO - 1
5 Capacitor 1µF 1

6 Bread Board - 1

PRECAUTIONS
1. The power should be off while giving connections.
2. The regulated power supply should be set to minimum position while giving power supply.
THEORY
At some situations it is necessary to add or subtract a dc voltage to a given waveform without
changing the shape of the waveform. Circuits used for this purpose are called clamping circuits. A
capacitor which is charged to a voltage and subsequently prevented from discharging can serve as a
suitable replacement for a dc source. This principle is utilized in clamping circuits. The clamping
level can be made at any voltage level by biasing the diode. Such a clamping circuit is called a
biased clamper.

CLAMPING POSITIVELY AT 0V
Suppose the input voltage is represented by the expression Vm.Sin(t) during one negative
half cycle of the input sine wave, the diode conducts and capacitor charges to Vm with positive
polarity at right side of the capacitor. During the positive half cycle of the input sine wave, the
capacitor cannot discharge since the diode does not conduct. Thus capacitor acts as a dc source of
Vm volts connected in series with input signal source., the output voltage then can be expressed as
Vo = Vm + Vm. Sin (t).

CLAMPING NEGATIVELY AT +3V


During the positive half cycle of the input sine wave, capacitor charges through the dc source
and diode till (Vm – 3) volts, with negative polarity of the capacitor at its right side. The charging of
the capacitor is limited to (Vm – 3) volts due to the presence of the dc source. The output is
expressed as Vo = - (Vm – 3) + Vm Sin t.

CLAMPING POSITIVELY AT +3 V

During one negative half cycle of the input sine wave, capacitor charges through the dc
source and diode till (Vm + 3) V with positive polarity of the capacitor at its right side, the charging
of the capacitor is extended up to (Vm + 3) V due to the presence of the dc source. The output is
then expressed as Vo = (Vm + 3) + Vm Sin(t).

Note: 0.6 V is not negligible compared to clamping voltage of 3V.

PROCEDURE
1. Set up the circuit after testing the components.
2. Set the amplitude of the input sine wave at 20 V peak, if the input sine wave has any dc
level, nullify it by turning the offset knob of the signal generator. Set the frequency to be
1 kHz.
3. Observe the input and output on CRO screen simultaneously keeping AC-DC switch of
the CRO in DC position.

CIRCUIT DIAGRAM

1. CLAMPING POSITIVELY AT 0V
C1

1 F
1µF D1

IN400

Vm.Sin(wt)
2. CLAMPING NEGATIVELY AT +3V

1µF

Vm.Sin(wt)

3. CLAMPING POSITIVELY AT +3 V

1µF

Vm.Sin(wt)

RESULT

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