Intel® Extreme Memory Profile

(Intel® XMP) 2.0

Specification

Enthusiast Extension to the JEDEC DDR4 SPD Specification

December 2013

Revision 1.0

Intel Confidential

Document Number: IBL# 541356

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Copyright © 2013, Intel Corporation. All Rights Reserved.

2 Intel Confidential IBL# 541356

Contents
1 Introduction .............................................................................................................. 7
2 Address Map .............................................................................................................. 8
2.1 Address Map....................................................................................................... 8
2.2 Global Bytes 384 to 392 ..................................................................................... 10
2.2.1 Byte 384 and 385: Intel® XMP Identification String..................................... 10
2.2.2 Byte 386: Intel® XMP Organization & Configuration.................................... 11
2.2.3 Byte 387: Intel® XMP Revision ................................................................. 11
2.2.4 Byte 388: Timebases for Profile 1 ............................................................. 12
2.2.5 Byte 389: Timebases for Profile 2 ............................................................. 12
2.2.6 Bytes 390,391,392: RFU ......................................................................... 14
2.3 Details of Each Byte 393 to 486 .......................................................................... 14
2.3.1 Byte 393 or 440: Module VDD Voltage Level .............................................. 15
2.3.2 Bytes 394/395 or 441/442: RFU............................................................... 15
2.3.3 Byte 396 or 443: Minimum SDRAM Cycle Time (tCKAVGmin) .......................... 16
2.3.4 Byte 397 or 444: CAS Latencies Supported, First Byte
Byte 398 or 445: CAS Latencies Supported, Second Byte
Byte 399 or 446: CAS Latencies Supported, Third Byte
Byte 400 or 447: CAS Latencies Supported, Fourth Byte.............................. 16
2.3.5 Byte 401 or 448: Minimum CAS Latency Time (tAAmin) .............................. 17
2.3.6 Byte 402 or 449: Minimum RAS# to CAS# Delay Time (tRCDmin) ................ 18
2.3.7 Byte 403 or 450: Minimum Row Precharge Delay Time (tRPmin)................... 19
2.3.8 Byte 404 or 451: Upper Nibbles for tRAS and tRC ....................................... 19
2.3.9 Byte 405 or 452: Minimum Active to Precharge Delay Time (tRASmin), Least
Significant Byte...................................................................................... 19
2.3.10 Byte 406 or 453: Minimum Active to Active/Refresh Delay Time (tRCmin), Least
Significant Byte...................................................................................... 20
2.3.11 Byte 407 or 454: Minimum Refresh Recovery Delay Time (tRFC1min), LSB .... 21
2.3.12 Byte 409 or 456: Minimum Refresh Recovery Delay Time (tRFC2min), LSB .... 21
2.3.13 Byte 411 or 458: Minimum Refresh Recovery Delay Time (tRFC4min), LSB .... 22
2.3.14 Byte 413 or 460: Upper Nibble for tFAW .................................................... 22
2.3.15 Byte 414 or 461: Minimum Four Activate Window Delay Time (tFAWmin), Least
Significant Byte...................................................................................... 23
2.3.16 Byte 415 or 462: Minimum Activate to Activate Delay Time (tRRD_Smin),
Different Bank Group .............................................................................. 23
2.3.17 Byte 416 or 463: Minimum Activate to Activate Delay Time (tRRD_Lmin), same
bank group............................................................................................ 24
2.3.18 Bytes 417-422 or 464-469: RSVD in Profiles .............................................. 24
2.3.19 Bytes 423 & 424 or 470 & 471: RSVD for Supplier Custom Mods .................. 25
2.3.20 Byte 425 or 472: Fine Offset for Minimum Row Active to Row Active Delay Time
(tRRD_Lmin), same bank group ............................................................... 25
2.3.21 Byte 426 or 473: Fine Offset for Minimum Row Active to Row Active Delay Time
(tRRD_Smin), different bank group........................................................... 25
2.3.22 Byte 427 or 474: Fine Offset for Minimum Active to Active/Refresh Delay Time
(tRCmin)............................................................................................... 25
2.3.23 Byte 428 or 475: Fine Offset for Minimum Row Precharge Delay Time (tRPmin) ..
25
2.3.24 Byte 429 or 476: Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
25

IBL# 541356 Intel Confidential 3

Tables
2-1 tCKAVGmin SPD Calculations Using MTB and FTB..........................................................13
2-2 Timing Parameters using both MTB and FTB .................................................................13
2-3 Two’s Complement Encoding Fine Timebase Offset........................................................13

4 Intel Confidential IBL# 541356

Revision History

Document Revision
Description Revision Date
Number Number

IBL# 541356 1.0 • Initial release December 2013

§§

IBL# 541356 Intel Confidential 5

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6 Intel Confidential IBL# 541356

Introduction

1 Introduction

Intel® Extreme Memory Profile (Intel® XMP) provides a simple and robust high
performance, DDR4-based memory solution for Intel-based platforms. Modules are
designed around this specification. The XMP Spec was developed by Intel and it’s
memory partners to enable an enthusiast performance extension to the traditional
JEDEC SPD Spec.

Intel® XMPs are traditionally designed with two performance profiles. Profile 1 is used
for the Enthusiast/Certified settings and is the profile that is tested under the Intel®
XMP Certification program. Profile 2 is designed to host the extreme or fastest possible
settings that have no guardband and my or may not work on every system.

It should also be noted that Extreme Memory Profiles aren’t always defined as over-
frequency/over voltage parts. In some cases, Extreme Memory Profiles can be used to
define extremely power savvy settings or extremely fast latencies.

Intel® XMP End User Benefits

• Enables users to take advantage of the fastest DDR4 memory
• Provides a mechanism for end users to easily performance tune Intel platforms
• Enables both novice (use built-in profiles) and advanced users (manually adjust
timing parameters) to performance tune their Intel platforms.

Intel® XMP DIMM vendor benefits

• Ability for DIMM vendors to provide value added capability and performance
optimizations
• Enable DIMM vendors to differentiate Extreme Memory, designed specifically for
enthusiasts, gamer and over-clockers from other memory.

This appendix describes the Intel® XMP serial presence detect (SPD) values for all
DDR3 modules. These presence detect values are those referenced in the SPD standard
document for ‘Specific Features’ and are in some cases, are features outside of the
standard. The following SPD fields will be documented in the order presented in
Chapter 2, “Address Map”. All unused entries will be coded as 00h. All unused bits in
defined bytes will be coded as 0 except where noted. To allow for maximum flexibility
as devices evolve, SPD fields described in this document may support device
configuration and timing options that are not included in the JEDEC DDR4 SDRAM data
sheet JESD79-4. Please refer to DRAM supplier data sheets or JESD79-4 to determine
the compatibility of components.

CDI/IBL 541356 Intel Confidential 7

 Address Map

2 Address Map

2.1 Address Map

The following is the SPD address map for all DDR4 modules. It describes where the
individual lookup table entries will be held in the serial EEPROM.

Byte Number Function Described Notes

384-385 Intel® Extreme Memory Profile ID String

386 Intel® Extreme Memory Profile Organization Type

387 Intel® Extreme Memory Profile Revision

388 Timebase for Profile 1 1

389 Timebase for Profile 2 1

390 RFU 1

391 RFU 1

392 RFU - End of Global Range 1

393 Module VDD Voltage Level for Profile 1 (Certified Settings) 2

394 RFU

395 RFU

396 SDRAM Minimum Cycle Time (tCKAVGmin) 2,4

397 CAS Latencies Supported, First Byte 2,4

398 CAS Latencies Supported, Second Byte 2,4

399 CAS Latencies Supported, Third Byte 2,4

400 CAS Latencies Supported, Fourth Byte 2,4

401 Minimum CAS Latency Time (tAAmin) 2,4

402 Minimum RAS# to CAS# Delay Time (tRCDmin) 2,4

403 Minimum Row Precharge Time (tRPmin) 2,4

404 Upper Nibbles for tRAS and tRC 2,4

405 Minimum Active to Precharge Time (tRASmin), Least Significant Byte 2,4

406 Minimum Active to Active/Refresh Time (tRCmin), Least Significant Byte 2,4

407 Minimum Refresh Recovery Time (tRFC1min), Least Significant Byte 2,4

408 Minimum Refresh Recovery Time (tRFC1min), Most Significant Byte 2,4

409 Minimum Refresh Recovery Time (tRFC2min), Least Significant Byte 2,4

410 Minimum Refresh Recovery Time (tRFC2min), Most Significant Byte 2,4

411 Minimum Refresh Recovery Time (tRFC4min), Least Significant Byte 2,4

412 Minimum Refresh Recovery Time (tRFC4min), Most Significant Byte 2,4

413 Upper Nibble for tFAW 2,4

414 Minimum Four Activate Window Delay Time (tFAWmin) 2,4

Notes:
1. Global Parameters used across all profiles
2. Utilized for Profile 1 (Enthusiast / Certified Settings)
3. Utilized for Profile 2 (Extreme Settings)
4. Parameter utilized in the same fashion as the standard DDR4 SPD byte with the exception that it may
exceed the DDR4 SDRAM data sheet

8 Intel Confidential CDI/IBL 541356

Address Map

Byte Number Function Described Notes

415 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group 2,4

416 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group 2,4

417-422 RSVD

423-424 RSVD for Supplier Custom Modification in Profile 1

425 Fine Offset for Minimum Row Active to Row Active Delay Time (tRRD_Lmin), same 2,4
bank group

426 Fine Offset for Minimum Row Active to Row Active Delay Time (tRRD_Smin), 2,4
different bank group

427 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) 2,4

428 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) 2,4

429 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) 2,4

430 Fine Offset for Minimum CAS Latency Time (tAAmin) 2,4

431 Fine Offset for SDRAM Minimum Cycle Time (tCKAVGmin) 2,4

432-437 RSVD

438-439 RSVD for Supplier Custom Modification in Profile 1

440 Module VDD Voltage Level for Profile 2 (Extreme Settings) 3

441 RFU

442 RFU

443 SDRAM Minimum Cycle Time (tCKAVGmin) 3,4

444 CAS Latencies Supported, First Byte 3,4

445 CAS Latencies Supported, Second Byte 3,4

446 CAS Latencies Supported, Third Byte 3,4

447 CAS Latencies Supported, Fourth Byte 3,4

448 Minimum CAS Latency Time (tAAmin) 3,4

449 Minimum RAS# to CAS# Delay Time (tRCDmin) 3,4

450 Minimum Row Precharge Time (tRPmin) 3,4

451 Upper Nibbles for tRAS and tRC 3,4

452 Minimum Active to Precharge Time (tRASmin), Least Significant Byte 3,4

453 Minimum Active to Active/Refresh Time (tRCmin), Least Significant Byte 3,4

454 Minimum Refresh Recovery Time (tRFC1min), Least Significant Byte 3,4

455 Minimum Refresh Recovery Time (tRFC1min), Most Significant Byte 3,4

456 Minimum Refresh Recovery Time (tRFC2min), Least Significant Byte 3,4

457 Minimum Refresh Recovery Time (tRFC2min), Most Significant Byte 3,4

458 Minimum Refresh Recovery Time (tRFC4min), Least Significant Byte 3,4

459 Minimum Refresh Recovery Time (tRFC4min), Most Significant Byte 3,4

460 Upper Nibble for tFAW 3,4

461 Minimum Four Activate Window Delay Time (tFAWmin) 3,4

462 Minimum Row Active to Row Active Delay Time (tRRD_Smin), different bank 3,4
group

Notes:
1. Global Parameters used across all profiles
2. Utilized for Profile 1 (Enthusiast / Certified Settings)
3. Utilized for Profile 2 (Extreme Settings)
4. Parameter utilized in the same fashion as the standard DDR4 SPD byte with the exception that it may
exceed the DDR4 SDRAM data sheet

CDI/IBL 541356 Intel Confidential 9

 Address Map

Byte Number Function Described Notes

463 Minimum Row Active to Row Active Delay Time (tRRD_Lmin), same bank group 3,4

464-469 RSVD

470-471 RSVD for Supplier Custom Modification in Profile 2

472 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank 3,4
group

473 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), different 3,4
bank group

474 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) 3,4

475 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) 3,4

476 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) 3,4

477 Fine Offset for Minimum CAS Latency Time (tAAmin) 3,4

478 Fine Offset for SDRAM Minimum Cycle Time (tCKAVGmin) 3,4

479-484 RSVD

485-486 RSVD for Supplier Custom Modification in Profile 2

Notes:
1. Global Parameters used across all profiles
2. Utilized for Profile 1 (Enthusiast / Certified Settings)
3. Utilized for Profile 2 (Extreme Settings)
4. Parameter utilized in the same fashion as the standard DDR4 SPD byte with the exception that it may
exceed the DDR4 SDRAM data sheet

2.2 Global Bytes 384 to 392

This section contains defines bytes that are common to all extended mode profiles.

2.2.1 Byte 384 and 385: Intel® XMP Identification String

Two bytes are required to ensure that the module supports the correct performance
mode and isn’t populated with some other customer data. Potentially this string could
be used to identify incompatibility between different designs.

Byte 384] Byte 385

SDRAM / Module Type
Line #
Corresponding to Key Byte Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
Hex
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

0 Intel® XMP ID String 0 0 0 0 1 1 0 0 0 1 0 0 1 0 1 0 0C4A

- - - - - - - - - - - - - - - - - -
253 Reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 FFFD
254 Reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FFFE
255 Reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF

10 Intel Confidential CDI/IBL 541356

Address Map

2.2.2 Byte 386: Intel® XMP Organization & Configuration

This byte is primary utilized to inform the platform about which profiles are
programmed and what configuration they are designed for. In some cases, suppliers
may choose not to populate profile 2 and to avoid system BIOS confusion, bits 0 & 1
were defined. Bits 2 through 5 define the recommended channel configuration for each
profile. The rest of the bits of this byte may be used in the future to define different
profile organizations for a specific profile ID.

Bit 7-6 Bits 5-4 Bits 3-2 Bit 1 Bit 0

Profile 2 Profile 1
Reserved Recommended Recommended Profile 2 Enabled Profile 1 Enabled
Channel Config Channel Config

Reserved1 00 - 1 DIMM per CH 00 - 1 DIMM per CH 0 - Disabled 0 - Disabled

01 - 2 DIMM per CH 01 - 2 DIMM per CH 1 - Enabled 1 - Enabled2
10 - 3 DIMM per CH 10 - 3 DIMM per CH
11 - 4 DIMM per CH 11 - 4 DIMM per CH

Notes:
1. Reserved bytes must be programmed to 0 (zero)
2. Bit 0 must always be programmed to 1 - Profile 1 must always be enabled

2.2.3 Byte 387: Intel® XMP Revision

This byte describes the compatibility level of the Intel® XMP encoding of the bytes
contained in the SPD EEPROM, and the current collection of valid defined bytes. This
byte will be coded as 0x20 for SPDs with Intel® Extreme Memory Profile 2.0. Software
should examine the upper nibble (Encoding Level or Major Revision Level) to determine
if it can correctly interpret the contents of the module SPD. The lower nibble (Additions
Level or Minor Revision Level) can optionally be used to determine which additional
bytes or attribute bits have been defined since introduction of the major revision level.
Historically, Encoding Levels or Major Revision levels are rare and only introduced when
some feature is added that potentially breaks backward compatibility or significant
changes have taken place since introduction of that major revision number, in all other
cases, an additions level or minor revision level is just added to the revision number.

Note: This should now be programmed as Rev 2.0.

Encoding Level Additions Level

Intel® XMP Revision Hex
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Revision 0.0 0 0 0 0 0 0 0 0 00
Revision 0.1 0 0 0 0 0 0 0 1 01
... . . . . . . . . .
Revision 2.0 0 0 1 0 0 0 0 0 20
... . . . . . . . . ...
Undefined 1 1 1 1 1 1 1 1 FF

CDI/IBL 541356 Intel Confidential 11

 Address Map

2.2.4 Byte 388: Timebases for Profile 1

This byte defines a value in picoseconds that represents the fundamental timebase for
fine grain and medium grain timing calculations. These values are used as a multiplier
for formulating subsequent timing parameters. This is a simplification of the DDR3
specification where many combinations of divisors and dividends could be
programmed.

Bits 7-4 Bits 3-2 Bits 1-0

Medium Timebase (MTB) Fine Timebase (FTB)

0000 = Reserved 00 = 125ps 00 = 1ps

All other values reserved. All other values reserved

2.2.5 Byte 389: Timebases for Profile 2

This byte defines a value in picoseconds that represents the fundamental timebase for
fine grain and medium grain timing calculations. These values are used as a multiplier
for formulating subsequent timing parameters. This is a simplification of the DDR3
specification where many combinations of divisors and dividends could be
programmed.

Bits 7-4 Bits 3-2 Bits 1-0

Medium Timebase (MTB) Fine Timebase (FTB)

0000 = Reserved 00 = 125ps 00 = 1ps

All other values reserved. All other values reserved

2.2.5.1 Relating the MTB and FTB

When a timing value tXX cannot be expressed by an integer number of MTB units, the
SPD must be encoded using both the MTB and FTB. The Fine Offsets are encoded using
a two’s complement value which, when multiplied by the FTB yields a positive or
negative correction factor. Typically, for safety and for legacy compatibility, the MTB
portion is rounded UP and the FTB correction is a negative value. The general algorithm
for programming SPD values is the following:

Temp_val = tXX / MTB // Calculate as real number

Remainder = Temp_val modulo 1 // Determine if integer # MTBs
Fine_Correction = 1 - Remainder // If needed, what correction
if (Remainder == 0) then // Integer # MTBs?
tXX(MTB) = Temp_val // Convert to integer
tXX(FTB) = 0 // No correction needed
else // Needs correction
tXX(MTB) = ceiling (Temp_val) // Round up for safety in legacy systems
tXX(FTB) = Fine_Correction / FTB // Correction is negative offset
endif

To recalculate the value of tXX from the SPD values, a general formula BIOSes may use
is:

tXX = tXX(MTB) * MTB + tXX(FTB) * FTB

12 Intel Confidential CDI/IBL 541356

Address Map

Table 2-1. tCKAVGmin SPD Calculations Using MTB and FTB

tCKAVGmin Value XMP Byte 396 or Byte 443 XMP Byte 431 or Byte 478
Speed Bin
Decimal Decimal (Hexadecimal) Decimal (Hexadecimal)

DDR4-1866 1.071 ns 9 (0x09) -54 (0xCA)

= (9 * 0.125) + (-54 * 0.001)

Note: Examples assume MTB of 0.125 ns and FTB of 0.001 ns (or 1 picosecond).

Table 2-2. Timing Parameters using both MTB and FTB

Parameter MTB Byte(s) FTB Byte

tCKAVGmin Profile 1 - 396 / Profile 2 - 443 Profile 1 - 431 / Profile 2 - 478

tAAmin Profile 1 - 401 / Profile 2 - 448 Profile 1 - 430 / Profile 2 - 477

tRCDmin Profile 1 - 402 / Profile 2 - 449 Profile 1 - 429 / Profile 2 - 476

tRPmin Profile 1 - 403 / Profile 2 - 450 Profile 1 - 428 / Profile 2 - 475

tRCmin Profile 1 - 404 & 406 / Profile 2 - 451 & 453 Profile 1 - 427 / Profile 2 - 474

tRRD_Smin Profile 1 - 415 / Profile 2 - 462 Profile 1 - 426 / Profile 2 - 473

tRRD_Lmin Profile 1 - 416 / Profile 2 - 463 Profile 1 - 425 / Profile 2 - 472

Table 2-3. Two’s Complement Encoding Fine Timebase Offset

Coding FTB Timebase
Value (Dec) Value (Hex)
Bit 7 Bits 6-0 1 ps

0 1111111 +127 7F +127 ps

0 1111110 +126 7E +126 ps

... ... ... ... ...

0 0000001 +1 01 +1 ps

0 0000000 0 00 0

1 1111111 -1 FF -1 ps

1 1111110 -2 FE -2 ps

... ... ... ... ...

1 0000000 -128 80 -128 ps

2.2.5.2 Rounding Algorithms

Software algorithms for calculation of timing parameters are subject to rounding errors
from many sources. For example, a system may use a memory clock with a nominal
frequency of 933.33... MHz, or a clock period of 1.0714... ns. Similarly, a system with a
memory clock frequency of 1066.66... MHz yields mathematically a clock period of
0.9375... ns. In most cases, it is impossible to express all digits after the decimal point
exactly, and rounding must be done because the SPD establishes a minimum
granularity for timing parameters of 1 ps.

Rules for rounding must be defined to allow optimization of memory module

performance without violating device parameters. These algorithms rely on results that
are within guardbands on device testing and specification to avoid losing performance
due to rounding errors.

CDI/IBL 541356 Intel Confidential 13

 Address Map

These rules are:

1. Clock periods such as tCKAVGmin are rounded to the nearest picosecond of
accuracy. For example, 0.9375... ns is rounded to 938 ps and 1.0714... ns is
rounded to 1071 ps.
2. Parameters programmed in systems in numbers of clocks (nCK) but expressed in
the SPD in units of time (ns or ps) are divided by the clock period, a guardband
factor of 0.01 clocks is subtracted, then the result is rounded up to the nearest
integer number of clocks.

Temp
Value @ tCKAVGmin Guardband Rounding Result
DDR4 Result
Parameter
Bin
ps ps nCK nCK nCK

1600 tRRD_Lmin 7500 1250 6.000 5.990 6

1600 tRRD_Lmin 7500 1071 7.002 6.992 7

2133 tRRD_Lmin 6400 1250 5.120 5.110 6

1866 tRRD_Lmin 5300 1071 4.948 4.938 5

2.2.6 Bytes 390,391,392: RFU

These bytes are left reserved for future use.

2.3 Details of Each Byte 393 to 486

Throughout this document, you will find that in order to save space, the descriptions of
the bytes were not replicated when they were the same. This will be done by listing
both or all byte numbers near the title of each byte. For example:

Byte 396 or 443: Minimum SDRAM Cycle Time (tCKAVGmin)

This title indicates that both byte 396 and byte 443 are used for tCKAVGmin values and
should be programmed the same way. Byte 396 is for the first profile, while byte 443 is
for the 2nd profile.

Note: All bytes not programmed or RSVD MUST be programmed at 0 (zero). This is a
standard SPD programming protocol.

14 Intel Confidential CDI/IBL 541356

Address Map

2.3.1 Byte 393 or 440: Module VDD Voltage Level

This byte describes the Modules VDD Voltage Level for Profiles 1 and 2. The Byte will
allow voltages above and below the typical standard voltage for Performance Tuning
and Low Power Performance Modes. This byte does not use MTB.

Bit 7 Shows the Integer of the Voltage

Voltage
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0.0V 0 See Subfield B

1.0V 1

Bits 6-0 Show the Decimal Fraction of the Voltage

Voltage
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0.00V See 0 0 0 0 0 0 0
Subfield
0.01V A 0 0 0 0 0 0 1

0.02V 0 0 0 0 0 1 0

0.03V 0 0 0 0 0 1 1

0.04V 0 0 0 0 1 0 0

0.05V 0 0 0 0 1 0 1

...

0.95V 1 0 1 1 1 1 1

0.96V 1 1 0 0 0 0 0

0.97V 1 1 0 0 0 0 1

0.98V 1 1 0 0 0 1 0

0.99V 1 1 0 0 0 1 1

Undefined All other combinations

Example 2-1.Example Module VDD Voltage Level

Subfield A Subfield B Hex Value
Use
Binary Value Binary Value programmed

1 0001010 8Ah Low Voltage DDR4 @ 1.1V VDD

1 0101000 A8h Overvoltage DDR4 @ 1.4V VDD

Note: Non-used/RSVD bytes are always programmed by default at zero.

2.3.2 Bytes 394/395 or 441/442: RFU

These Bytes are reserved for future voltage controls (if needed).

CDI/IBL 541356 Intel Confidential 15

 Address Map

2.3.3 Byte 396 or 443: Minimum SDRAM Cycle Time (tCKAVGmin)

This byte defines the minimum cycle time for the SDRAM module, in medium timebase
(MTB) units. This number applies to all applicable components on the module. This byte
applies to SDRAM and support components as well as the overall capability of the
DIMM. This value is based off but may exceed the DDR4 SDRAM data sheet.

Bit 7-0

Minimum SDRAM Cycle Time (tCKAVGmin)

MTB Units

Values defined from 1 to 255

If tCKAVGmin cannot be divided evenly by the MTB, this byte must be rounded up to the
next larger integer and the Fine Offset for tCKAVGmin (SPD byte 431 or 478) used for
correction to get the actual value.

Example 2-2.Example tCKAVG

tCKAVGmin tCKAVGmin
tCKAVGmin MTB FTB
Offset Result Use
(MTB units) (ns) (ns)
(FTB units)1 (ns)

10 0x0A 0.125 0 0 0.001 1.25 DDR4-1600 (800 Mhz Clock)

9 0x09 0.125 -54 0xCA 0.001 1.071 DDR4-1866 (933 Mhz Clock)

8 0x08 0.125 -62 0xC2 0.001 0.938 DDR4-2133 (1067 Mhz Clock)

7 0x07 0.125 -42 0xD6 0.001 0.833 DDR4-2400 (1200 Mhz Clock)

6 0x06 0.125 0 0 0.001 0.750 DDR4-2666 (1333 Mhz Clock)

5 0x05 0.125 0 0 0.001 0.625 DDR4-3200 (1600 Mhz Clock)

2.3.4 Byte 397 or 444: CAS Latencies Supported, First Byte

Byte 398 or 445: CAS Latencies Supported, Second Byte
Byte 399 or 446: CAS Latencies Supported, Third Byte
Byte 400 or 447: CAS Latencies Supported, Fourth Byte
These bytes define which CAS Latency (CL) values are supported. The range is from CL
= 7 through CL = 24 with one bit per possible CAS Latency. A 1 in a bit position means
that CL is supported. A 0 in that bit position means it is not supported. These values
come from the DDR4 SDRAM data sheet JESD79-4. This value is based off but may
exceed the DDR4 SDRAM data sheet.

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Byte 397/444: CAS Latencies Supported, First Byte

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CL = 14 CL = 13 CL = 12 CL = 11 CL = 10 CL = 9 CL = 8 CL = 7

0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1

Byte 398/445: CAS Latencies Supported, Second Byte

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CL=22 CL = 21 CL = 20 CL = 19 CL = 18 CL = 17 CL = 16 CL = 15

0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1

Byte 399/446: CAS Latencies Supported, Third Byte

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved Reserved Reserved Reserved Reserved Reserved CL = 24 CL = 23

0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 1 0 or 1 0 or 1

Byte 400/447: CAS Latencies Supported, Fourth Byte

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1

Note: For each bit position, 0 means this CAS Latency is not supported, 1 means this CAS Latency is
supported.

Example 2-3.Example CAS Latencies Supported

.

CAS
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
Latencies

CL Mask 0 0 0 0 0 1 0 0 1 0 1 1 0 1 0 0

CAS
tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 24 23
Latencies

CL Mask 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Byte 397 or 444 = 0xB4 (1011 0100)- first byte

Byte 398 or 445 = 0x05 (0000 0101)- second byte

Byte 399 or 446 = 0x00 (0000 0000)- third byte

Byte 400 or 447 = 0x00 (0000 0000)- fourth byte

Results: Actual CAS Latencies supported = 9, 11, 12, 14, 15, 17

2.3.5 Byte 401 or 448: Minimum CAS Latency Time (tAAmin)

This byte defines the minimum CAS Latency in medium timebase (MTB) units. Software
can use this information, along with the CAS Latencies supported (found in bytes 397-
400 or 444-447) to determine the optimal cycle time for a particular module. This value
is based off but may exceed the DDR4 SDRAM data sheet.

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Bit 7-0

Minimum SDRAM CAS Latency Time (tAAmin)

MTB Units

Values defined from 1 to 255

If tAAmin cannot be divided evenly by the MTB, this byte must be rounded up to the
next larger integer and the Fine Offset for tAAmin used for correction to get the actual
value.

Example 2-4.Example tAAmin

tAAmin
tAAmin MTB tAAmin Offset FTB
Result Use
(MTB units) (ns) (FTB units)1 (ns)
(ns)

106 0x6A 0.125 -120 0x89 0.001 13.13 DDR4-2133N (1066 Mhz Clock)

113 0x71 0.125 -65 0xC0 0.001 14.06 DDR4-2133P (1066 Mhz Clock)

108 0x6c 0.125 0 0 0.001 13.50 DDR4-2133P (1066 Mhz Clock) downbin

120 0x78 0.125 0 0 0.001 15.00 DDR4-2133R (1066 Mhz Clock)

100 0x64 0.125 0 0 0.001 12.50 DDR4-2400P (1200 Mhz Clock)

107 0x6B 0.125 -55 0xCA 0.001 13.32 DDR4-2400R (1200 Mhz Clock)

2.3.6 Byte 402 or 449: Minimum RAS# to CAS# Delay Time

(tRCDmin)
This byte defines the minimum SDRAM RAS# to CAS# Delay in medium timebase
(MTB) units. This value is based off but may exceed the DDR4 SDRAM data sheet.

Bit 7-0

Minimum RAS# to CAS# Delay (tRCD)

MTB Units

Values defined from 1 to 255

If tRCDmin cannot be divided evenly by the MTB, this byte must be rounded up to the
next larger integer and the Fine Offset for tRCDmin used for correction to get the actual
value.

Example 2-5.Example tRCD

tRCDmin
tRCDmin MTB tRCDminOffset FTB
Result Use
(MTB units) (ns) (FTB units)1 (ns)
(ns)

106 0x6A 0.125 -120 0x89 0.001 13.13 DDR4-2133N (1066 Mhz Clock)

113 0x71 0.125 -65 0xC0 0.001 14.06 DDR4-2133P (1066 Mhz Clock)

108 0x6c 0.125 0 0 0.001 13.50 DDR4-2133P (1066 Mhz Clock) downbin

120 0x78 0.125 0 0 0.001 15.00 DDR4-2133R (1066 Mhz Clock)

100 0x64 0.125 0 0 0.001 12.50 DDR4-2400P (1200 Mhz Clock)

107 0x6B 0.125 -55 0xCA 0.001 13.32 DDR4-2400R (1200 Mhz Clock)

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2.3.7 Byte 403 or 450: Minimum Row Precharge Delay Time

(tRPmin)
This byte defines the minimum SDRAM Row Precharge Delay Time in medium timebase
(MTB) units. This value is based off but may exceed the DDR4 SDRAM data sheet.

Bit 7-0

Minimum Row Precharge Time (tRP)

MTB Units

Values defined from 1 to 255

If tRPmin cannot be divided evenly by the MTB, this byte must be rounded up to the
next larger integer and the Fine Offset for tRPmin used for correction to get the actual
value.

Example 2-6.Example tRP

tRPmin
tRPmin MTB tRPmin Offset FTB
Result Use
(MTB units) (ns) (FTB units)1 (ns)
(ns)

106 0x6A 0.125 -120 0x89 0.001 13.13 DDR4-2133N (1066 Mhz Clock)

113 0x71 0.125 -65 0xC0 0.001 14.06 DDR4-2133P (1066 Mhz Clock)

108 0x6c 0.125 0 0 0.001 13.50 DDR4-2133P (1066 Mhz Clock) downbin

120 0x78 0.125 0 0 0.001 15.00 DDR4-2133R (1066 Mhz Clock)

100 0x64 0.125 0 0 0.001 12.50 DDR4-2400P (1200 Mhz Clock)

107 0x6B 0.125 -55 0xCA 0.001 13.32 DDR4-2400R (1200 Mhz Clock)

2.3.8 Byte 404 or 451: Upper Nibbles for tRAS and tRC
This byte defines the most significant nibbles for the values of tRAS (byte 405/452) and
tRC (byte 406/453). This value is based off but may exceed the DDR4 SDRAM data
sheet.

Bit 7-4 Bit 3-0

tRC Most Significant Nibble tRAS Most Significant Nibble

See Byte 406 description See Byte 405 description

2.3.9 Byte 405 or 452: Minimum Active to Precharge Delay Time

(tRASmin), Least Significant Byte
The lower nibble of byte 404/451 and the contents of byte 405/452 combined create a
12-bit value which defines the minimum SDRAM Active to Precharge Delay Time in
medium timebase (MTB) units. The most significant bit is Bit 3 of byte 404/451, and
the least significant bit is bit 0 of byte 405/452. This value is based off but may exceed
the DDR4 SDRAM data sheet.

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Byte 404/451 Bit 3-0

Byte 405/452 Bit 7-0

Minimum Active to Precharge Time (tRAS)

MTB Units

Values defined from 1 to 4095

Example 2-7.Example tRAS

tRASmin Timebase tRASmin Result
Use
(MTB units) (ns) (ns)

280 0x118 0.125 35 DDR4-1600 (800 Mhz Clock)

272 0x110 0.125 34 DDR4-1866 (933 Mhz Clock)

264 0x108 0.125 33 DDR4-2133 (1066 Mhz Clock)

256 0x100 0.125 32 DDR4-2400 (1200 Mhz Clock)

2.3.10 Byte 406 or 453: Minimum Active to Active/Refresh Delay

Time (tRCmin), Least Significant Byte
The upper nibble of byte 404/451 and the contents of Byte 406/453 combined create a
12-bit value which defines the minimum SDRAM Active to Active/Refresh Delay Time in
medium timebase (MTB) units. The most significant bit is bit 7 of byte 404/451, and
the least significant bit is bit 0 of byte 406/453. This value is based off but may exceed
the DDR4 SDRAM data sheet.

Byte 404/451 Bit 7-4

Byte 406/453 Bit 7-0

Minimum Active to Active/Refresh Time (tRC)

MTB Units

Values defined from 1 to 4095

If tRCmin cannot be divided evenly by the MTB, this byte must be rounded up to the
next larger integer and the Fine Offset for tRCmin used for correction to get the actual
value.

Example 2-8.Example tRC

tRCmin
tRCmin MTB tRCmin Offset FTB
Result Use
(MTB units) (ns) (FTB units)1 (ns)
(ns)

370 0x172 0.125 -120 0x89 0.001 46.13 DDR4-2133N (1066 Mhz Clock)

377 0x179 0.125 -65 0xC0 0.001 47.06 DDR4-2133P (1066 Mhz Clock)

372 0x174 0.125 0 0 0.001 46.50 DDR4-2133P (1066 Mhz Clock) downbin

384 0x180 0.125 0 0 0.001 48.00 DDR4-2133R (1066 Mhz Clock)

356 0x164 0.125 0 0 0.001 44.50 DDR4-2400P (1200 Mhz Clock)

363 0x16B 0.125 -55 0xCA 0.001 45.32 DDR4-2400R (1200 Mhz Clock)

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2.3.11 Byte 407 or 454: Minimum Refresh Recovery Delay Time

(tRFC1min), LSB
Byte 408 or 455: Minimum Refresh Recovery Delay Time
(tRFC1min), MSB
The contents of bytes 407/454 and the contents of bytes 408/455 are combined to
create a 16-bit value which defines the minimum SDRAM Refresh Recovery Time Delay
in medium timebase (MTB) units. The most significant bit is bit 7 of byte 408/455. The
least significant bit is bit 0 of byte 407/454. This value is based off but may exceed the
DDR4 SDRAM data sheet.

Byte 407/454 Bit 7-0

Byte 408/455 Bit 7-0

Minimum Refresh Recover Time Delay (tRFC1min)

MTB Units

Values defined from 1 to 65535

Example 2-9.Example tRFC1

tRFC1min Timebase tRFC1min Result
Use
(MTB units) (ns) (ns)

1280 0x0500 0.125 160 2 Gb DDR4 SDRAM

2080 0x0820 0.125 260 4 Gb DDR4 SDRAM

2800 0x0AF0 0.125 350 8 Gb DDR4 SDRAM

TBD TBD 0.125 TBD 16 Gb DDR4 SDRAM

2.3.12 Byte 409 or 456: Minimum Refresh Recovery Delay Time

(tRFC2min), LSB
Byte 410 or 457: Minimum Refresh Recovery Delay Time
(tRFC2min), MSB
The contents of bytes 409/456 and the contents of bytes 410/457 are combined to
create a 16-bit value which defines the minimum SDRAM Refresh Recovery Time Delay
in medium timebase (MTB) units. The most significant bit is bit 7 of byte 410/457. The
least significant bit is bit 0 of byte 409/456. This value is based off but may exceed the
DDR4 SDRAM data sheet.

Byte 409/456 Bit 7-0

Byte 410/457 Bit 7-0

Minimum Refresh Recover Time Delay (tRFC2min)

MTB Units

Values defined from 1 to 65535

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Example 2-10.Example tRFC2

tRFC2min Timebase tRFC2min Result
Use
(MTB units) (ns) (ns)

880 0x0370 0.125 110 2 Gb DDR4 SDRAM

1280 0x0500 0.125 160 4 Gb DDR4 SDRAM

2080 0x0820 0.125 260 8 Gb DDR4 SDRAM

TBD TBD 0.125 TBD 16 Gb DDR4 SDRAM

2.3.13 Byte 411 or 458: Minimum Refresh Recovery Delay Time

(tRFC4min), LSB
Byte 412 or 459: Minimum Refresh Recovery Delay Time
(tRFC4min), MSB
The contents of bytes 411/458 and the contents of bytes 412/459 are combined to
create a 16-bit value which defines the minimum SDRAM Refresh Recovery Time Delay
in medium timebase (MTB) units. The most significant bit is bit 7 of byte 412/459. The
least significant bit is bit 0 of byte 411/458. This value is based off but may exceed the
DDR4 SDRAM data sheet.

Byte 411/458 Bit 7-0

Byte 412/459 Bit 7-0

Minimum Refresh Recover Time Delay (tRFC4min)

MTB Units

Values defined from 1 to 65535

Example 2-11.Example tRFC4

tRFC4min Timebase tRFC4min Result
Use
(MTB units) (ns) (ns)

720 0x02D0 0.125 90 2 Gb DDR4 SDRAM

880 0x0370 0.125 110 4 Gb DDR4 SDRAM

1280 0x0500 0.125 160 8 Gb DDR4 SDRAM

TBD TBD 0.125 TBD 16 Gb DDR4 SDRAM

2.3.14 Byte 413 or 460: Upper Nibble for tFAW

This byte defines the most significant nibble for the value of tFAW (SPD byte 414/461).
This value comes from the DDR4 SDRAM data sheet.

Bit 7-4 Bit 3-0

Reserved tFAW Most Significant Nibble

Reserved See byte 414 description

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2.3.15 Byte 414 or 461: Minimum Four Activate Window Delay

Time (tFAWmin), Least Significant Byte
The lower nibble of byte 413/460 and the contents of byte 414/461 combined create a
12-bit value which defines the minimum SDRAM Four Activate Window Delay Time in
medium timebase (MTB) units. This value comes from the DDR4 SDRAM data sheet.
The value of this number may be dependent on the SDRAM page size. Please refer to
the DDR4 SDRAM data sheet section on addressing to determine the page size for
these devices.

Byte 413/460 Bit 3-0

Byte 414/461 Bit 7-0

Minimum Four Activate Window Delay Time (tFAWmin)

MTB Units

Values defined from 1 to 4095

Example 2-12.Example tFAW

tFAWmin Timebase tFAWmin Result
Use
(MTB units) (ns) (ns)

240 0x0F0 0.125 30 Example: DDR4-2133, 2KB page size

184 0x0B8 0.125 21 Example: DDR4-2133, 1KB page size

136 0x088 0.125 15 Example: DDR4-2133, 1/2 KB page size

240 0x0F0 0.125 30 Example: DDR4-2400, 2KB page size

2.3.16 Byte 415 or 462: Minimum Activate to Activate Delay Time

(tRRD_Smin), Different Bank Group
This byte defines the minimum SDRAM Activate to Activate Delay Time to different
bank groups inmedium timebase (MTB) units. This value comes from the DDR4 SDRAM
data sheet. Memoy controller designers must also note that at some frequencies, a
minimum number of clocks may be required resulting in a larger tRRD_Smin value than
indicated in the SPD. For example, tRRD_Smin for DDR4-1600 must be 4 clocks.

Bit 7-0

Minimum Row Active to Row Active Delay (tRRD_S)

MTB Units

Values defined from 1 to 255

If tRRD_Smin cannot be divided evenly by the MTB, this byte must be rounded
up to the next larger integer and the Fine Offset for tRRD_Smin used for correction to
get the actual value.

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Example 2-13.Example tRRD_S

tRRD_Smin tRRD_Smin
tRRD_Smin MTB FTB
Offset Result Use
(MTB units) (ns) (ns)
(FTB units)1 (ns)

34 0x22 0.125 -50 0xCF 0.001 4.20 DDR4-1866 (933 Mhz Clock), 1/2 KB
page size

43 0x2B 0.125 -75 0xB5 0.001 5.30 DDR4-2133 (1066 Mhz Clock), 2 KB page
size

30 0x1E 0.125 -50 0xCF 0.001 3.70 DDR4-2133 (1066 Mhz Clock), 1 KB page
size

Note: See SPD Byte 426/473 for Fine Offset information

2.3.17 Byte 416 or 463: Minimum Activate to Activate Delay Time

(tRRD_Lmin), same bank group
This byte defines the minimum SDRAM Activate to Activate Delay Time to same bank
groups in medium timebase (MTB) units. This value comes from the DDR4 SDRAM data
sheet. Memory controller designers must also note that at some frequencies, a
minimum number of clocks may be required resulting in a larger tRRD_Lmin value than
indicated in the SPD. For example, tRRD_Lmin for DDR4-1600 must be 4 clocks.

Bit 7-0

Minimum Row Active to Row Active Delay (tRRD_L)

MTB Units

Values defined from 1 to 255

If tRRD_Lmin cannot be divided evenly by the MTB, this byte must be rounded up to the
next larger integer and the Fine Offset for tRRD_Lmin used for correction to get the
actual value.

Example 2-14.Example tRRD_L

tRRD_Lmin tRRD_Lmin
tRRD_Lmin MTB FTB
Offset Result Use
(MTB units) (ns) (ns)
(FTB units)1 (ns)

43 0x2B 0.125 -75 0xB5 0.001 5.30 DDR4-1866 (933 Mhz Clock), 1/2 KB
page size

52 0x34 0.125 -100 0x9D 0.001 6.40 DDR4-2133 (1066 Mhz Clock), 2 KB
page size

43 0x2B 0.125 -75 0xB5 0.001 5.30 DDR4-2133 (1066 Mhz Clock), 1 KB
page size

Note: See SPD Byte 425/472 for Fine Offset information

2.3.18 Bytes 417-422 or 464-469: RSVD in Profiles

These bytes are reserved for future use in the profiles. They are not to be programmed.
Must be coded as 0x00.

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2.3.19 Bytes 423 & 424 or 470 & 471: RSVD for Supplier Custom
Mods
These bytes are reserved for Supplier Custom Modification. Each supplier may utilize
these bytes in whichever manner they deem fit. Intel will leave these bytes as reserved
for suppliers.

2.3.20 Byte 425 or 472: Fine Offset for Minimum Row Active to
Row Active Delay Time (tRRD_Lmin), same bank group
This byte is modifies the calculation of XMP tRRD_Lmin byte 416 or 463 (MTB units) with
a fine correction using FTB units. The value of tRRD_Lmin comes from the SDRAM data
sheet. This value is a two’s complement multiplier for FTB units, ranging from +127 to
-128. See primary byte for more details. For two’s complement encoding, see Section
2.2.5.1, “Relating the MTB and FTB” for more details.

2.3.21 Byte 426 or 473: Fine Offset for Minimum Row Active to
Row Active Delay Time (tRRD_Smin), different bank group
This byte is modifies the calculation of XMP tRRD_Smin Byte 415 or 462 (MTB units) with
a fine correction using FTB units. The value of tRRD_Smin comes from the SDRAM data
sheet. This value is a two’s complement multiplier for FTB units, ranging from +127 to
-128. See primary byte for more details. For two’s complement encoding, see Section
2.2.5.1, “Relating the MTB and FTB” for more details.

2.3.22 Byte 427 or 474: Fine Offset for Minimum Active to Active/
Refresh Delay Time (tRCmin)
This byte is modifies the calculation of XMP tRCmin byte 404 & 405, or 451 & 453 (MTB
units) with a fine correction using FTB units. The value of tRCmin comes from the
SDRAM data sheet. This value is a two’s complement multiplier for FTB units, ranging
from +127 to -128. See primary byte for more details. For two’s complement encoding,
see Section 2.2.5.1, “Relating the MTB and FTB” for more details.

2.3.23 Byte 428 or 475: Fine Offset for Minimum Row Precharge
Delay Time (tRPmin)
This byte is modifies the calculation of XMP tRPmin byte 403 or 450 (MTB units) with a
fine correction using FTB units. The value of tRPmin comes from the SDRAM data sheet.
This value is a two’s complement multiplier for FTB units, ranging from +127 to -128.
See primary byte for more details. For two’s complement encoding, see Section
2.2.5.1, “Relating the MTB and FTB” for more details.

2.3.24 Byte 429 or 476: Fine Offset for Minimum RAS# to CAS#
Delay Time (tRCDmin)
This byte is modifies the calculation of XMP tRCDmin byte 402 or 449 (MTB units) with a
fine correction using FTB units. The value of tRCDmin comes from the SDRAM data
sheet. This value is a two’s complement multiplier for FTB units, ranging from +127 to
-128. See primary byte for more details. For two’s complement encoding, see Section
2.2.5.1, “Relating the MTB and FTB” for more details.

§§

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