SLM21364

600V Three-Phase Bridge Driver with OCP, Enable and Fault

PRODUCT SUMMARY GENEERAL DESCRIPTION
 VOFFSET 600 V max. The SLM21364 is a high voltage, high speed power
 IO+/- 200 mA / 350 mA MOSFET and IGBT drivers with three independent
high- and low-side referenced output channels for
 VOUT 10V - 20 V three-phase applications. Proprietary HVIC and latch
 ton/off (typ.) 350 ns / 400 ns immune CMOS technologies enable ruggedized
 Deadtime (typ.) 290 ns monolithic construction. The logic inputs are
compatible with standard CMOS or LSTTL output,
down to 3.3 V logic. A current trip function which
FEATURES terminates all six outputs can be derived from an
external current sense resistor. An enable function is
 Floating channel designed for bootstrap
available to terminate all six outputs simultaneously.
operation
An open-drain FAULT signal is provided to indicate
 Fully operational to +600 V that an overcurrent or undervoltage shutdown has
 Tolerant to negative transient voltage, dV/dt occurred. Overcurrent fault conditions are cleared
immune automatically after a delay programmed externally
 Gate drive supply range from 10 V to 20 V via an RC network connected to the RCIN input. The
output drivers feature a high pulse current buffer
 Undervoltage lockout for all channels stage designed for minimum driver cross conduction.
 Low/high side output in phase with inputs Propagation delays are matched to simplify use in
 3.3 V, 5 V logic compatible high frequency applications. The floating channel
 Lower di/dt gate drive for better noise immunity can be used to drive an N-channel power MOSFET
or IGBT in the high-side configuration which
 Cross-conduction prevention logic operates up to 600 V.
 Matched propagation delay for both channels
 Externally programmable delay for automatic
fault clear
 SOP28W package

TYPICAL APPLICATION CIRCUIT

Up to 600V

VCC VCC VB1,2,3

HIN1,2,3 HIN1,2,3 HO1,2,3

LIN1,2,3 LIN1,2,3 VS1,2,3

FAULT FAULT
SLM21364
EN EN

RCIN

ITRIP LO1,2,3

VSS COM

GND

Refer to Pin Configuration for correct configuration. This diagram shows electrical connections only.

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Rev 1.0, Jul 2022
 SLM21364
Table of Contents
Product Summary .......................................................................................................................................................1
Features ......................................................................................................................................................................1
Geneeral Description ..................................................................................................................................................1
Typical Application Circuit ..........................................................................................................................................1
PIN Configuration .......................................................................................................................................................3
PIN Description ...........................................................................................................................................................3
Ordering Information ...................................................................................................................................................4
Functional Block Diagram ...........................................................................................................................................5
Absolute Maximum Ratings ........................................................................................................................................6
Reconmmended Operation Conditions ......................................................................................................................6
Dynamic Electrical Characteristics .............................................................................................................................7
Static Electrical Characteristics ..................................................................................................................................7
Functional Table .........................................................................................................................................................9
Typical Performance Characteristics ........................................................................................................................12
Package Case Outlines ............................................................................................................................................15
Revision History ........................................................................................................................................................16

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Rev 1.0, Jul 2022
 SLM21364
PIN CONFIGURATION
Package Pin Configuration (Top View)

1 VCC VB1 28
2 HIN1 HO1 27
3 HIN2 VS1 26
4 HIN3 25
5 LIN1 VB2 24
6 LIN2 HO2 23
7 LIN3 VS2 22
SOP28W
8 FAULT 21
9 ITRIP VB3 20
10 EN HO3 19
11 RCIN VS3 18
12 VSS 17
13 COM LO1 16
14 LO3 LO2 15

PIN DESCRIPTION
No. Pin Description
1 VCC Low-side and logic supply voltage.
2, 3, 4 HIN1,2,3 Logic input for high-side gate driver output (HO1,2,3), in phase.

5, 6, 7 LIN1,2,3 Logic input for low-side gate driver output (LO1,2,3), in phase.

8 Indicates over-current (ITRIP) or low-side undervoltage lockout has occurred.

FAULT
Negative logic, open-drain output.
Analog input for overcurrent shutdown. When active, ITRIP shuts down outputs and
activates FAULT and RCIN low. When ITRIP becomes inactive, FAULT stays active
9 ITRIP
low for an externally set time, TFLTCLR, then automatically becomes inactive (open-
drain high impedance).

10 EN Logic input to enable I/O functionality. I/O logic functions when EN is high. No effect
on FAULT and not latched.
External RC network input used to define FAULT CLEAR delay, T FLTCLR,
11 RCIN approximately equal to R*C. When RCIN>8 V, the FAULT pin goes back into open-
drain high-impedance.
12 VSS Logic ground.
13 COM Low-side gate drivers return.
14, 15, 16 LO1, 2, 3 Low-side gate driver outputs.
18, 22, 26 VS1, 2, 3 High-side floating supply return.
19, 23, 27 HO1, 2, 3 High-side gate driver outputs.
20, 24, 28 VB1, 2, 3 High-side floating supply.

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 SLM21364
ORDERING INFORMATION
Industrial Range: -40°C to +125°C

Order Part No. Package QTY

SLM21364CF-DG SOP28W, Pb-Free 1000/Reel

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Rev 1.0, Jul 2022
 SLM21364
FUNCTIONAL BLOCK DIAGRAM

SLM21364
Input
VB1
HIN1 Noise
Filter Set Latch
VSS/COM HV
Dead time & Level Level Rset Driver HO1
VBS
Shoot-Through Shift Shift
UVLO
Prevention
VS1
Input
LIN1 Noise
Filter

Input
VB2
HIN2 Noise
Filter Set Latch
VSS/COM HV
Dead time & Level Level Rset Driver HO2
VBS
Shoot-Through Shift Shift
UVLO
Prevention
VS2
Input
LIN2 Noise
Filter

Input
VB3
HIN3 Noise
Filter Set Latch
VSS/COM HV
Dead time & Level Level Rset Driver HO3
VBS
Shoot-Through Shift Shift
UVLO
Prevention
VS3
Input
LIN3 Noise
Filter

VSS

Input
EN Noise
Filter
VCC
UVLO VCC

ITRIP Input VSS/COM

Noise Level Delay Driver LO1
VIT Filter S Shift
Set
Dominant Q
R Latch

VSS/COM
RCIN Level Delay Driver LO2
Shift

VSS/COM
Level Delay Driver LO3
FAULT Shift

COM

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 SLM21364
ABSOLUTE MAXIMUM RATINGS
Symbol Definition Min. Max. Units
VB High-side floating absolute voltage -0.3 625
VS High-side floating supply offset voltage VB1,2,3 - 25 VB1,2,3 + 0.3
VHO High-side floating output voltage VS1,2,3 - 0.3 VB1,2,3 + 0.3
VCC Low-side and logic supply voltage -0.3 25
VSS Logic ground -5 +5
V
Lower of (VSS +
VIN Logic input voltage (LIN, HIN, ITRIP, EN) VSS - 0.3
15) or (VCC + 0.3)
VLO1,2,3 Low-side output voltage -0.3 VCC + 0.3
VRCIN RCIN input voltage VSS - 0.3 VCC + 0.3
Lower of (VSS +
VFLT FAULT onput voltage VSS - 0.3
25) or (VCC + 0.3)
dVS/dt Allowable offset supply voltage transient --- 50 V/ns
PD Package power dissipation @ TA ≤ +25°C --- 1.6 W
θJA Thermal resistance, junction to ambient --- 75 °C/W
TJ Junction temperature --- 150
TS Storage temperature -55 150 °C
TL Lead temperature (soldering, 10 seconds) --- 300
Note: Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute
voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.

RECONMMENDED OPERATION CONDITIONS

The input/output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended
conditions. The VS offset rating is tested with all supplies biased at a 15 V differential.

Symbol Definition Min. Max. Units

VB1,2,3 High-side floating supply voltage VS1,2,3 + 10 VS1,2,3 + 20
VS1,2,3 High-side floating supply offset voltage 600
VHO1,2,3 High-side floating output voltage VS1,2,3 VB1,2,3
VLO1,2,3 Low-side output voltage 0 VCC
VCC Low-side and logic fixed supply voltage 10 20
V
VSS Logic ground -5 5

VFLT FAULT output voltage VSS VCC

VRCIN RCIN input voltage VSS VCC

VITRIP ITRIP input voltage VSS VSS + 20V
VIN Logic input voltage LIN1,2,3, HIN1,2,3, EN VSS VSS + 20V
TA Ambient temperature - 40 125 °C
Note: Logic operational for VS of (COM – 5 V) to (COM + 600V). Logic state held for VS of (COM-5V) to (COM - VBS).

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 SLM21364
DYNAMIC ELECTRICAL CHARACTERISTICS
VBIAS (VCC, VBS) = 15 V, VS1,2,3 = VSS = COM, CL = 1000 pF and TA = 25°C unless otherwise specified.

Symbol Parameter Condition Min. Typ. Max. Unit

ton Turn-on propagation delay VS = 0 V 200 350 500

toff Turn-off propagation delay VS = 600 V 250 400 550

tr Turn-on rise time --- 100 150

tf Turn-off fall time --- 40 70

Enable low to output shutdown

tEN VIN, VEN = 0 V or 5 V 300 400 500
propagation delay
ns
ITRIP to output shutdown propagation
tITRIP VITRIP = 5 V 450 650 850
delay
VIN = 0 V or 5 V
tbl ITRIP blanking time 100 150 ---
VITRIP = 5 V
VIN = 0 V or 5 V
tFLT ITRIP to FAULT propagation delay 400 600 800
VITRIP = 5 V

tFILIN Input filter time (HIN, LIN) VIN = 0 V & 5 V 200 300 ---

FAULT clear time RCIN: R = 2 MΩ, C = VIN = 0 V or 5 V

tFLTCLR 1.3 1.65 2 ms
1nF VITRIP = 0 V
Deadtime, LS turn-off to HS turn-on &
DT VIN = 0 V & 5 V 200 290 450
HS turn-on to LS turn-off
External dead time >
MT Matching delay, HS & LS turn-on/off --- --- 100 ns
400 ns
Output pulse width matching (PW IN -
PM --- 50 75
PW OUT) (Figure 2)

STATIC ELECTRICAL CHARACTERISTICS

VBIAS (VCC, VBS1,2,3) = 15 V and TA = 25°C unless otherwise specified. The VIN, VTH, and IIN parameters are
referenced to VSS and are applicable to all 6 channels (LIN1,2,3 and HIN1,2,3). The VO and IO parameters are
referenced to COM and VS1,2,3 and are applicable to the respective output leads: HO1,2,3 and LO1,2,3.

Symbol Parameter Condition Min. Typ. Max. Unit

Logic “1” input voltage (LIN1,2,3 and

VIH 2.5 --- ---
HIN1,2,3)
VCC = 10 V to 20V
Logic “0” input voltage (LIN1,2,3 and
VIL --- --- 0.8
HIN1,2,3)
V
VEN, TH+ Enable positive going threshold --- --- 2.5

VEN, TH- Enable negative going threshold 0.8 --- ---

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Rev 1.0, Jul 2022
 SLM21364
Symbol Parameter Condition Min. Typ. Max. Unit

VIT, TH+ ITRIP positive going threshold 0.39 0.47 0.55

VIT, HYS ITRIP input hysteresis --- 0.1 --- V

VRCIN, TH+ RCIN positive going threshold --- 8 ---

VRCIN, HYS RCIN input hysteresis --- 1 ---

VOH High level output voltage, VBIAS - VO --- 0.7 1.0

IO = 20 mA
VOL Low level output voltage, VO --- 0.2 0.4

VCCUV+ VCC and VBS supply undervoltage

8.0 8.9 9.8
VBSUV+ positive going threshold

VCCUV- VCC and VBS supply undervoltage

7.4 8.2 9.0
VBSUV- negative going threshold
V
VCCUVH VCC and VBS supply undervoltage lockout
0.3 0.7 ---
VBSUVH hysteresis

Input clamp voltage (HIN, LIN, ITRIP

VIN_CLAMP IIN = 100 µA --- 6.6 ---
and EN)

ILK Offset supply leakage current VB1,2,3 = VS1,2,3 = 600 V --- --- 50
µA
IQBS Quiescent VBS supply current --- 65 75
VIN = 0 V
IQCC Quiescent VCC supply current --- 0.6 1 mA

HIN1,2,3= 5 V
IIN+ Logic “1” input bias current --- 80 100
LIN1,2,3= 5 V
HIN1,2,3= 0 V,
IIN- Logic “0” input bias current --- 0 1
LIN1,2,3= 0 V

IITRIP+ “High” ITRIP input bias current VITRIP = 5 V --- 36 50

IITRIP- “Low” ITRIP input bias current VITRIP = 0 V --- 0 1 µA

IEN+ “High” ENABLE input bias current VENABLE = 5 V --- 40 55

IEN- “Low” ENABLE input bias current VENABLE = 0 V --- 0 1

IRCIN RCIN input bias current VRCIN = 0 V or 15 V --- 0 1

VO = 0 V, VIN = VIH
IO+ Output high short circuit pulsed current 120 200 --- mA
PW ≤ 10 µs

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Rev 1.0, Jul 2022
 SLM21364
Symbol Parameter Condition Min. Typ. Max. Unit

VO = 15 V, VIN = VIL
IO- Output low short circuit pulsed current 250 350 ---
PW ≤ 10 µs

Ron_RCIN RCIN low on resistance --- 25 50

Ω
Ron_FAULT FAULT low on resistance --- 120 200

FUNCTIONAL TABLE
VCC VBS ITRIP ENABLE FAULT LO1,2,3 HO1,2,3
< UVCC X X X 0 (note 2) 0 0
15 V < UVBS 0V 5V High imp LIN1,2,3 0
15 V 15 V 0V 5V High imp LIN1,2,3(note 1) HIN1,2,3(note 1)
15 V 15 V > VITRIP 5V 0 (note 3) 0 0
15 V 15 V 0V 0V High imp 0 0
Note:
1. A shoot-through prevention logic prevents LO1,2,3 and HO1,2,3 for each channel from turning on simultaneously.
2. UVCC is not latched, when VCC > UVCC, FAULT returns to high impedance.
3. When ITRIP < VITRIP, FAULT returns to high-impedance after RCIN pin becomes greater than 8 V (@ VCC = 15 V).

HIN1.2.3

LIN1.2.3
EN

ITRIP
FAULT

RCIN

HO1.2.3

LO1.2.3
Figure 1. Input/output Timing Diagram

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Rev 1.0, Jul 2022
 SLM21364
LIN1.2.3 50% 50%
50%
HIN1.2.3 EN
PWIN

tEN

ton tr toff tf
PWOUT
90%
90% 90% HO1.2.3
HO1.2.3
LO1.2.3
LO1.2.3 10% 10%

Figure 2. Switching Time Waveforms Figure 3. Output Enable Timing Waveform

HIN1.2.3

50% 50%
LIN1.2.3

50% 50%
LO1.2.3

DT DT

HO1.2.3
50% 50%

Figure 4. Internal Deadtime Timing Waveforms

VRCIN,TH+

RCIN

50% 50%
ITRIP

FAULT 50% 50%

tFLT

tFLTCLR
90%
Any
Output tITRIP

Figure 5. ITRIP/RCIN Timing Waveforms

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Rev 1.0, Jul 2022
 SLM21364
tFILIN tFILIN

on off on off on off

HIN/LIN

high
HO/LO
low

Figure 6. Input Filter Function

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Rev 1.0, Jul 2022
 SLM21364
TYPICAL PERFORMANCE CHARACTERISTICS
500 500

Low Side Low Side

Turn On Progation Delay (ns)

High Side

Turn Off Progation Delay (ns)

High Side
450 450

400 400

350 350

300 300

250 250
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120

Temperature (oC) Temperature (oC)

Figure 7. Turn On Time vs. Temperature Figure 8. Turn Off Time vs. Temperature
250 80

Low Side Low Side

High Side High Side
200
Turn On Rise Time (ns)

Turn Off Fall Time (ns)

60

150

40

100

20
50

0 0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
o o
Temperature ( C) Temperature ( C)

Figure 9. Turn On Rise Time vs. Temperature Figure 10. Turn Off Fall Time vs. Temperature
600 400

500 350
Enable Delay (ns)

Dead Time (ns)

400 300

300 250

200 200
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
o
Temperature ( C) Temperature (oC)

Figure 11. Enable Delay vs. Temperature Figure 12. Dead Time vs. Temperature

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Rev 1.0, Jul 2022
 SLM21364
2.4 1.0

Fall
2.2 Rise
0.8

ITRIP Threshold (V)

Fault Clear Time (ms)

2.0

0.6
1.8

1.6
0.4

1.4

0.2
1.2

1.0 0.0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120

Temperature (oC) Temperature (oC)

Figure 13. Fault Clear Time vs. Temperature Figure 14. ITRIP Threshold vs. Temperature
1200 400

350
1000
High Level Output (mV)

Low Level Output (mV)

300

250
800

200

600
150

100
400
50

200 0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120

Temperature (oC) Temperature (oC)

Figure 15. High Level Output Voltage Figure 16. Low Level Output Voltage
vs. Temperature vs. Temperature
11 11

Fall Fall
Rise Rise
10 10
VCC UVLO (V)

VBS UVLO (V)

9 9

8 8

7 7

6 6
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
o
Temperature ( C) Temperature (oC)

Figure 17. VCC Under Voltage Threshold vs. Figure 18. VBS Under Voltage Threshold vs.
Temperature Temperature

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Rev 1.0, Jul 2022
 SLM21364
1200 120
VCC Quiescent Current (uA)

VBS Quiescent Current (uA)

100
1000

80
800

60

600
40

400
20

200 0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120

Temperature (oC) Temperature (oC)

Figure 19. Vcc Quiescent Current vs. Temperature Figure 20. VBS Quiescent Current vs. Temperature
50 250
RCIN Low on Resistance (Ω)

Fault Low on Resistance (Ω)

40 200

30 150

20 100

10 50

0 0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120

Temperature (oC) Temperature (oC)

Figure 21. RCIN Low On Resistance vs. Temperature Figure 22. FAULT Low On Resistance vs. Temperature

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Rev 1.0, Jul 2022
 SLM21364
PACKAGE CASE OUTLINES

Figure 23. SOP28W Outline Dimensions

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Rev 1.0, Jul 2022
 SLM21364
REVISION HISTORY
Note: page numbers for previous revisions may differ from page numbers in current version
Page or Item Subjects (major changes since previous revision)
Rev 0.1 datasheet, 2020-1-14
Whole document Preliminary datasheet released
Rev 1.0 datasheet, 2022-7-20
Whole document Rev 1.0 datasheet released

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Rev 1.0, Jul 2022