QUESTION BANK

UNIT I-

NUMBER SYSTEM

Short Questions

1. Find the 2’s complement of (101101)2.

2. State De Morgan’s law.

3. Prove that ABC+ABC’+AB’C+A’BC = AB+AC+BC
4. Convert (4021.2)5 to decimal number.
5. Convert the given binary number (11011101)2 to gray code.
Long Questions

1. a)Convert (i)(11101001110)2=()8
ANS:- (11101001110)2= (1646) 8

(ii)(A0CB.EE) 16= ( )10

(iii)(235)10 = ( )16
b) Show how to connect NAND gates to get an AND gate and OR gate?
2. a) write the decimal number 5 in the weighted code form of
i) 8 4 2 1
ii) 5 2 1 1
iii) 8 4 -2 -1
b) Express the function Y=A+B’C in canonical SOP and canonical POS form
3. Evaluate the following Boolean expression using Boolean Algebra and draw the
logic diagram.
(a)F(X, Y, Z) = (X +Y )(X’(Z’+Y’))’+X’Y’+X’Z’.
(b) F(A,B,C,D)=AB’C+B+BD’+ABD’+AC’
4. (a) Explain about Boolean postulates and laws.
(b) construct the hamming code for BCD 0110.using even parity.

5 a) subtract the following numbers using 10’s complement

i) 24-09 ii) 69-32 iii)347-265

b) Explain various logic gates with truth table and logic diagram
6 a) perform following binary numbers using 2’s complement

i) 39-22 ii)-47+22

7. Simplify the following Boolean expression

a) ((AB’+ABC)’+A(B+AB’))’

b) AB+A’C+AB’C(AB+C)

UNIT-II

COMBINATIONAL CIRCUITS

Short Questions

1. What is Half adder? obtain the sum and carry expression.

2. Draw the 2-bit comparator circuit using logic gates.
3. Distinguish between encoder and decoder.
4. What is a multiplexer? Give the applications.
5. Design half subtractor and implement using NAND gates.

Long Questions

1 (a)simplify the Boolean expression using K-map method f(A,B,C,D) = ∑m

(4,5,7,12,14,15)+∑d(3,8,10).

(b) Analyze the design of 8 x1multiplexer using only 2x1 multiplexer

2 a) Reduce the following function using Quine Mc cluskey tabular method.

f(A,B,C,D)=∑m(0,2,3,4,5,8,10,11,13,14,15).

b) define magnitude comparator? draw the block diagram and truth table of 4 bit
magnitude comparator.

3 a)simplify the Boolean expression using K-map method f(A,B,C,D) =

∑m(0,1,2,4,7,8,`12,14,15,16,17,18,20,24,28,30,31)

(b) design 3 to 8 decoder using 2 to 4 decoder circuits.

4 a) what is full subtractor? draw the block diagram and truth table of full subtractor and
obtain design equation using two half subtractors..

b) Implement following function using 8:1 MUX f(A,B,C,D)= ∑m(0,1,3,4,8,9,15).

5. a) what is full adder? draw the block diagram and truth table of full adder and obtain
design equation using two half Adders.

(b) What is a priority encoder? Design a 4 x2 priority encoder with appropriate gates.

6a) simplify the Boolean expression using K-map method f(A,B,C,D) =

πM(0,1,4,5,6,8,9,12,13,14).

b) Simplify the expression using k- map method F=A’+AB+ABD’+AB’D’+C.

7. Reduce the following function using Quine Mc cluskey tabular method.

f(A,B,C,D)=∑m(6,7,8,9)+d(10,11,12,13,14,15)

UNIT III

SEQUENTIAL CITRCUITS

Short Questions
1. Write a short notes on sequential circuit.
ANS:- A sequential circuit refers to a special type of circuit. It consists of a series
of various inputs and outputs. Here, the outputs depend on a combination of both the
present inputs as well as the previous outputs. This previous output gets treated in the
form of the present state. The sequential circuits can be event driven, clock driven and
pulse driven.

2. Difference between latch and flip flop.

ANS:- Difference between Flip-flop and Latch :
SNO.Flip-flop Latch

*Flip-flop is a bistable device i.e., it has |*Latch is also a bistable device whose
two stable states that are represented as 0 | states are also represented as 0 and 1.
and 1.

*It is a edge triggered device. |*It is a level triggered device.

*Gates like NOR, NOT, AND, NAND
are building blocks of flip flops. |*These are also made up of gates.
*They are classified into asynchronous
or synchronous flipflops. |*There is no such classification in latches.
.
*a, Flip-flop always have a clock signal |*Latches doesn’t have a clock signal
 *Flip-flop can be build from Latches |*Latches can be build from gates
*ex:D Flip-flop, JK Flip-flop |*ex:SR Latch, D Latch

3. Draw the excitation table of JK flip flop.

ANS:-

4. Draw the logic diagram of SR flip flop using NAND gates.

ANS:-

5. Define race around condition?

ANS:- Race Around Condition in JK Flip-flop

 For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then output Q will toggle as long
as CLK remains high which makes the output unstable or uncertain.
 This is called a race around condition in J-K flip-flop.
 We can overcome this problem by making the clock =1 for very less duration.
 The circuit used to overcome race around conditions is called the Master Slave JK flip flop.

Long Questions
1 a) Distinguish between combinational circuits and sequential circuits.
Ans:- Difference between Combinational and Sequential Circuit
The following table highlights how a combinational circuit is different from a sequential circuit −

Key Combinational Circuit Sequential Circuit

A Combinational Circuit is a type of circuit A Sequential circuit is a type of circuit

in which the output is independent of time where output not only relies on the
Definition
and only relies on the input present at that current input but also depends on the
particular instant. previous output.

Since output does not depend on the time The output relies on its previous
instant, no feedback is required for its feedback so output of previous input is
Feedback
next output generation. being transferred as feedback used
with input for next output generation.

As the input of current instant is only Sequential circuits are comparatively

required in case of Combinational circuit, slower and has low performance as
Performance
it is faster and better in performance as compared to that of Combinational
compared to that of Sequential circuit. circuit.

No implementation of feedback makes the The implementation of feedback makes

Complexity combinational circuit less complex as sequential circuit more complex as
compared to sequential circuit. compared to combinational circuit.

The elementary building blocks of a The building blocks of a sequential

Elementary
combinational circuit are its logic gates. circuit are the logic gates along with flip
Blocks
flops.

Combinational circuits are mainly used for Sequential circuits are mainly used for
Operation
arithmetic as well as Boolean operations. storing data.

b) With a neat diagram explain operation of SR flip flop and derive its truth table, excitation table
and characteristic equation.

ANS:-

SR Flip Flop | Diagram | Truth Table | Excitation Table

SR Flip Flop-
SR flip flop is the simplest type of flip flops.
 It stands for Set Reset flip flop.
It is a clocked flip flop.

Construction of SR Flip Flop-

There are following two methods for constructing a SR flip flop-

1. By using NOR latch

2. By using NAND latch

1. Construction of SR Flip Flop By Using NOR Latch-

This method of constructing SR Flip Flop uses-

 NOR latch
 Two AND gates

Logic Circuit-

The logic circuit for SR Flip Flop constructed using NOR latch is as shown below-
 2. Construction of SR Flip Flop By Using NAND Latch-

This method of constructing SR Flip Flop uses-

 NAND latch
 Two NAND gates

Logic Circuit-

The logic circuit for SR Flip Flop constructed using NAND latch is as shown below-

Logic Symbol-

The logic symbol for SR Flip Flop is as shown below-

Truth Table-

The truth table for SR Flip Flop is as shown below-

INPUTS OUTPUTS REMARKS

Qn Qn+1
S R States and Conditions
(Present State) (Next State)

0 0 X Qn Hold State condition S = R = 0

0 1 X 0 Reset state condition S = 0 , R = 1

1 0 X 1 Set state condition S = 1 , R = 0

1 1 X Indeterminate Indeterminate state condition S = R = 1

Truth Table

Characteristic Equation-

Draw a k map using the above truth table-

From here-
Qn+1 = ( SR + SR’ ) ( Qn + Q’n ) + Qn ( S’R’ + SR’ )

Qn+1 = S + QnR’

Excitation Table-

The excitation table of any flip flop is drawn using its truth table.

What is excitation table?

For a given combination of present state Qn and next state Qn+1, excitation table tell the inputs required.

Qn Qn+1 S R

0 0 0 X

0 1 1 0

1 0 0 1

1 1 X 0

Excitation Table

To gain better understanding about SR Flip Flop,

2 a) Draw the clocked Master-Slave J-K flip-flop configuration and explain how it removes race-
around condition in J-K flip-flops.

ANS:-

Master-Slave JK Flip Flop

Race Around Condition In JK Flip-flop – For J-K flip-flop, if J=K=1, and if clk=1 for a long period of
time, then Q output will toggle as long as CLK is high, which makes the output of the flip-flop unstable
or uncertain. This problem is called race around condition in J-K flip-flop. This problem (Race Around
Condition) can be avoided by ensuring that the clock input is at logic “1” only for a very short time. This
introduced the concept of Master Slave JK flip flop.
Master Slave JK flip flop –
The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected together in a series
configuration. Out of these, one acts as the “master” and the other as a “slave”. The output from the
master flip flop is connected to the two inputs of the slave flip flop whose output is fed back to inputs of
the master flip flop.
In addition to these two flip-flops, the circuit also includes an inverter. The inverter is connected to clock
pulse in such a way that the inverted clock pulse is given to the slave flip-flop. In other words if CP=0 for
a master flip-flop, then CP=1 for a slave flip-flop and if CP=1 for master flip flop then it becomes 0 for
slave flip flop.

Working of a master slave flip flop –

1. When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of the system.
The slave flip-flop is isolated until the CP goes to 0. When the CP goes back to 0, information is
passed from the master flip-flop to the slave and output is obtained.
2. Firstly the master flip flop is positive level triggered and the slave flip flop is negative level triggered,
so the master responds before the slave.
3. If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and the clock forces
the slave to reset, thus the slave copies the master.
4. If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the Negative
transition of the clock sets the slave, copying the master.
5. If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles on the
negative transition of the clock.
6. If J=0 and K=0, the flip flop is disabled and Q remains unchanged.
Timing Diagram of a Master flip flop –
1. When the Clock pulse is high the output of master is high and remains high till the clock is low
because the state is stored.
2. Now the output of master becomes low when the clock pulse becomes high again and remains low
until the clock becomes high again.
3. Thus toggling takes place for a clock cycle.
4. When the clock pulse is high, the master is operational but not the slave thus the output of the slave
remains low till the clock remains high.
5. When the clock is low, the slave becomes operational and remains high until the clock again becomes
low.
6. Toggling takes place during the whole process since the output is changing once in a cycle.
This makes the Master-Slave J-K flip flop a Synchronous device as it only passes data with the timing of
the clock signal.

b) what is SR latch? explain gated SR latch?

Ans:-

An SR latch made from two NAND gates.

An SR latch (Set/Reset) is an asynchronous device: it works independently of control signals and

relies only on the state of the S and R inputs. In the image, we can see that an SR latch can be
created with two NOR gates that have a cross-feedback loop. SR latches can also be made from
NAND gates, but the inputs are swapped and negated. In this case, it is sometimes called
an SR latch.
When a high input is applied to the Set line of an SR latch, the Q output goes high (and Q low). The
feedback mechanism, however, means that the Q output will remain high, even when the S input
goes low again. This is how the latch serves as a memory device. Conversely, a high input on
the Reset line will drive the Q output low (and Q high), effectively resetting the latch's "memory".
When both inputs are low, the latch "latches" – it remains in its previously set or reset state.
When both inputs are high at once, however, there is a problem: it is being told to simultaneously
produce a high Q and a low Q. This produces a "race condition" within the circuit - whichever flip flop
succeeds in changing first will feedback to the other and assert itself. Ideally, both gates are identical
and this is "metastable", and the device will be in an undefined state for an indefinite period. In real
life, due to manufacturing methods, one gate will always win, but it's impossible to tell which it will be
for a particular device from an assembly line. The state of S = R = 1 is therefore "illegal" and should
never be entered.

S R Q Q

0 0 Latched

0 1 0 1

1 0 1 0

1 1 Metastable

When the device is powered up, a similar condition occurs, because both outputs, Q and Q, are low.
Again, the device will quickly exit the metastable state due to differences between the two gates, but
it's impossible to predict which of Q and Q will end up high. To avoid spurious actions, you should
always set SR flip-flops to a known initial state before using them - you must not assume that they
will initialise to a low state.

Gated SR latch[edit | edit source]

A Gated SR latch made from two NOR and two AND gates.
In some situations it may be desirable to dictate when the latch can and cannot latch. The gated SR
latch is a simple extension of the SR latch which provides an Enable line which must be driven high
before data can be latched. Even though a control line is now required, the SR latch is not
synchronous, because the inputs can change the output if the enable line is held high at length.
(Note: If a clock is supplied to the control line, the gated SR latch becomes known as an SR flip
flop because the output changes only when edge-triggered by the clock.[1])
When the Enable input is low, then the outputs from the AND gates must also be low, thus
the Q and Q outputs remain latched to the previous data. Only when the enable input is high can the
state of the latch change, as shown in the truth table. When the enable line is asserted, a gated SR
latch is identical in operation to an SR latch.
The Enable line is sometimes a clock signal, but is usually a read or write strobe.

Enable S R Q Q

0 0 0 Latched

0 0 1 Latched

0 1 0 Latched

0 1 1 Latched

1 0 0 Latched

1 0 1 0 1

1 1 0 1 0

1 1 1 Metastable

3 a)obtain characteristic table and truth table and excitation table of T &D flip flop.
Ans:-

:- D Flipflop
Truth Table

D Q(t+1)

0 0

1 1

Characteristic Equation

Q(t+1) = D(t)

Excitation Table

Q(t) Q(t+1) D

0 0 0

0 1 1

1 0 0

1 1 1

T Flipflop

Truth Table

T Q(t+1)

0 Q(t)

1 Q'(t)

Characteristic Equation

Q(t+1) = T'(t)Q(t) + T(t)Q'(t) = T(t) ⊕ Q(t)

Excitation Table

Q(t) Q(t+1) T

0 0 0

0 1 1

1 0 1

1 1 0
 b) convert a SR flip flop into JK flip flop using standard procedure

asn:-

Flip flop Conversion – SR flip-flop to JK flip-flop

Step 1: Write the truth table of the required flip-flop

Here the required flip-flop is JK flip-flop

Hence you need to write the truth table of JK flip-flop which is

J K QN QN+1

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

Step 2: Write the excitation table of the given flip-flop

In this case the given flip-flop is SR flip-flop

Therefore you need to write the excitation table of SR flip-flop which is

QN QN+1 S R
 0 0 0 X

0 1 1 0

1 0 0 1

1 1 X 0

Step 3: Write the conversion table

The conversion table, which is a combination of truth table and excitation table, to implement
a JK flip-flop from SR flip-flop is as follows

J K QN QN+1 S R

0 0 0 0 0 X

0 0 1 1 X 0

0 1 0 0 0 X

0 1 1 0 0 1

1 0 0 1 1 0

1 0 1 1 X 0

1 1 0 1 1 0

1 1 1 0 0 1

Step 4: Find the Boolean expressions for the inputs of the given flip-flop.

In this case the given flip-flop is SR.

Therefore, write the Boolean expressions for S and R from the conversion table using K-Maps.

K-Map for S:
Expression for S would be

S = JQN/

K-Map for R:

Expression for R would be

R = KQN

Step 5: Draw the circuit for implementing JK flip-flop using SR flip-flop

 4 a) with a neat diagram explain operation of JK flip flop and derive its truth
table ,excitation table and characteristic equation.

ANS:-
JK Flip Flop- JK flip flop is a refined & improved version of SR Flip Flop that has been
introduced to solve the problem of indeterminate state that occurs in SR flip flop when both the
inputs are 1.
In JK flip flop,
 Input J behaves like input S of SR flip flop which was meant to set the flip flop.
 Input K behaves like input R of SR flip flop which was meant to reset the flip flop.

Construction of JK Flip Flop-

1. Construction of JK Flip Flop By Using SR Flip Flop Constructed From NOR Latch-

This method of constructing JK Flip Flop uses-

 SR Flip Flop constructed from NOR latch
 Two other connections

Logic Circuit-

The logic circuit for JK Flip Flop constructed using SR Flip Flop constructed from NOR latch is
as shown below-
Logic Symbol-

The logic symbol for JK Flip Flop is as shown below-

Truth Table-

The truth table for JK Flip Flop is as shown below-

Truth Table

The above truth table may be reduced as-

INPUTS OUTPUTS REMARKS

Qn Qn+1
J K States and Conditions
(Present State) (Next State)

0 0 X Qn Hold State condition J = K = 0

0 1 X 0 Reset state condition J = 0 , K = 1

1 0 X 1 Set state condition J = 1 , K = 0

 1 1 X Q’n Toggle state condition J = K = 1

Characteristic Equation-

Draw a k map using the above truth table-

From here-
Qn+1 = Q’n (JK + JK’) + Qn (J’K’ + JK’)

Qn+1 = Q’nJ + QnK’

Excitation Table-

The excitation table of any flip flop is drawn using its truth table.

What is excitation table?

For a given combination of present state Qn and next state Qn+1, excitation table tell the inputs required.

Qn Qn+1 S R
 0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

Excitation Table

b) Convert a D flip flop into T flip flop using Standard Procedure

ANS:- Flip-flop Conversion – D flip-flop to T flip-flop

Step 1: Write the truth table of the required flip-flop

Here the required flip-flop is T flip-flop

Hence you need to write the truth table of T flip-flop which is

T QN QN+1

0 0 0

0 1 1

1 0 1

1 1 0

Step 2: Write the excitation table of the given flip-flop

In this case the given flip-flop is D flip-flop

Therefore you need to write the excitation table of D flip-flop which is

 QN QN+1 D

0 0 0

0 1 1

1 0 0

1 1 1

Step 3: Write the conversion table

The conversion table, which is a combination of truth table and excitation table, to implement a T flip-
flop from D flip-flop is as follows

T QN QN+1 D

0 0 0 0

0 1 1 1

1 0 1 1

1 1 0 0

Step 4: Find the Boolean expressions for the inputs of the given flip-flop

In this case the given flip-flop is D.

Therefore, write the Boolean expression for D from the conversion table using K-Map.

K-Map for D:

Expression for D would be

D = T/QN + TQN/

Step 5: Draw the circuit for implementing T flip-flop from D flip-flop

For this, connect the input D of the given flip-flop (D flip-flop) to the circuit made for the expression of
D obtained from the K Map. Therefore, the circuit would be:

5a) obtain excitation table of

i) SR Flip flop

ii)JK flip flop

iii)D flip flop

iv)T flip flop

ANS:-

The excitation table for each flip-flop.

SR flip flop
The excitation table of the SR flip-flop can be constructed from the information available in the
truth table. In the diagram shown below, the first table shows the truth table, from which the
excitation table is derived.

From the truth table, you can observe that when the present state is Qn = 0, the next state
becomes Qn+1 = 0 for two input values S = 0, R = 0 and S = 0, R = 1. (It is shown in the first and
third rows with yellow color)
From this we can say that, for the state transition from Qn = 0 to Qn+1 = 0, the excitation inputs
required are S = 0 and R = 0 or 1. It is filled in the first row(Yellow color) of the excitation table.
Since R has two values(0 and 1), it is denoted as a don’t care condition(x).

Similarly, when you observe the truth table, to obtain the next state output Qn+1 = 1 from the
present state input Qn = 0, the required SR inputs are S = 1 and R = 0(shown in the 5th row as
pink color).

Thus for state transition from 0 to 1, the excitation inputs require are S = 1 and R = 0. It is filled
in the second row of the excitation table.

The state transition from the present state Qn = 1 to the next state Qn+1 = 0 happens only when
the inputs are S = 0 and R = 1(observed from the 4th row in light green color). It is filled in the
third row of the excitation table.

In the same way, the state transition from Qn = 1 to Qn+1 = 1 happens at S = 0, R = 0 and S = 1, R
= 0(shown in second and sixth row of the truth table).

It is filled in the fourth row of the excitation table as Qn = 1, Qn+1 = 1 and S = x, R = 0. Here x
denotes the don’t care condition, as it has two values(0 and 1).

***JK flip flop

For the JK flip flop, the excitation table is derived in the same way. From the truth table, for the
present state and next state values Qn = 0 and Qn+1 = 0(indicated in the first and third row with
yellow color), the inputs are J = 0 and K = 0 or 1.

Since K input has two values, it is considered as a don’t care condition(x).

Thus the state transition from Qn = 0 to Qn+1 = 0 takes place when J = 0, K = x. It is filled in the
first row of the excitation table.
The state transition from present state Qn = 0 to the next state Qn+1 = 1 occur, when the inputs
are either J = 1, K = 0 or J = 1, K = 1(indicated in the fifth and seventh row with pink color).
Thus the excitation table is filled with datas Qn = 0, Qn+1 = 1, J = 1 and K = x.

Similarly, for the transition of the state from 1 to 0, the inputs are J = 0, K = 1 or J = 1, K =
1(indicated in the fourth and eighth row with ash color). So for this transition, the required
inputs are J = x and K =1, as the value of J can be either 0 or 1.

For the state transition from Qn = 1 to Qn+1 = 1, the J input can be 0 or 1 but the K input remains
at o(indicated in the second and sixth row with violet color). For this transition to occur, the
excitation inputs are J = x and K = 0.

D flip flop
The excitation table of the D flip-flop is derived from its truth table. The excitation table is
constructed in the same way as explained for the SR flip-flop.

Here, when you observe from the truth table shown below, the next state output is equal to the D
input. So it is very simple to construct the excitation table.

For the state transition from Qn = 0 to Qn+1 = 0, the required excitation input is D = 0, regardless
of Qn value. For transition of states from Qn = 0 to Qn+1 = 1, the input required to excite is D = 1.
The state transit from Qn = 1 to Qn+1 = 0 for the input D = 0. For the input D = 1, the state
transition takes place from Qn = 1 to Qn+1 = 1.

All the above-mentioned state transitions for D flip flop from the present state(Qn) to the next
state(Qn+1) for the corresponding excitation inputs are filled in the table to get the excitation
table.

T flip flop
The following figure shows the truth table of the T flip flop, from which the excitation table is
derived.

From the truth table, we can observe that, when the T input is 0, there is no change in the state.
So for the state transition from the present state to the next state, i.e., from Qn = 0 to Qn+1 = 0
and from Qn = 1 to Qn+1 = 1, the excitation input require is T = 0. It is filled in the first and the
fourth row in the excitation table.

Similarly, from the truth table, we can also observe, when T = 1, the state of the flip flop toggles
or is complimented. Thus, for the transition of the state from either 0 to 1 or from 1 to 0, the
excitation input is T = 1. It is filled in the second and third rows of the excitation table.

b) Convert a JK flip flop into D flip flop using standard procedure

ANS:-

Conversion of J-K Flip-Flop into D Flip-Flop

1. JK Flip-Flop:
JK Flip-Flip is basically a gated SR flip-flop which has an additional input that is clock input. It prevents
the invalid output that may be obtained when both the inputs are 1.
2. D Flip-Flop:
D Flip-Flop is a modified SR flip-flop which has an additional inverter. It prevents the inputs from
becoming the same value.
Conversion of J-K Flip-Flop into D Flip-Flop:
 Step-1:
We construct the characteristic table of D flip-flop and excitation table of JK flip-flop.
 Step-2:
Using the K-map we find the boolean expression of J and K in terms of D.

J = D
K = D'
 Step-3:
We construct the circuit diagram of the conversion of JK flip-flop into D flip-flop.

UNIT-IV
BASIC STRUCTURE OF COMPUTER SYSTEM

Short Questions
1.What is the role of MAR and MDR?

ANS:- memory address register (MAR) - holds the address of the current instruction that is to be
fetched from memory, or the address in memory to which data is to be transferred. memory data
register (MDR) - holds the contents found at the address held in the MAR, or data which is to be
transferred to primary memory.

2.What is DMA and why it is used?

ANS:- Direct memory access (DMA) is the process of transferring data without the
involvement of the processor itself. It is often used for transferring data to/from input/output
devices. A separate DMA controller is required to handle the transfer. The controller notifies the
DSP processor that it is ready for a transfer.

DMA is useful when dealing with data generated at a very high and very low speed.
In high speed data transfers, like from USB and Ethernet, data is typically handled by
complex peripherals that can deal with the blocks of data being transferred

3.Write short notes on indirect addressing mode?

ANS:- Indirect Addressing Mode: This is the mode of addressing where the instruction
contains the address of the location where the target address is stored. So in this way, it is
Indirectly storing the address of the target location in another memory location. So it is called
Indirect Addressing mode.

1.

4.What is the function of accumulator and program counter?

ANS:- Accumulator is a pressure vessel for storing hydraulic pressure in it utilizing

compressible and decompressible nature of nitrogen gas. So, it can be said that the
accumulator has a similar function to the rechargeable electrical battery. In electricity, electrical
energy is stored to the battery.

The program counter (PC) is a register that manages the memory address of the instruction
to be executed next. The address specified by the PC will be + n (+1 for a 1-word instruction
and +2 for a 2-word instruction) each time one instruction is executed.

5.List out various phases of instruction cycle?

ANS:- It is composed of three main stages: the fetch stage, the decode stage, and the
execute stage.
Long Questions

1. (a) with a neat sketch Explain the various functional blocks of computer and the way they
communicate with each other.

Functional Components of a Computer

Computer: A computer is a combination of hardware and software resources which integrate together
and provides various functionalities to the user. Hardware are the physical components of a computer like
the processor, memory devices, monitor, keyboard etc. while software is the set of programs or
instructions that are required by the hardware resources to function properly.
There are a few basic components that aids the working-cycle of a computer i.e. the Input- Process-
Output Cycle and these are called as the functional components of a computer. It needs certain input,
processes that input and produces the desired output. The input unit takes the input, the central processing
unit does the processing of data and the output unit produces the output. The memory unit holds the data
and instructions during the processing.
Digital Computer: A digital computer can be defined as a programmable machine which reads the
binary data passed as instructions, processes this binary data, and displays a calculated digital output.
Therefore, Digital computers are those that work on the digital data.

Details of Functional Components of a Digital Computer

 Input Unit :The input unit consists of input devices that are attached to the computer. These devices
take input and convert it into binary language that the computer understands. Some of the common
input devices are keyboard, mouse, joystick, scanner etc.
 Central Processing Unit (CPU) : Once the information is entered into the computer by the input
device, the processor processes it. The CPU is called the brain of the computer because it is the
control center of the computer. It first fetches instructions from memory and then interprets them so
as to know what is to be done. If required, data is fetched from memory or input device. Thereafter
CPU executes or performs the required computation and then either stores the output or displays on
the output device. The CPU has three main components which are responsible for different functions
– Arithmetic Logic Unit (ALU), Control Unit (CU) and Memory registers
 Arithmetic and Logic Unit (ALU) : The ALU, as its name suggests performs mathematical
calculations and takes logical decisions. Arithmetic calculations include addition, subtraction,
multiplication and division. Logical decisions involve comparison of two data items to see which one
is larger or smaller or equal.
 Control Unit : The Control unit coordinates and controls the data flow in and out of CPU and also
controls all the operations of ALU, memory registers and also input/output units. It is also responsible
for carrying out all the instructions stored in the program. It decodes the fetched instruction, interprets
it and sends control signals to input/output devices until the required operation is done properly by
ALU and memory.
 Memory Registers : A register is a temporary unit of memory in the CPU. These are used to store
the data which is directly used by the processor. Registers can be of different sizes(16 bit, 32 bit, 64
bit and so on) and each register inside the CPU has a specific function like storing data, storing an
instruction, storing address of a location in memory etc. The user registers can be used by an
assembly language programmer for storing operands, intermediate results etc. Accumulator (ACC) is
the main register in the ALU and contains one of the operands of an operation to be performed in the
ALU.
 Memory : Memory attached to the CPU is used for storage of data and instructions and is called
internal memory The internal memory is divided into many storage locations, each of which can store
data or instructions. Each memory location is of the same size and has an address. With the help of
the address, the computer can read any memory location easily without having to search the entire
memory. when a program is executed, it’s data is copied to the internal memory and is stored in the
memory till the end of the execution. The internal memory is also called the Primary memory or Main
memory. This memory is also called as RAM, i.e. Random Access Memory. The time of access of
data is independent of its location in memory, therefore this memory is also called Random Access
memory (RAM). Read this for different types of RAMs
 Output Unit : The output unit consists of output devices that are attached with the computer. It
converts the binary data coming from CPU to human understandable form. The common output
devices are monitor, printer, plotter etc.

Interconnection between Functional Components

A computer consists of input unit that takes input, a CPU that processes the input and an output unit that
produces output. All these devices communicate with each other through a common bus. A bus is a
transmission path, made of a set of conducting wires over which data or information in the form of
electric signals, is passed from one component to another in a computer. The bus can be of three types –
Address bus, Data bus and Control Bus.
Following figure shows the connection of various functional components:
The address bus carries the address location of the data or instruction. The data bus carries data from one
component to another and the control bus carries the control signals. The system bus is the common
communication path that carries signals to/from CPU, main memory and input/output devices. The
input/output devices communicate with the system bus through the controller circuit which helps in
managing various input/output devices attached to the computer.
(b)Explain Various Types Of Computer Registers.

Computer Registers

Registers are a type of computer memory used to quickly accept, store, and transfer data and
instructions that are being used immediately by the CPU. The registers used by the CPU are
often termed as Processor registers.

A processor register may hold an instruction, a storage address, or any data (such as bit
sequence or individual characters).

The computer needs processor registers for manipulating data and a register for holding a
memory address. The register holding the memory location is used to calculate the address of
the next instruction after the execution of the current instruction is completed.

Following is the list of some of the most common registers used in a basic computer:

Register Symbol Number of bits Function

Data register DR 16 Holds memory operand

Address register AR 12 Holds address for the memory

Accumulator AC 16 Processor register

Instruction register IR 16 Holds instruction code

Program counter PC 12 Holds address of the instruction

Temporary register TR 16 Holds temporary data

Input register INPR 8 Carries input character

Output register OUTR 8 Carries output character

The following image shows the register and memory configuration for a basic computer.

o The Memory unit has a capacity of 4096 words, and each word contains 16 bits.
o The Data Register (DR) contains 16 bits which hold the operand read from the memory
location.
o The Memory Address Register (MAR) contains 12 bits which hold the address for the
memory location.
o The Program Counter (PC) also contains 12 bits which hold the address of the next
instruction to be read from memory after the current instruction is executed.
 o The Accumulator (AC) register is a general purpose processing register.
o The instruction read from memory is placed in the Instruction register (IR).
o The Temporary Register (TR) is used for holding the temporary data during the
processing.
o The Input Registers (IR) holds the input characters given by the user.
o The Output Registers (OR) holds the output after processing the input data.

2.(a) define interrupt? Explain interrupt cycle with flow chart.

Interrupt Cycle:

 An instruction cycle (sometimes called fetch-and-execute cycle, fetch-decode-execute

cycle, or FDX) is the basic operation cycle of a computer. It is the process by which a
computer retrieves a program instruction from its memory, determines what actions the
instruction requires, and carries out those actions. This cycle is repeated continuously by
the central processing unit (CPU), from bootupto when the computer is shut down.

Block diagram of Interrupt Cycle

 After the execute cycle is completed, a test is made to determine if an interrupt was
enabled (e.g. so that another process can access the CPU)
 If not, instruction cycle returns to the fetch cycle
 If so, the interrupt cycle might performs the following tasks: (simplified...)
 move the current value of PC into MBR
 move the PC-save-address into MAR
 move the interrupt-routine-address into PC
 move the contents of the address in MBR into indicated memory cell
 continue the instruction cycle within the interrupt routine
 after the interrupt routine finishes, the PC-save-address is used to reset the value of PC
and program execution can continue
flowchart of interrupt cycle

(b) Illustrate block diagram of I/O configuration.

introduction of Input-Output Processor

The DMA mode of data transfer reduces CPU’s overhead in handling I/O operations. It also allows
parallelism in CPU and I/O operations. Such parallelism is necessary to avoid wastage of valuable CPU
time while handling I/O devices whose speeds are much slower as compared to CPU. The concept of
DMA operation can be extended to relieve the CPU further from getting involved with the execution of
I/O operations. This gives rises to the development of special purpose processor called Input-Output
Processor (IOP) or IO channel.
The Input Output Processor (IOP) is just like a CPU that handles the details of I/O operations. It is more
equipped with facilities than those are available in typical DMA controller. The IOP can fetch and
execute its own instructions that are specifically designed to characterize I/O transfers. In addition to the
I/O – related tasks, it can perform other processing tasks like arithmetic, logic, branching and code
translation. The main memory unit takes the pivotal role. It communicates with processor by the means of
DMA.
The block diagram –

The Input Output Processor is a specialized processor which loads and stores data into memory along
with the execution of I/O instructions. It acts as an interface between system and devices. It involves a
sequence of events to executing I/O operations and then store the results into the memory.
3. Write short notes on
i) Instruction format

ans:- Instruction includes a set of operation codes and operands that manage with the
operation codes. Instruction format supports the design of bits in an instruction. It contains
fields including opcode, operands, and addressing mode.
The instruction length is generally preserved in multiples of the character length, which is 8 bits.
When the instruction length is permanent, several bits are assigned to opcode, operands, and
addressing modes.
The function of allocating bits in the instruction can be interpreted by considering the following
elements −

 Number of addressing modes

 Number of operands
 Number of CPU registers
 Number of register sets
 Number of address lines
The figure displayed the general IA-32 (Intel Architecture- 32 bits) instruction format. IA-32 is
the instruction format that can Intel’s most outstanding microprocessors. This instruction format
includes four fields, such as opcode field, addressing mode field, displacement field, and
immediate field.
The opcode field has 1 or 2 bytes. The addressing mode field also includes 1 or 2 bytes. In the
addressing mode field, an instruction needs only one byte if it uses only one register to
generate the effective address of an operand.
The field that directly follows the addressing mode field is the displacement field. If an effective
address for a memory operand is computed using the displacement value, then it uses either
one or four bytes to encode. If an operand is an immediate value, then it is located in the
immediate field and it appears either one or four bytes.

ii) Stored program organization

ans:- Store Program Control Concept

The term Stored Program Control Concept refers to the storage of instructions in computer
memory to enable it to perform a variety of tasks in sequence or intermittently.

The idea was introduced in the late 1040s by John von Neumann who proposed that a program
be electronically stored in the binary-number format in a memory device so that instructions
could be modified by the computer as determined by intermediate computational results.

ENIAC (Electronic Numerical Integrator and Computer) was the first computing system
designed in the early 1940s. It was based on Stored Program Concept in which machine use
memory for processing data.

Stored Program Concept can be further classified in three basic ways:

1. Von-Neumann Model
2. General Purpose System
3. Parallel Processing
 iii) Strobe control

ans:- The strobe control technique of asynchronous data transfer operates a single control line
to time each transfer. The strobe can be activated by either the source or the destination unit.
The diagram shows a source-initiated transfer. The data bus gives the binary data from the
source unit to the destination unit

4. a) Explain DMA controller with neat block diagram.

ANS:-
Direct Access Media (DMA) Controller in Computer Architecture
Direct Memory Access (DMA) :
DMA Controller is a hardware device that allows I/O devices to directly access memory with less
participation of the processor. DMA controller needs the same old circuits of an interface to communicate
with the CPU and Input/Output devices.
Fig-1 below shows the block diagram of the DMA controller. The unit communicates with the CPU
through data bus and control lines. Through the use of the address bus and allowing the DMA and RS
register to select inputs, the register within the DMA is chosen by the CPU. RD and WR are two-way
inputs. When BG (bus grant) input is 0, the CPU can communicate with DMA registers. When BG (bus
grant) input is 1, the CPU has relinquished the buses and DMA can communicate directly with the
memory.
DMA controller registers :
The DMA controller has three registers as follows.
 Address register – It contains the address to specify the desired location in memory.
 Word count register – It contains the number of words to be transferred.
 Control register – It specifies the transfer mode.
Note –
All registers in the DMA appear to the CPU as I/O interface registers. Therefore, the CPU can both read
and write into the DMA registers under program control via the data bus.

Fig 1- Block Diagram

Explanation :
The CPU initializes the DMA by sending the given information through the data bus.
 The starting address of the memory block where the data is available (to read) or where data are to be
stored (to write).
 It also sends word count which is the number of words in the memory block to be read or write.
 Control to define the mode of transfer such as read or write.
 A control to begin the DMA transfer.

b) Explain handshaking technique in terms of source initiated and destination initiated

data transfer
ANS:-

Handshaking Method

The strobe method has the disadvantage that the source unit that initiates the transfer has no
way of knowing whether the destination has received the data that was placed in the bus.
Similarly, a destination unit that initiates the transfer has no way of knowing whether the source
unit has placed data on the bus.
So this problem is solved by the handshaking method. The handshaking method introduces a
second control signal line that replays the unit that initiates the transfer.

In this method, one control line is in the same direction as the data flow in the bus from the
source to the destination. The source unit uses it to inform the destination unit whether there
are valid data in the bus.

The other control line is in the other direction from the destination to the source. This is because
the destination unit uses it to inform the source whether it can accept data. And in it also, the
sequence of control depends on the unit that initiates the transfer. So it means the sequence of
control depends on whether the transfer is initiated by source and destination.

o Source initiated handshaking: In the below block diagram, you can see that two
handshaking lines are "data valid", which is generated by the source unit, and "data
accepted", generated by the destination unit.

The timing diagram shows the timing relationship of the exchange of signals between
the two units. The source initiates a transfer by placing data on the bus and enabling its
data valid signal. The destination unit then activates the data accepted signal after it
accepts the data from the bus.
The source unit then disables its valid data signal, which invalidates the data on the bus.
After this, the destination unit disables its data accepted signal, and the system goes into
its initial state. The source unit does not send the next data item until after the
destination unit shows readiness to accept new data by disabling the data accepted
signal.
 This sequence of events described in its sequence diagram, which shows the above
sequence in which the system is present at any given time.
o Destination initiated handshaking: In the below block diagram, you see that the two
handshaking lines are "data valid", generated by the source unit, and "ready for data"
generated by the destination unit.
Note that the name of signal data accepted generated by the destination unit has been
changed to ready for data to reflect its new meaning.

The destination transfer is initiated, so the source unit does not place data on the data
bus until it receives a ready data signal from the destination unit. After that, the
handshaking process is the same as that of the source initiated.
The sequence of events is shown in its sequence diagram, and the timing relationship
between signals is shown in its timing diagram. Therefore, the sequence of events in
both cases would be identical.

5.a) Explain basic operational concepts of the computer.

ANS:-

Basic Operational Concepts

o The primary function of a computer system is to execute a program, sequence of

instructions. These instructions are stored in computer memory.
o These instructions are executed to process data which are already loaded in the
computer memory through some input devices.
o After processing the data, the result is either stored in the memory for further reference,
or it is sent to the outside world through some output port.
 o To perform the execution of an instruction, in addition to the arithmetic logic unit, and
control unit, the processor contains a number of registers used for temporary storage of
data and some special function registers.
o The special function registers include program counters (PC), instruction registers (IR),
memory address registers (MAR) and memory and memory data registers (MDR).
o The Program counter is one of the most critical registers in CPU.
o The Program counter monitors the execution of instructions. It keeps track on which
instruction is being executed and what the next instruction will be.
o The instruction register IR is used to hold the instruction that is currently being executed.
o The contents of IR are available to the control unit, which generate the timing signals
that control, the various processing elements involved in executing the instruction.
o The two registers MAR and MDR are used to handle the data transfer between the main
memory and the processor.
o The MAR holds the address of the main memory to or from which data is to be
transferred.
o The MDR contains the data to be written into or read from the addressed word of the
main memory.
o Whenever the processor is asked to communicate with devices, we say that the
processor is servicing the devices. The processor can service these devices in one of the
two ways.
o One way is to use the polling routine, and the other way is to use an interrupt.
o Polling enables the processor software to check each of the input and output devices
frequently. During this check, the processor tests to see if any devices need servicing or
not.
o Interrupt method provides an external asynchronous input that informs the processor
that it should complete whatever instruction that is currently being executed and fetch a
new routine that will service the requesting device.

b) Explain common bus structure and various types of computers.

ANS:-
Common Bus System
We shall study the common bus system of a very basic computer in this article. A basic computer has 8
registers, memory unit and a control unit. The diagram of the common bus system is as shown below.
Connections:
The outputs of all the registers except the OUTR (output register) are connected to the common bus. The
output selected depends upon the binary value of variables S2, S1 and S0. The lines from common bus
are connected to the inputs of the registers and memory. A register receives the information from the bus
when its LD (load) input is activated while in case of memory the Write input must be enabled to receive
the information. The contents of memory are placed onto the bus when its Read input is activated.
Various Registers:
4 registers DR, AC, IR and TR have 16 bits and 2 registers AR and PC have 12 bits. The INPR and
OUTR have 8 bits each. The INPR receives character from input device and delivers it to the AC while
the OUTR receives character from AC and transfers it to the output device. 5 registers have 3 control
inputs LD (load), INR (increment) and CLR (clear). These types of registers are similar to a binary
counter.
Abbreviation Register name

OUTR Output register

TR Temporary register

IR Instruction register

INPR Input register

AC Accumulator

DR Data register

PC Program counter
 Abbreviation Register name

AR Address register

Adder and logic circuit:

The adder and logic circuit provides the 16 inputs of AC. This circuit has 3 sets of inputs. One set comes
from the outputs of AC which implements register micro operations. The other set comes from the DR
(data register) which are used to perform arithmetic and logic micro operations. The result of these
operations is sent to AC while the end around carry is stored in E as shown in diagram. The third set of
inputs is from INPR.
Note:
The content of any register can be placed on the common bus and an operation can be performed in the
adder and logic circuit during the same clock cycle.
*** Types of Computers
is a device that transforms data into meaningful information. It processes the input according to the set of
instructions provided to it by the user and gives the desired output. Computers are of various types and
they can be categorized in two ways on the basis of size and on the basis of data handling capabilities.
So, on the basis of size, there are five types of computers:
1. Supercomputer
2. Mainframe computer
3. Minicomputer
4. Workstation
5. PC (Personal Computer)
And on the basis of data handling capabilities, there are three types of computer:
1. Analogue Computer
2. Digital Computer
3. Hybrid Computer
UNIT-V

THE MEMORY SYSTEM

Short Questions
1. Explain cache hit?
ANS:- A "cache hit" occurs when a file is requested from a cache and the cache is
able to fulfill that request.
A cache hit describes the situation where your site's content is successfully
served from the cache. The tags are searched in the memory rapidly, and when the
data is found and read, it's considered as a cache hit. A cache hit is when content is
successfully served from the cache instead of the server

2. Draw the memory hierarchy.

ANS:-
 3. Define latency and bandwidth?
ANS:- Bandwidth is a measure of how much data can move (measured in X bits
per second) and latency is a measure of the delay in moving that data (measured
in milliseconds), between two nodes.

4. Draw the block diagram of associative memory?

ANS:-

5. Write short notes on auxiliary memory?

ANS:- Auxiliary memory units are among computer peripheral equipment. They trade
slower access rates for greater storage capacity and data stability. Auxiliary memory
holds programs and data for future use, and, because it is nonvolatile (like ROM), it is
used to store inactive programs and to archive data.

Long Questions
1. a) define mapping? Explain three mapping techniques of memory in detail?
ANS:- Memory Mapping and its types
Memory Mapping

The translation between the logical address space and the physical memory is known
as Memory Mapping. To translate from logical to a physical address, to aid in memory
protection also to enable better management of memory resources are objectives of memory
mapping.

During cache mapping, the block is not brought from the main memory but the main memory
block is simply copied to the cache. Cache memory generally tends to operate in some different
configurations,

1. Direct mapping
2. Fully associative mapping
3. Set associative mapping

1) Direct Mapping

In Direct mapped cache memory, each block mapped to exactly one location in cache memory.

A particular block of main memory can map the line number of cache is given by - Cache line
number = (Block Address of Main Memory) modulo (Number of lines in Cache).

Direct Mapping of Cache

The direct-mapped cache is like rows in a table with three columns' main memory address are
bits for Offset, Index, and Tag. The size of the fields depends on the capacity of memory and size
of the block in the cache.
The least significant w bits are used to identify a word within a block of main memory. Tag
corresponds to the remaining bits are used to determine the proper block of main memory. Line
off-set or block is used to select a block to be accessed out of total blocks are available
according to the capacity of the cache.

The data block or cache line that contains the actual data fetched and stored, a tag with all or
part of the address of the data that was fetched, and a flag bit that shows the presence in the
row entry of a valid bit of data.

2) Associative Mapping

In this type of mapping, any main memory block can go in any line of the cache. So we have to
use proper replacement policy to replace a block from the cache if the required block of main
memory is not present in the cache. Here, the main memory is divided into two fields: word field
identifies which word in the block is needed and the tag field identifies the block. It is
considered to be the fastest and the most flexible mapping form of cache mapping.

Associative Mapping of Cache

3) Set-associative Mapping

In this mapping technique, blocks of cache are grouped to form a set and a block of main
memory can go into any block of a specific set.
 Set Associative Mapping of Cache

This form of mapping removes the drawbacks of direct mapping. In Set-associative mapping,
each word that is present in the cache can have two or more words in the main memory for the
same index address. Set associative cache mapping is a combination of direct and associative
cache mapping techniques.

This also reduces searching overhead present in the associative mapping. Here, searching is
restricted to the number of sets instead of the number of blocks.

b) Explain in detail various types of ROM?

ANS:- What is Read-Only Memory (ROM)?

ROM stands for Read-Only Memory. It is a non-volatile memory that is used to stores
important information which is used to operate the system. As its name refers to read-only
memory, we can only read the programs and data stored on it. It is also a primary memory
unit of the computer system. It contains some electronic fuses that can be programmed for a
piece of specific information. The information stored in the ROM in binary format. It is also
known as permanent memory.
Features of ROM (Read-Only Memory):
 ROM is a non-volatile memory.
 Information stored in ROM is permanent.
 Information and programs stored on it, we can only read.
 Information and programs are stored on ROM in binary format.
 It is used in the start-up process of the computer.
Types of Read-Only Memory (ROM):
1. MROM (Masked read-only memory)
2. PROM (Programmable read-only memory)
3. EPROM (Erasable programmable read-only memory)
4. EEPROM (Electrically erasable programmable read-only memory)
Now we will discuss the types of ROM one by one:
1. MROM (Masked read-only memory): We know that ROM is as old as semiconductor
technology. MROM was the very first ROM that consists of a grid of word lines and bit lines
joined together transistor switches. This type of ROM data is physically encoded in the circuit
and only be programmed during fabrication. It was not so expensive.
2. PROM (Programmable read-only memory): PROM is a form of digital memory. In this
type of ROM, each bit is locked by a fuse or anti-fuse. The data stored in it are permanently
stored and can not be changed or erasable. It is used in low-level programs such as firmware
or microcode.
3. EPROM (Erasable programmable read-only memory): EPROM also called EROM, is a
type of PROM but it can be reprogrammed. The data stored in EPROM can be erased and
reprogrammed again by ultraviolet light. Reprogrammed of it is limited. Before the era of
EEPROM and flash memory, EPROM was used in microcontrollers.
4. EEPROM (Electrically erasable programmable read-only memory): As its name refers,
it can be programmed and erased electrically. The data and program of this ROM can be
erased and programmed about ten thousand times. The duration of erasing and programming
of the EEPROM is near about 4ms to 10ms. It is used in microcontrollers and remote keyless
systems.
2. Explain the following secondary storage devices
i) Magnetic disk

Magnetic disks: A magnetic disk is a storage device that uses a magnetization process to write,
rewrite and access data. It is covered with a magnetic coating and stores data in the form of
tracks, spots and sectors. Hard disks, zip disks and floppy disks are common examples of
magnetic disks.

i. Floppy Disk: A floppy disk is a flexible disk with a magnetic coating on it, and it is
packaged inside a protective plastic envelope. These are among the oldest portable
storage devices that could store up to 1.44 MB of data, but now they are not used due to
very little memory storage.
ii. Hard Disk Drive (HDD): Hard disk drive comprises a series of circular disks
called platters arranged one over the other almost ½ inches apart around a spindle.
Disks are made of non-magnetic material like aluminium alloy and coated with 10-20 nm
magnetic material. The standard diameter of these disks is 14 inches, and they rotate
with speeds varying from 4200 rpm (rotations per minute) for personal computers to
15000 rpm for servers.
Data is stored by magnetizing or demagnetizing the magnetic coating. A magnetic
reader arm is used to read data from and write data to the disks. A typical modern HDD
has a capacity in terabytes (TB).

ii) Magnetic tape

i. Magnetic tape: It is a medium for magnetic recording, made of a thin, magnetizable

coating on a long, narrow strip of plastic film. Devices that record and play audio and
 video using magnetic tape are tape recorders and videotape recorders. A device that
stores computer data on magnetic tape is known as a tape drive.
It was a key technology in early computer development, allowing unparalleled amounts
of data to be mechanically created, stored for long periods, and rapidly accessed.

iii) Optical disk

2. Optical Disk: An optical disk is any computer disk that uses optical storage techniques and
technology to read and write data. It is a computer storage disk that stores data digitally and
uses laser beams to read and write data.

i. CD Drive: CD stands for Compact Disk. CDs are circular disks that use optical rays,
usually lasers, to read and write data. They are very cheap as you can get 700 MB of
storage space for less than a dollar. CDs are inserted in CD drives built into the CPU
cabinet. They are portable as you can eject the drive, remove the CD and carry it with
you. There are three types of CDs:
o CD-ROM (Compact Disk - Read Only Memory): The manufacturer recorded the
data on these CDs. Proprietary Software, audio or video are released on CD-
ROMs.
o CD-R (Compact Disk - Recordable): The user can write data once on the CD-R.
It cannot be deleted or modified later.
o CD-RW (Compact Disk - Rewritable): Data can repeatedly be written and
deleted on these optical disks.
ii. DVD Drive: DVD stands for digital video display. DVD is an optical device that can store
15 times the data held by CDs. They are usually used to store rich multimedia files that
need high storage capacity. DVDs also come in three varieties - read-only, recordable
and rewritable.
iii. Blu Ray Disk: Blu Ray Disk (BD) is an optical storage media that stores high definition
(HD) video and other multimedia files. BD uses a shorter wavelength laser than CD/DVD,
enabling the writing arm to focus more tightly on the disk and pack in more data. BDs
can store up to 128 GB of data.

3 a) tabulate comparison between different memories in terms of speed, size and cost?
 b) Draw static RAM cell. Explain its read write operation and write its merits and
demerits?
ANS:-
Static Memories: Memories that consist of circuits capable of retaining their state as long as power is
applied are known as static memory.

 Two inverters are cross connected to form a batch.

 The batch is connected to two bit lines by transistors T1 and T2.

 These transistors act as switches that can be opened / closed under the control of the word line.

 When the word line is at ground level, the transistors are turned off and the latch retain its state.
Read Operation:

 In order to read the state of the SRAM cell, the word line is activated to close switches T1 and T2.
 If the cell is in state 1, the signal on bit line b is high and the signal on the bit line b is low. Thus b and b
are complements of each other.

 Sense / write circuit at the end of the bit line monitors the state of b and b’ and set the output
accordingly. Write Operation:

 The state of the cell is set by placing the appropriate value on bit line b and its complement on b and
then activating the word line. This forces the cell into the corresponding state.

 The required signal on the bit lines are generated by Sense / Write circuit.

Fig:CMOS cell (Complementary Metal oxide Semi Conductor):

Transistor pairs (T3, T5) and (T4, T6) form the inverters in the latch.

 In state 1, the voltage at point X is high by having T5, T6 on and T4, T5 are OFF.

 Thus T1 and T2 returned ON (Closed), bit line b and b will have high and low signals respectively.

 The CMOS requires 5V (in older version) or 3.3.V (in new version) of power supply voltage.

 The continuous power is needed for the cell to retain its state Merit :

 It has low power consumption because the current flows in the cell only when the cell is being
activated accessed.

 Static RAM’s can be accessed quickly. It access time is few Nano seconds. Demerit:

 SRAM’s are said to be volatile memories because their contents are lost when the power is
interrupted.

4.a) illustrate virtual memory address translation with the help of neat sketch?
ANS:- Virtual Memory:-
1) Virtual Memory was introduced in the system in order to increase the size the size of memory.
2) A hardware unit called Memory Management Unit (MMU) translates Virtual addresses into
physical addresses.
3) If CPU wants data from main memory and it is not present in main memory then MMU
causes operating system to bring the data into the Memory from disk.
4) As the disk limit is beyond the main memory address, the desired data address has to be
translated from Virtual to physical address. MMU does the address translation.
5) Figure below shows Virtual Memory Organization:-

Fig : Virtual Memory Organization

Paging:
1) Virtual Memory space is divided into equal size pages.
2) Main Memory space is divided into equal size page frames each frame can hold any page
from Virtual Memory.
3) When CPU wants to access page, it first looks into main memory. If it is found in main
memory then it is called Hit and page is transfer from main memory to CPU.
4) If CPU needs page that is not present in main memory then it is called as page fault. The
page has to be loaded from Virtual Memory to main memory.
5) There are different page replacement schemes such as FIFO, LRU, LFU, Random Etc.
6) During page replacement, it the old page has been modified in the main memory, then it
needs to be first copied into the Virtual Memory and then replaced. CPU keeps track of such
updated pages by maintaining Dirty bit for each page. When page is updated in main memory
dirty bit is set then this dirty page first copied into Virtual Memory & then replaced.
7) Pages are loaded into main memory only when required by the CPU, then it is called demand
paging. Thus pages are loaded only after page faults.
8) Translation Look-Aside Buffer (TLB) :-
This is a on chip buffer within the CPU, used to speed up the paging process. Since a page
from Virtual Memory can get stored into any frame of main memory, the OS maintains a page
Table which indicates which page of virtual memory is stored in each page frame of main
memory.
Hence for accessing the page CPU has to perform 2 Memory Operations:-
First access the page table to get information about where the page is stored in main memory,
than access the main memory for the page. To solve this problems CPU copies the pages table
information of the most recently used pages in the on-chip TLB. Therefore, subsequent access
to the pages will be faster and information will be provided by the TBL and CPU need not
Access the Table.

b) Explain memory management techniques in detail?

ANS:-

Memory management techniques

1. Swapping

When process is to be executed then that process is taken from secondary memory to stored in RAM.But
RAM have limited space so we have to take out and take in the process from RAM time to time. This
 process is called swapping. The purpose is to make a free space for other processes. And later on, that
process is swapped back to the main memory.

The situations in which swapping takes place

 The Round Robin algorithm is executing in which quantum process is supposed to preempt after
running for some time. In that case, that process is swapped out, and the new process is swapped in.
 When there is a priority assigned to each process, the process with low priority is swapped out, and the
higher priority process is swapped in. After its execution, the lower priority process is again swapped
in, and this process is so fast that users will not know anything about it.
 In shortest time remaining first algorithm when the next process(which arrive in ready queue) is having
less burst time,then executing process is preempted.
 When process have to do I/O operations,then that process temporaily swapped out.

It is further divided into two types:

 Swap-in: Swap-in means removing a program from the hard disk and putting it back in the RAM.
 Swap-out: Swap-out means removing a program from the RAM and putting it into the hard disk.

2. Paging

Paging is the memory management technique in which secondary memory is divided into fixed-size
blocks called pages, and main memory is divided into fixed-size blocks called frames. The Frame has the
same size as that of a Page. The processes are initially in secondary memory, from where the processes
are shifted to main memory(RAM) when there is a requirement. Each process is mainly divided into parts
where the size of each part is the same as the page size. One page of a process is mainly stored in one of
 the memory frames. Paging follows no contiguous memory allocation. That means pages in the main
memory can be stored at different locations in the memory.

3. Compaction

Compaction is a memory management technique in which the free space of a running system is
compacted, to reduce fragmentation problem and improve memory allocation efficiency. Compaction is
used by many modern operating systems, such as Windows, Linux, and Mac OS X. As in the fig we have
some used memory(black color) and some unused memory(white color).The used memory is
combined.All the empty spaces are combined together.This process is called compaction.This is done to
prevent to solve the problem of fragmentation, but it requires too much of CPU time.

By compacting memory, the operating system can reduce or eliminate fragmentation and make it easier
for programs to allocate and use memory.

The compaction process usually consists of two steps:

 Copying all pages that are not in use to one large contiguous area.
 Then write the pages that are in use into the newly freed space.
4. Segmentation

Segmentation is another memory management technique used by operating systems. The process is
divided into segments of different sizes and then put in the main memory. The program/process is divided
into modules, unlike paging, in which the process was divided into fixed-size pages or frames. The
corresponding segments are loaded into the main memory when the process is executed. Segments
contain the program’s utility functions, main function, and so on.

5.a) draw and explain block diagram of synchronos DRAM along with its timing diagram?

SynchronousDRAM(SDRAM) –
These RAM chips’ access speed is directly synchronized with the CPU’s clock. For this, the
memory chips remain ready for operation when the CPU expects them to be ready. These
memories operate at the CPU-memory bus without imposing wait states. SDRAM is
commercially available as modules incorporating multiple SDRAM chips and forming the
required capacity for the modules.
 b) write short notes on cache memory and its uses?

Cache Memory is a special very high-speed memory. It is used to speed up and synchronize
with high-speed CPU. Cache memory is costlier than main memory or disk memory but more
economical than CPU registers. Cache memory is an extremely fast memory type that acts as
a buffer between RAM and the CPU. It holds frequently requested data and instructions so
that they are immediately available to the CPU when needed. Cache memory is used to
reduce the average time to access data from the Main memory. The cache is a smaller and
faster memory that stores copies of the data from frequently used main memory locations.
There are various different independent caches in a CPU, which store instructions and data