High voltage corresponds to logic “ 1” High voltage corresponds to logic “ 0”

Maximum positive value is taken as logic „1 Maximum positive value is taken as logic „0 Finding the dual of a given Boolean expression
+5V ----> logic “1”
„ 1. ∗ ↔ +
+5V ----> logic “0” 2. 0 ↔ 1
0V ----> logic “0 “ 3. Keep the variables as it is
0V ----> logic “1 “

A+ 0 = A A∗ 𝟏 = 𝑨 BVREDDY

1+A= 1 A∗ 𝟎 = 𝟎

A∗ 𝑨 = 𝑨 Distribution Law
A+A=A (Mingle wala)
𝑨𝑩 = 𝑨 + 𝑩 (A+B)(A+C)= A+BC
A∗ 𝑨 = 0 A(B+C)=AB+AC
A+𝑨= 1 𝑨 + 𝑩 = 𝑨𝑩
A+BC= (A+B)(A+C)
BVREDDY

Canonical form : Each minterm ( maxterms ) Literal : A Boolean variable either in

contains all the Boolean variables normal form (or ) complimented form
(A+B)(𝐴 + 𝐶) =AC+𝐴𝐵 F(A, B,C )= ABC+ 𝑨𝑩𝑪 + 𝑨𝑩𝑪 ---->SOP is known as literal
F(A, B, C) = (A+B+C) (A+𝑩 + 𝑪)(𝑨 + 𝑩 + 𝑪) ---> POS Minterm :Each term in canonical SOP
Consensus theorem ( Rajinikanth wala) representation is known as minterm
Minimal Form : The minimized form of Boolean
expression Maxterm: Each term in canonical POS
𝑨𝑩 + 𝑨𝑪 + 𝑩𝑪 = 𝑨𝑩 + 𝑨𝑪 representation is known as maxterm
F(A, B,C )= 𝑩𝑪 + 𝑨𝑩
F(A, B, C) = (A+B) (A+𝑩)(𝑨 + 𝑪)
(A+B)(𝑨 + 𝑪) 𝑩 + 𝑪 = (𝑨 + 𝑩)(𝑨 + 𝑪) BVREDDY
1. Maximum possible minterms = 𝟐𝒏 Neutral Function :
2. Maximum possible maxterms =𝟐𝒏 BVREDDY The number of minterms = number of maxterms
3. Number of minterm‟s + number of maxterm‟s = 𝟐𝒏 Mutually exclusive terms BVREDDY
4. The sum of all the minterms = ONE The mutually exclusive term of 𝑚𝑖 is 𝑚2 −𝑖−1
𝑛

5. The product of all maxterms = ZERO Self Dual Expression

6. Minterm‟s and maxterm‟s of same index are compliment to each If one time dual of the Boolean expression result the same expression ,
other then it is called as self dual expression
7. By using 2- Boolean variables total number of possible Boolean Eg : f = AB+BC+AC
functions = 16 Conditions for the given expression is self dual
8. By using n- Boolean variables total number of possible Boolean 1. The number of minterms = number of maxterms (Neutral Function)
functions =22
𝑛
number of minterms+ number of maxterms = 𝟐𝒏
9. By using 2- Boolean variables total number of possible Boolean number of minterms = number of maxterms = 𝟐𝒏−𝟏
functions having at most 3- minterms = 4𝐶0 +4𝐶1 + 4𝐶2 + 4𝐶3 = 15
2. If 𝑚𝑖 belongs to f , then 𝑚2𝑛−𝑖−1 should belongs to 𝑓
10. By using 2- Boolean variables total number of possible Boolean 𝑛−1
functions having at most 3- maxterms = 15 3. The number of self dual functions =22
11. By using 2- Boolean variables total number of possible Boolean
functions having 3- minterms = 4𝐶3 = 4
12. By using n- Boolean variables total number of possible Boolean
functions having 2- minterms = 𝟐 𝑪
𝒏
𝟐
13. By using 5- Boolean variables total number of possible Boolean
functions having at most 3- minterms = 32𝐶0 +32𝐶1 + 32𝐶2 + 32𝐶3

BVREDDY
 NOT GATE AND GATE OR GATE
𝒀=𝑨 Y = AB Y =A+B
The output is the compliment of the input BVREDDY
• Output is „0‟ if any one input „0‟ • Output is „1‟ if anyone of the inputs are „1‟
A Y=A A Y=A • Y = AB = 𝚺 𝟑 = 𝚷(𝟎, 𝟏, 𝟐) • Y = A+B = 𝚺 𝟏, 𝟐, 𝟑 = 𝚷(𝟎)
• Enable input ⟹ 1 • Enable input ⟹ 0 BVREDDY
RS • Disable input ⟹ 0 • Disable input ⟹ 1
• Commutative law ⟹ Obeys • Commutative law ⟹ Obeys
Y= 𝑨 • Associative law ⟹ Obeys • Associative law ⟹ Obeys
A VS A
A+B A
A AB A A A+B A+B
B B AB
B B
A A RS A
A A RS A B
A B VS A B VS B Y=
A+B
Y = AB
A
A AB
AB A+B
B
B
A A
A+B A
A+B
AB
B B B

BVREDDY
 NAND GATE NOR- GATE
𝒀 = 𝑨𝑩 𝒀=𝑨+𝑩
• Output is ‘1’ if any one input is ‘0’ • Output is ‘0’ if any one of the input is ‘1’
• 𝒀 = 𝑨𝑩 = ∑ 𝟎, 𝟏, 𝟐 = ∏(𝟑) • 𝒀 = 𝑨 + 𝑩 =∑ 𝟎 = ∏(𝟏, 𝟐, 𝟑)
• Enable input --1 • Enable input --0
• Disable input– 0 BVREDDY • Disable input– 1
• Commutative law ---> Obeys • Commutative law ---> Obeys
• Associative law ----> not Obeys • Associative law ----> not Obeys
A 𝐀𝐁 A 𝐀+𝐁
A A+ B A A.B
B B 𝐀𝐁 B B
A+ B BVREDDY
RS
RS
A B A B
A B VS A
VS
B Y=𝑨 + 𝑩
Y =𝐀𝐁

A A
A
AB
B A+B
B B

BVREDDY BVREDDY
 EX-OR GATE BVREDDY A
A A B

 Output is „1‟ for odd number of „1‟s in the input

 Y = 𝐀 ⊕ 𝐁 = ∑ 𝟏, 𝟐 = 𝚷(𝟎, 𝟑) A B
 Y = 𝐀 ⊕ 𝐁 ⊕ 𝐂 = ∑ 𝟏, 𝟐, 𝟒, 𝟕 VS B B VS

 Y = 𝐀 ⊕ 𝐁 ⊕ 𝐂 ⊕ 𝐃 = ∑ 𝟏, 𝟐, 𝟒, 𝟕, 𝟖, 𝟏𝟏, 𝟏𝟑, 𝟏𝟒 Y = A⊕B

 Commutative law ⟹ Obeys
 Associative law ⟹ Obeys
 A⊕0=A
BVREDDY
 A⊕1=A Y = A⊕B
 A⊕A=0 A
 A⊕A=1 B
A , n is odd
 A ⊕ A ⊕ A ⊕………...n times = A B
0, n is even

 A ⊕ 𝐴B = A + B
 AB ⊕ BC = B(A ⊕ C)
Y = A⊕B
A
B

BVREDDY
 A A A B
EX-NOR GATE BVREDDY
Y = A⊙B Y = A⊙B
 Output is „1‟ for even number of „1‟s in the input VS
A B
 Y = A ⊙ B = ∑ 0,3 = Π(1,2) VS
B B
 Commutative law ⟹ Obeys
 Associative law ⟹ not Obeys
 A⊙0=A
 A⊙1=A BVREDDY
 A⊙A=1 A Y = A⊙B
A
Y = A⊙B
 A⊙A=0 B B
 A ⊙ A ⊙ A ⊙………...n times = A , n is odd
1, n is even
 A⊙B=A⊕B
 A⊕B=A⊙B BVREDDY

 A⊕B=A⊙B EX-OR GATE EX-NOR GATE

 A⊕B =A⊕B A B Output is „1‟ for odd Output is „1‟ for even
 A ⊙ B ⊙ C= ∑ 0,3,5,6 number of „1‟s in the input number of „1‟s in the input
 A ⊕ B ⊕ C = ∑ 1,2,4,7
 (A ⊙ B) ⊙ C= ∑ 1,2,4,7
 (A ⊙ C) ⊙ B= ∑ 1,2,4,7 Odd number of 1‟s Even number of 1‟s
 A ⊕ B ⊕ C = A ⊙ B ⊙ C = (A ⊙ C) ⊙ B detector detector
 A⊙B= A⊕B= A⊕B=A⊙B Inequality detector Equality detector
 A⊕B=A⊙B=A⊙B=A⊕B BVREDDY
 A ⊕ B ⊕ C = A⊙ B ⊙ C = [A ⊕ B] ⊙ C = A ⊙ [B ⊕ C] Anti-coincident gate Coincident gate
  For a n- variable Boolean expression , the maximum number of literals = n
No. of NAND No . of NOR
GATES GATES  For a n- variable K- Map if group is done by considering 2m number of cells , then the
resulting term from that group contains ( n- m ) number of literals .
NOT 1 1
 8 𝑐𝑒𝑙𝑙𝑠 − 23 cells  Octet --> 3 variables eliminated
AND 2 3  4 𝑐𝑒𝑙𝑙𝑠 − 22 cells  Quad ---> 2 variables eliminated
OR 3 2  2 𝑐𝑒𝑙𝑙𝑠 − 21 cells  Pair ---> 1 variables eliminated
EX-OR 4 5
 Minimal expression may not be unique .
EX-NOR 5 4
 The minimal expression = ( All EPI‟s ) + ( Optional PI‟s ) Use the Code :
NAND 1 4  If all PI‟s are EPI‟s , then the minimal expression is unique BVREDDY
NOR 4 1  The sufficient condition for a K-map to have unique solution is
number of PI‟s = number of EPI‟s

CD
Minterm mode Maxterm mode
CD CD CD CD
Implicant : Each minterm in canonical SOP expression is known as AB CD
C+D C+D C+D C+D
AB
Implicant . AB ABCD A BC D A BC D A BC D
A+B +C+D A+B +C+D
0 1 3 2 A+B A+B +C+D A+B +C+D
Prime Implicant is a product term , obtained by combining maximum 0 1 3 2
ABCD ABCD ABCD ABCD
possible cells in the K- Map. While doing so make sure that a smaller AB A+B +C+D A+B +C+D A+B +C+D A+B +C+D
4 5 7 6 A+B
group is not completely inside a bigger group . 4 5 7 6
ABCD ABCD ABCD ABCD
Essential Prime Implicant : A prime Implicant is an EPI , if and only AB
12 13 15 14 A+B
A+B +C+D A+B +C+D A+B +C+D A+B +C+D
if it contains at least one minterm which is not covered by multiple ABCD ABCD
12 13 15 14
ABCD ABCD
AB
groups 8 9 11 10 A+B
A+B +C+D A+B +C+D A+B +C+D A+B +C+D
8 9 11 10

Use the Code : BVREDDY ,to get the maximum discount

 Number systems (r-1) ‟ s Complement of the number (N) = 𝑟 𝑛 − 𝑟 −𝑚 − 𝑁
 Base (b) is always a positive integer . r‟ s Complement of the number (N) = (r-1)‟s complement + 𝑟 −𝑚
 In general b ≥ 0 if m= 0
Base Different digits r‟ s Complement of the number (N) = (r-1)‟s complement + 1
2 ( Binary ) 0,1
8( Octal ) 0,1,2,3,4,5,6,7 BVREDDY
10 ( Decimal ) 0,1,2,3,4,5,6,7 ,8,9
 Strictly applicable for positive numbers
 There is no sign bit concept
16 (Hexadecimal) 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F + 5 ------> 101
- 5 -----> not allowed
 Range = 0 to 2𝑛 − 1
BVREDDY
r‟ s Complement of the number (N) = 𝑟 𝑛 − 𝑁
 Valid for both positive and negative numbers .
r --------> Radix
 Sign bit concept is used .
n -------> number of integer digits
N --------> given number Use the Code :
BVREDDY Sign bit Magnitude
Sign bit = 0 , for ⨁Ve number
= 1, for ⊝ 𝑣𝑒 𝑛𝑢𝑚𝑏𝑒𝑟
Range = - 2𝑛−1 − 1 to +(2𝑛−1 − 1)
Use the Code :
BVREDDY BVREDDY
1’s Compliment representation BCD (Binary Coded Decimal)Code
In this ⨁Ve numbers are represented as normal binary In this code each decimal number is Binary B3 B2 B1 B0
number with MSB „0‟ represented by a separate group of 4- bits
BVREDDY
 It uses only 0 to 9
1. Write the binary equivalent of magnitude  0 to 9 are valid BCD Code Gray G3 G2 G1 G0
2. Take its 1‟s compliment  10, 11, 12 , 13 , 14 ,15 are invalid BCD
 Range = - 2𝑛−1 − 1 to +(2𝑛−1 − 1) Code B3 G3 = B3
 Coding method is very simple but it
Over flow occurs in signed arithmetic operations if two same requires more number of bits . B2 G2 = B3⊕B2
sign numbers are added and result exceeds with given EX-3 Code
number of bits . Overflow can be avoided by taking extra bits The EX-3 code can be derived from the
G1 = B2⊕B1
natural BCD code by adding 3 to each coded B1
𝐶𝑖𝑛 −−−−−−−→ 𝑐𝑎𝑟𝑟𝑦 𝑖𝑛𝑡𝑜 𝑀𝑆𝐵 number
𝐶𝑜𝑢𝑡 −−−→ 𝑐𝑎𝑟𝑟𝑦 𝑜𝑢𝑡 𝑓𝑟𝑜𝑚 𝑀𝑆𝐵 Valid EX -3 : 3 ,4,5,6,7,8,9,10,11,12 G0 = B1⊕B0
B0
if 𝐶𝑖𝑛 ⨁𝐶𝑜𝑢𝑡 = 0 , no overflow occurs Invalid EX-3 : 0,1,2,13,14,15
𝐶𝑖𝑛 ⨁𝐶𝑜𝑢𝑡 = 1 , over flow occurs Gray Code Gray G3 G2 G1 G0
2. By using Sign Bits  Non weighted code
X ----------> Sign bit of 1st number BVREDDY  Unit distance code BVREDDY
nd
Y -----------> Sign bit of 2 number  Cyclic code Binary B3 B2 B1 B0
Z-----------> Sign bit of Resultant  Reflective code BVREDDY
Over flow = 𝑿𝒀𝒁 +𝑿𝒀𝒁  Minimum error code G3 B3
2’s Compliment representation SELF COMPLEMENTING CODE
In this ⨁Ve numbers are represented as normal binary A code is said to be self complementing, if G2 B2
number with MSB „0‟ the 1‟ complement of a number N is equal to
the 9‟s complement of the number. G1 B1
1. Write the binary equivalent of magnitude  For a code to be self complementing, the
2. Take its 2‟s compliment sum of all its weights must be 9 . B0
 Range = - 2𝑛−1 to +(2𝑛−1 − 1) 2 4 2 1 5 2 1 1 4 3 1 1 3 3 2 1 EX -3
G0
 Half Adder Full Adder Full Subtractor
BVREDDY
A B Sum Carry A B C Sum Carry A B C Difference Barrow
1. Logical expression for Sum = A⊕ 𝑩
2. Logical expression for Carry = AB 0 0 0 0
3. Minimum number of NAND Gates = 5 0 1 1 0 0 0 0 0 0 0 0 0 0 0
4. Minimum number of NOR Gates = 5
1 0 1 0 0 0 1 1 0 0 0 1 1 1
1. Logical expression for Sum = A⊕ 𝐵 ⊕ 𝐶 1 1 0 1 0 1 0 1 0 0 1 0 1 1
2. Logical expression for Carry =AB+(A⊕ 𝐵)C
3. Minimum number of NAND Gates = 9
Half Subtractor 0 1 1 0 1 0 1 1 0 1
4. Minimum number of NOR Gates = 9 A B Difference Barrow 1 0 0 1 0 1 0 0 1 0
0 0 0 0 1 0 1 0 1 1 0 1 0 0
1. Logical expression for Difference = A⊕ 𝐵
2. Logical expression for Barrow=𝑨𝑩 0 1 1 1 1 1 0 0 1 1 1 0 0 0
3. Minimum number of NAND Gates = 5 1 0 1 0 1 1 1 1 1 1 1 1 1 1
4. Minimum number of NOR Gates =5
1 1 0 0
BVREDDY
1. Logical expression for Difference= A⊕ 𝑩 ⊕ 𝑪
2. Logical expression for Barrow = 𝑨𝑩 + 𝑨⨁𝑩 𝑪 A Sum Difference
A
3. Minimum number of NAND Gates = 9
4. Minimum number of NOR Gates = 9
B C C
B
Carry Barrow

Use the Code : BVREDDY

BVREDDY
 FS : C- A- B Binary Multiplier
FS : A- B- C FS : B- C- A Number of AND gates required = m× 𝑛
Difference = A⊕ 𝐵 ⊕ 𝐶 Difference = A⊕ 𝐵 ⊕ 𝐶
Difference = A⊕ 𝐵 ⊕ 𝐶 Number of Adders required = m+n-2
Barrow = 𝑨𝑩 + 𝑨⨁𝑩 𝑪 Barrow = 𝑪𝑨 + 𝑪⨁𝑨 𝑩
Barrow = 𝑩𝑪 + 𝑩⨁𝑪 𝑨 m-----------> number of bits in A
= 𝑨𝑩 + 𝑨𝑪 + 𝑩𝑪 = 𝐀𝑪 + 𝑩𝑪 + 𝑨𝑩
= A𝑩 + 𝑩𝑪 + 𝑨𝑪 n ------------>number of bits in B
In general for n- bit Parallel Adder For n- bit Magnitude Comparator
Worst case Delay = (n-1) (𝒕𝒑𝒅 𝒄𝒂𝒓𝒓𝒚 + 𝑴𝒂𝒙(𝒔𝒖𝒎 , 𝒄𝒂𝒓𝒓𝒚 ) Total number of input combinations = 22𝑛
2𝑛 𝑛 2 −2
Lesser than combinations =
2
 In this adder ,the carry dependency BVREDDY 22𝑛 − 2𝑛
Greater than combinations =
2
of Ripple Carry Adder (RCA) is eliminated
Equal combinations = 2𝑛
 This is the fastest adder among all
 This adder have the maximum complexity
Hardware Requirements
For 3- bit magnitude comparator
Y1(A<B) = a 2 b2 + a2 ⨀b2 a1 b1 + a2 ⨀b2 a1 ⨀b1 a0 b0
BVREDDY
L1 : n- XOR + n- AND
𝑛(𝑛+1) Y2(A=B) = a2 ⨀b2 a1 ⨀b1 a0 ⨀b0
L2 : − 𝐴𝑁𝐷 carry sum Y3(A>B) = a2 b2 + a2 ⨀b2 a1 b1 + a2 ⨀b2 a1 ⨀b1 a0 b0
2
L3 : n- OR For 4-bit Magnitude Comparator

L4 : n- XOR Y1(A<B) = a3 b3 + (a3⊙b3)(a2 b2) + (a3⊙b3)(a2⊙b2)(a1 b1) + (a3⊙b3)(a2⊙b2)(a1⊙b1)(a0 b0)

𝒏(𝒏+𝟏)
Total number of gates for carry = 3n +
𝟐
Y2(A=B) = (a3⊙b3) (a2⊙b2) (a1⊙b1) (a0⊙b0)
𝒏(𝒏+𝟏)
Total number of gates for sum = 4n +
𝟐 Y3(A>B) = a3b3 + (a3⊙b3)(a2 b2 ) + (a3⊙b3)(a2⊙b2)(a1b1 ) + (a3⊙b3)(a2⊙b2) (a1⊙b1)(a0 b0 )
Worst delay for Carry = Max( xor ,and)+ (𝑡𝑝𝑑 )𝑎𝑛𝑑 + (𝑡𝑝𝑑 )𝑜𝑟

Worst case delay for Sum = Max( xor ,and)+ (𝑡𝑝𝑑 )𝑎𝑛𝑑 + (𝑡𝑝𝑑 )𝑜𝑟 + (𝑡𝑝𝑑 )𝑥𝑜𝑟 BVREDDY
Multiplexer (MUX) Decoder is a special case of
 Data selector BVREDDY  One input to many output Decoder is a multi input ,multi Demultiplexer , in which the
 Many to one  Data distributor output logic circuit which coverts select lines or Demultiplexer
 Universal logic gate
 One to many circuit coded input into coded output , are treated as input's to the
 Parallel to serial converter
𝟐𝒏 × 1 1 × 2𝑛 where the input and output codes decoder and input of
2𝑛 ----------> number of data inputs n---------> number of select lines are different Demultiplexer is treated as
n -----------> number of select inputs 2𝑛 --------> number of output lines Enable input of the Decoder
1 ------------> number of outputs 1 ----------> number of inputs n -------------> number of inputs
BVREDDY -------------> number of outputs
Logic Gate Number of
MUX All 2 variable functions
Encoder is a combinational circuit , which is 1. By using one 4 × 1 Mux
required used to convert Some but not All 3 variable functions
BVREDDY
BUFFER 1 1. Octal to binary ( 8 × 3 encoder ) All 2 variable functions
NOT 1 2. Decimal to Binary ( 10× 4 encoder ) 2. By using one 4 × 1 Mux + NOT
3. Hexadecimal to Binary ( 16 × 4 encoder ) Gate All 3 variable functions
AND 1
2𝑛 𝑋 𝑛 All 3 variable functions
OR 1 n -------------> number of outputs 3. By using one 8 × 1 Mux
2𝑛 -------------> number of inputs Some but not All 4 variable
NAND 2
 For an Encoder at a time only one among functions
NOR 2 the all inputs is high , reaming all inputs All 3 variable functions
should be zero 4. By using one 8 × 1 Mux +
EX-OR 2 All 4 variable functions
 If multiple inputs are simultaneously NOT Gate
EX-NOR 2 high, then the output is not valid, to avoid One 𝟐𝒏 × 1 MUX
HA 3 this restriction we will go for priority 5. n- variable function
encoder.
HS 2 One 𝟐𝒏−𝟏 × 1 MUX + one NOT Gate
BVREDDY
 Sequential Circuits For SR NAND latch , if the input sequence is BVREDDY
00 ---------> 11 , then the following cases arises
The logic circuit whose outputs at any instant of time
 If the delay of both gates are same then we don‟t have any stable output
depends on the present inputs as well as on the past outputs , the output is oscillatory , this condition is known as critical race
are called sequential circuits, in sequential circuits ,the output  However if the delay of both gates are not equal then there exist a
signals are fed back to the input side . BVREDDY
stable output , but it depends on the individual delay of the gates
 Out put of combinational circuit depends on input combinations .
For SR NOR latch , if the input sequence is
 Output of sequential circuits depends on input sequence.
11 ---------> 00 , then the following cases arises
 For unequal delay of gates also the operation is valid
 If the delay of both gates are same then we don‟t have any stable output
NAND LATCH
A NOR LATCH , the output is oscillatory , this condition is known as critical race .
x X  However if the delay of both gates are not equal then there exist a
A
stable output , but it depends on the individual delay of the gates .

B y Y
B FLIP FLOP
In a latch the output changes immediately in response to external input , so
A B X Y A B X Y to have an additional control , we are introducing a signal called “ CLOCK
0 0 1 1 “ , whose purpose is same as Enable pin of Decoder.
0 0 1 1
Latch +Clock = Flip Flop
0 1 0 1 0 1 1 0 Latches are universally not unique and hence their truth tables are not
1 0 1 0 1 0 0 1 unique .
Flip Flops are universally unique , and their truth tables are unique .
1 1 Memory 1 1 Memory
BVREDDY

Use the Code : BVREDDY ,to get the maximum discount

 CLK S R Q Q+ CLK J K Q Q+
1 0 0 0 0 1 0 0 0 0

1 0 0 1 1 1 0 0 1 1
BVREDDY State
CLK J K Q+
1 0 1 0 0
1 0 1 0 0
0 × × Q
CLK S R Q+ State Memory 1 0 1 1 0
1 0 1 1 0
0 × × Q
Memory 1 0 0 Q
Memory 1 1 0 0 1
1 1 0 0 1
1 0 0 Q
Memory 1 0 1 0 1 1 0 1 1
Reset
1 0 1 0 1 1 0 1 1
Reset 1 1 0 1 1 1 1 0 1
1 1 1 0 ×
Set
1 1 0 1
Set 1 1 1 𝑸 1 1 1 1 0
1 1 1 × 1 1 1 1 × Toggle
Invalid
Q Q+ J K
Q Q+ S R S=0 R=X J = 0K = X J=X K=0
S=X R=0 0 0 0 X J=1 K=X
S=1 R=0
0 0 0 X
0 1 1 X Q=0 Q=1
0 1 1 0 Q=0 Q=1
1 0 X 1
1 0 0 1 J=X K=1

1 1 X 0 S=0 R=1 1 1 X 0 BVREDDY

 T Flip Flop
D Flip Flop

CLK D Q Q+ J Q
D J Q D CLK T Q Q+
JK JK
Flip Flop 0 X Q Q CLK Flip Flop 0 X Q Q
K Q BVREDDY K Q
1 0 0 0 + 1 0 0 0
Q =T⊕Q
Q+ = D
1 0 1 0 1 0 1 1
CLK T Q+
CLK D Q+ 1 1 0 1 0 X Hold 1 1 0 1
0 X Hold 1 0 Q
1 0 0 1 1 1 1 1 1 1 0
1 1 Toggle
1 1 1
BVREDDY
D=0
Q Q+ D Q Q+ T T=0 T=0
D=1 T=1
D=1
0 0 0 0 0 0
Q=0 Q=1 Q=0 Q=1

0 1 1 D=0 0 1 1
T=1

1 0 0 1 0 1
BVREDDY
Use the Code :
1 1 1 1 1 0
BVREDDY
Race Around Condition BVREDDY
Master – Slave Flip Flop BVREDDY
The output of the FF changes to 0 1 0 …. Continuously
at the starting of the next clock the output is uncertain , which
JM = 1 S QM JS QS
is called as Race Around Condition (RAC )
M S
RAC occurs in any FF if the following conditions satisfies KM = 1 R QM KS QS
1. If the FFs are operated in level triggering
2. if (tpd ) < (Tclk )on ,
3. If the FFs are operated in Toggle mode CLK
If the above 3 conditions satisfies simultaneously then there is 1. In case of Master Slave configuration , Master is applied with input clock and
a continuous race in the output of the FF between 0 and 1 to Slave is applied with inverted clock , so out of two FFs at a time only one of
reach the next state , who will be the winner of the race in not the FF respond and other will not respond . As a result, Many times toggling in
certain , that depends on tpd and ( Tclk ) on . a single clock cycle has been converted to one time toggle , hence RAC is
Remedy avoided .
1. ( Tclk )on < (tpd ) < T BVREDDY 2. In Master Slave configuration , command signal is generated by master FF
2. By using Edge triggered FF and the response of the command signal is given by slave FF
3. By using Master Slave FF 3. Master slave FF can store 1 – bit of data
C
O F
N L
V I
E
R
of P
S BVREDDY
A F
T L
I
O O
N P
 BVREDDY

CLK CLK
CLK CLK CLK CLK CLK

SISO SIPO PIPO PISO

Data in Data in
Data out Data in
Data in
Data out

 SISO Configuration has only Data out Data out

1- input  SIPO Configuration has only  PIPO Configuration has only  PISO Configuration has only
BVREDDY 1- input 4- input 4- input
1- output
 For SISO configuration 4- output 4- output 1- output
for storing = (n) CP  For SIPO configuration  For PIPO configuration  For PISO configuration
for retrieving = (n-1) CP for storing = (n ) CP for storing = 1 CP for storing = 1 CP
Total number clock pulses = 2n-1 for retrieving = 0 CP for retrieving = 0 CP for retrieving = (n-1)CP
Total number clock pulses = n Total number clock pulses = 1 Total number clock pulses = n
Counters
State of a Counter : Any possible output of a counter is known as its state , for a n – bit counter the maximum possible states are 2n
The states which are counted by the counter are called as valid states , and the states which are not counted (skipped) by the counter are called as
invalid states .
Modulus of a Counter : The minimum number of clocks needed to get the counting pattern repeats is called as Modulus of a counter
Design equation of a counter
BVREDDY 2𝑛 ≥ 𝑁
n----> number of Flip Flops
BVREDDY
N-----> MOD no. of a counter
𝑛 ≥ 𝑙𝑜𝑔2 𝑁
ASYNCHRONOUS COUNTER BVREDDY RING COUNTER
 Different FFs are applied with different clocks  Ring counter is a synchronous counter , it is a shift register in
 For only one FF external clock is applied ,which is LSB and which last FF output is connected to the first FF input .
output of one FF will acts as clock to next FFs  In ring counter only one FF output is logic „1 „ and it will
 FFs are operated in toggle mode rotate with clock .
 Fixed counting sequence ये वक्त भी गुजर जाएगा  Ring counter performs right shift operation .
1. up counter BVREDDY
This time will also pass
2. down counter
 ⊝ve Edge trigger and Q as a clock --------> Up counter
Q3 Q2 Q1 Q0
 ⊝ve Edge trigger and 𝑄 as a clock --------> Down counter CLK
 ⨁ve Edge trigger and Q as a clock --------> Down counter  Decoding logic of ring counter is simple and does not require
 ⊕ve Edge trigger and 𝑄 as a clock --------> Up counter any external logic circuit
 The disadvantages of the ripple counter is that transition states  If all the outputs of FFs initially zero , then the Ring counter
are present due to delay of the FF ( Decoding errors) . does not start .
 If only one FF changes its state ,then no transition states will be  If more than one FF outputs' are high initially, then the ring
present , if more than one FF changes its states than transition counter enters into unused state and never come out of unused
states present. BVREDDY state , this is called as Lock out problem .
 To avoid decoding errors strobe signal is used . JOHNSON RING COUNTER BVREDDY
 Strobe signal is kept low for 3tpd , for 3- bit counter , so that
transition states are not reflected, and after 3tpd strobe signal is
made high .
 If delay each FF is 𝑡𝑝𝑑 , 𝑡𝑕𝑒𝑛
CLK
Q3 Q2 Q1 Q0
𝑇𝐶𝐿𝐾 ≥ 𝑛 𝑡𝑝𝑑

1
𝑓𝐶𝐿𝐾 ≤
𝑡𝑝𝑑 Use the Code :
BVREDDY
 Ring counter Johnson ring counter
Mealy Modal
0/0
1. Mod No = n BVREDDY 1. Mod No = 2n
NS , O/P
2. Number of used states= n 2. Number of used states= 2n Present a 1/0
X =0 X= 1 1/1
state
Number of unused states = 2𝑛 − 𝑛 Number of unused states =22𝑛 − 𝑛
0/0 0/1
d b
3.Time period of each FF = n(𝑇𝐶𝐿𝐾 ) 3.Time period of each FF = 2n(𝑇𝐶𝐿𝐾 ) a a ,0 b,0
0/0 c 1/0

4. Frequency of each FF =
𝑓𝑐𝑙𝑘
4. Frequency of each FF =
𝑓𝑐𝑙𝑘 b b, 1 c,0
𝑛 2𝑛
1/0
5. Suffer from lock out problem 5. Suffer from lock out problem c d, 0 c,0

6.Decoding logic is simple 6.Decoding logic requires AND and d d, 0 a ,1 BVREDDY

NOR gates
Moore Modal
Synchronous Sequential circuits are also called as Finite State Machine ( FSM ) Next State 0
Present Output
There are two types of FSMs state X =0 X=1 𝑎
1. Mealy State Machine 0 0 0
 The output of Mealy State Machine is a function of present state as well as a a b 0
1 𝑑 𝑏 0
present input
0 0
 to detect n – bit sequence by using Mealy modal n number of states are b b c 0
required 0 𝑐 0
2. Moore State Machine
BVREDDY
c d c 0 0
 The output of Moore State Machine is a function of present state only
 To detect n – bit sequence by using Mealy modal (n+1) number of states 1
are required
d a d 1 BVREDDY