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Question Bank DPD All Modules

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85 views5 pages

Question Bank DPD All Modules

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Uploaded by

Anvitha
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© © All Rights Reserved
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DIGITAL PRINCIPLES AND DESIGN

Module wise Question Bank

Module-1: Digital Logic and Principles of combination logic


Module-2: Combinational logic circuit design, Introduction to HDL.
Module-3: Data Processing circuits
Module-4: Latches and Flipflops
Module-5: Registers and Counters

1. What is positive and Negative logic? List the equivalences in positive and negative logic.
2. Explain De-Morgan first and second theorem
3. Realize the basic gates using NOR gates only or Realize the basic gates using NAND gates
only
4. Realize Y = AB+C’ using only one type of gate.
5. Prove that, A(A' + C) (A'B + C) (A'BC + C') = 0
6. Simplify, Y= (A+ B) (A'(B' + C'))' + A'(B + C)
7. Draw the logic circuit for Y=AB’C+ABC. Simplify the equation with Boolean algebra and
draw the simplified logic circuit.
8. Consider this function F(A,B)=AB’+AB. Apply the duality Theorem and obtain its Dual.

9. A digital system has a 4-bit input from 0000 to 1111. Design a logic circuit that produces
a high output whenever the equivalent decimal input is greater than 13.
10. Minimize the following function for SOP and implement it using basic gates.
F(A,B,C,D)= ∑m (0,1,4,8,9,10)+ ∑ d(2,11)
11. Simplify the following using Q-M Method.
F(A,B,C,D)= ∑ m(1, 3, 4, 5, 6, 7, 10, 12, 13)+ ∑ d(2, 9, 15)
F(W,X,Y,Z)= ∑ m(0,1, 4, 6, 8,9, 10, 12)+ ∑ d(5, 7, 14)

12. What is a Map Entered Variable? Using the MEV method simplifies the following function
by taking D as the entered variable.
F(A,B,C,D)= ∑m (2,3,4,5,13,15) + d (8,9,10,11)
13. Plot the following function on a K-Map and find the minimum SOP and POS solution.
F(A,B,C,D)= BD’ + B’CD + ABC + ABC’D + B’D’
14. Using the map-entered variable, use 4 variable maps to find all minimum SOP expression
for the function
G(A,B,C,D,E,F)=m0+m2+m3+m5+m7+m9+m11+m15+d(1,10,13)
15. What is a hazard? Explain the different types of hazards with an example?
16. Write the Verilog structural code the circuit given below

17. For the following K-map give SOP and POS forms that do not show static-0 or static-1
hazard

18. Find the minimal SOP of the following Boolean function using K-MAPs’
(i) f(a,b,c,d) = 𝛴m(6,7,9,10,13) + d(1,4,5,11)
ii) f(w,x,y,z) = 𝛑M(1,2,3,4,9,10 + d(0,1,4,5)
19. Draw the Karnaugh map of Y = F(A,B,C,D) = 𝛑M(0,1,2,4,5,10)+d(8,9,11,12,13,15) and
get the simplified POS form of Kmap.
20. What is the static-0 hazard? Give an example. Also explain how to design a hazard free
circuit. (Or) What is the static-1 hazard? Give an example. Also explain how to design a
hazard free circuit.

21. Explain multiplexer with an example. Realize the 8:1 multiplexer using 2:1 and 4:1
multiplexer.
22. With a neat diagram, explain the 3:8 decoder
23. Show how using a 3-to-8 decoder and multi-input OR gates following Boolean expressions
can be realized simultaneously.
F (A, B, C) = 𝛴m(O, 4, 6); F2(A, B, C) = 𝛴m(O, 5); F2(A, B, C) = 𝛴m(l, 2, 3, 7)
24. Design a circuit that realizes following three functions using a decoder and three OR gates.
F1(A,B,C) =𝛴 m(l,3,7),F2(A,B,C) =𝛴m(2,3,5) and F3(A,B,C) = 𝛴m(O, 1,5,7)
25. Design a circuit that realizes following two functions using a decoder and two OR gates.
F1(A,B) = 𝛴m(0,3) and F2(A,B) =𝛴m(l,2)
26. Show how to connect a 74150(16:1) MUX to implement this Boolean equation:
y = A’BC’D + AB’CD’ + ABCD’
27. Show how two 1-to-16 demultiplexers can be connected to get 1-to-32 demultiplexers.
28. What is a multiplexer? Design a 4-to-1 multiplexer using logic gates, write the truth table
and explain its working principle.
29. Implement the given Boolean function using 8:1 MUX.
Y=f(a,b,c,d) = 𝛴m(0,1,3,5,11,12,13,14)
30. Using a decoder and external gates design the combinational circuit defined by Boolean
functions.
F1 = x’y’z + xz’
F2 = x’yz’ + xy’
F3 = xyz’ + xy
31. Explain how EX-OR gates are ideal for parity checking and parity generation.
32. What is magnitude comparator? Design one bit comparator and write the truth table, logic
circuit using basic gates.
33. Design seven- segment decoder and realize using PLA
34. Differentiate between PLA and PAL. Realize the following using functions using PLA.
Give PLA table and internal connection diagram for the PLA.
F1(a,b,c,d)=∑m(1,2,4,5,6,8,10,12,14)
F2(a,b,c,d)= ∑m(2,4,6,8,10,11,12,14,15)
35. Realize full adder using PAL
36. Implement the following Boolean functions using an appropriate PLA and PAL.
F1(a,b,c)= ∑m(0,4,7)
F2(a,b,c)= ∑m(4,6)
37. Write a Verilog code for a 4-to-1 Multiplexer using conditional assign and case statements.

38. What is a flipflop? Construct NOR-gate( NAND gate) RS flipflop.


39. With a help of a neat diagram, explain the working of Clocked RS-Flipflops.
40. With a help of a neat diagram, explain the working of edge-triggered JK flip-flop.
41. Draw the logic diagram, truth table and timing diagram for edge-triggered D flip flop.
42. With a neat diagram and truth table, explain the working of JK Master – slave flip flop.
43. Construct a switch debouncing circuit using SR Latch and explain its working.
44. Give the state transition diagram of SR, JK and D flip flop.
45. What is the characteristic equation of SR, JK, D and T flip flop.
46. Show how a D flipflop can be converted to JK flipflop.
47. Analyze the circuit shown below and find the output Y.
48. With the neat sketch, explain the working principle of SISO (Serial In Serial Out) shift register.
49. Define register and what are the types of registers. Explain switched tail counter with a
neat diagram.
50. With a neat diagram, show how a shift register can be applied for serial addition.
51. With a neat diagram, explain how a shift register can be used as a sequence detector.
52. What are synchronous and asynchronous counters. With a neat block diagram, output
waveform and truth table, explain a 3-bit binary ripple counter constructed using negative
edge- triggered JK flipflops,
53. Design a mod-5 counter using JK flipflops having the feature that if an unused state
appears, the counter will reset to 000 at the next clock pulse.
54. Design a synchronous mod-6 counter using JK flipflops.
55. Design asynchronous counter for the sequence 0→4→1→2→6→0→4 using SR Flipflop.
56. What do you mean by lockout condition in counters? Using JK flipflop design a self-
correcting mod-6 counter.
57. Write Verilog code for switched tail counter.
58. With neat block diagrams, compare Mealy model and Moore model of sequential logic
system.
59. Design a sequence detector that receives binary data stream at its input X and signals when
a combinations ‘011’ arrives at the input by making its output Y high which otherwise
remains 0. Here consider that the data is coming from left, i.e. the first bit to be identified
is 1, second bit is 1 and third bit is 0 from the input sequence. Design using Mealy model.
60. Design a sequence detector that receives binary data stream at its input X and detects three
consecutive zeros and signals by making its output Y high which otherwise remains 0.
Design using Mealy model.
61. Build a synchronous counter for the sequence 0 → 3 → 1→ 2→ 6 → 7→ 0 → 3 using
JK flip-flops. Differentiate between synchronous and asynchronous counters
62. Draw the ASM chart for the Moore model shown below:
63. With the help of state diagram and state and transition table and timing diagram explain sequential
parity checker.
64. Design ASM chart, design equation and circuit diagram for vending machine problem
using mealy model.
65. What is the use of state reduction technique?. Using row elimination method, simplify the
following table. (or What is the use of state reduction technique?. Using Implication table
method, simplify the following table.).

66. With the help of state graph, state and transition table and timing diagram, Explain the
working of sequential parity checker.

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