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LAB Experiment 3 NOT Gate

not gate experiment time na

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Mark Daniel Abuda II
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88 views2 pages

LAB Experiment 3 NOT Gate

not gate experiment time na

Uploaded by

Mark Daniel Abuda II
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Republic of the Philippines

CAVITE STATE UNIVERSITY


Imus Campus
Cavite Civic Center Palico IV, Imus, Cavite
 (046) 471-6607/ (046) 471-6770/ (046) 6862349
www.cvsu.edu.ph

NAME:______________________________________________ Course and


Section:____________

COSC 65B – ARCHITECTURE AND ORGANIZATION


LABORATORY EXPERIMENT NO. _______

NOT GATE
I. Aim: To verify basic Logic gates.
II. Materials/Tools:
Wire stripper, solid wire # 22, bread board, LED, Digital IC (7408 AND
Gate), 9v battery or power supply, resistor, alligator clips
III. CIRCUIT DIAGRAM:

A NOT A

IV. PROCEDURE:
1. Plug the chips you will be using into the breadboard. Point all the chips
in the same direction with Pin 1 at the upper left corner.
2. Connect +5v and GRND pins of each chip to the power and ground bus
strips on the breadboard.
3. Make the connection as per circuit diagram.
4. Switch on +VCC and apply various combinations of input according to
the Truth Table.

V. REVIEW QUESTIONS:
1. Why do we use a NOT gate?
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
_____________________
2. Explain the behavior of a NOT gate when the input is LOW and when it is
HIGH..________________________________________________________________________
______________________________________________________________________________
______________
______________________________________________________________________________
_______

3. How does a NOT gate change the logical state of its input?
______________________________________________________________________________
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_______________

VI. CONCLUSION:

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