UNIT III APPLICATIONS OF OPAMP

Instrumentation amplifier and its applications for transducer

Bridge, Log and Antilog Amplifiers- Analog multiplier & Divider,
first and second order active filters, comparators, multivibrators,
waveform generators, clippers, clampers, peak detector, S/H
circuit, D/A converter (R- 2R ladder and weighted resistor types),
A/D converters using op-amps

3.1 INSTRUMENTATION AMPLIFIER

Instrumentation Amplifier (In-Amp) forms the basic component of

every measuring instrument and testing equipment.
Instrumentation Amplifier is a type of Differential Amplifier which
offers high Common-Mode Rejection. Instrumentation Amplifier is
available in integrated circuit form and can also be built using
Op-amps and Resistors which have very low tolerance value
called as Precision Resistors. This post will provide you a better
understanding about what is Instrumentation Amplifier, its
Working Principle, Applications, Advantages and Disadvantages.

Instrumentation Amplifiers are basically used to amplify small

differential signals. Instrumentation Amplifier provides the most
important function of Common-Mode Rejection (CMR). It cancels
out any signals that have the same potential on both the inputs.
The signals that have a potential difference between the inputs
get amplified.
An Instrumentation Amplifier (In-Amp) is used for low-frequency
signals (≪1 MHz) to provide a large amount of Gain. It amplifies
the input signal rejecting Common-Mode Noise that is present in
the input signal.

Basically, a typical Instrumentation Amplifier configuration

consists of three Op-amps and several resistors. To achieve the
highest CMRR (Common Mode Rejection Ratio), high-precision
resistors are used (0.1 % tolerance or better).

Fig. 2 below shows the Pin configuration and Physical view of IC,
AD620 In-Amp (Instrumentation Amplifier). This has been the
industry standard, high performance, low cost amplifier. It is
completely monolithic available in both 8-lead DIP and SOIC
packages. The user can obtain any desired gain from 1 to 1000
using a single external resistor. By design, the fixed resistor
values for gains of 10 and 100 are standard 1% metal film
resistor values.
Fig. 2 – (a) Pin Configuration (b) AD620 Instrumentation
Amplifier

3.1.1 Working Principle of Instrumentation Amplifier

Figure 3 below represents the configuration of the
Instrumentation Amplifier using two Op-amps where V1 and V2
are the input voltages and V01, Vo2 are the outputs of the Op-
amp 1 and Op-amp 2 respectively. R1, R2, R3 are the resistors
and the output stage of the Instrumentation Amplifier is a
difference amplifier, whose output V out is the amplified difference
of the input signals.

The inputs of the two buffer Op-amps draw no current and hence
the voltage drop across Rg is proportional to the differential
voltage V1 and V2. This produces a current that runs entirely
through the resistors R and the voltage produced acts as the
input to the differential amplifier or Subtractor circuit.
All the Resistors except Rg are equal. Rg may be an external
resistor connected across two pins of the IC. If the pins are not
connected, then the gain of the amplifier is 1 but preferably
different gains may be obtained by connecting a resistor of
relevant value. Alternatively, a number of resistors may be
fabricated on the chip to give Gains of 1, 10, 100 and 1000.

Fig. 3 – Instrumentation Amplifier Configuration

Similar to the Op-amp circuit, the input buffer amplifiers (Op-amp

1 and Op-amp 2) of the Instrumentation Amplifier pass the
common-mode signal through at unity gain. The signal gets
amplified by both buffers. The output signals from the two
buffers connect to the subtractor section of the Instrumentation
amplifier. The differential signal is amplified at low gain or unity
and the common-mode voltage is attenuated.
The potential at node A is the inverting input voltage V 1. From
the virtual short concept the potential at node B and G is also V 1.
The potential at node D is the non-inverting input voltage V 2.
Hence the potential at node C and H is also V 2 .The current I
through the resistors R1, Rgain and R1 remains the same as ideally
the current to the input stage Op-amps is zero.

Applying Ohm’s law between the nodes E and F

I = (Vo1-Vo2)/(R1+Rgain+R1)
I = (Vo1-Vo2)/(2R1+Rgain)
Since there is no current flow to the input of the op-amps 1 & 2,
the current I between the nodes G and H can be given as,
I = (VG-VH)/Rgain = (V1-V2)/Rgain
The output of the difference amplifier is given by
Vo = (R3/R2)(Vo1-Vo2)
Theoretically, this means that the end user may obtain Gain in
the front end as desired without increasing the common-mode
gain and error. That is, the differential signal will be increased by
gain and thus CMRR is directly proportional to gain.

3.1.2 Applications of Instrumentation Amplifier

The applications of Instrumentation Amplifier are:

 They are used extensively in Bio-medical applications like
ECG’s and EEG’s.
  Instrumentation Amplifiers are used where long-term
stability is essential like Industrial applications that
includes automation.
 Instrumentation amplifiers are incorporated with pressure
transducers in Weighing Systems to monitor various
physical quantities such as weight, force, pressure,
displacement and torque.
 They are used in Gaming industry.Instrumentation
Amplifiers are also used in hand held batteries.

3.1.3 Advantages of Instrumentation Amplifier

The advantages of Instrumentation Amplifier are:
 Offset voltage is minimized.
 Voltage Gain is high as the configuration uses high
precision resistors.
 The Gain of the circuit can be varied by using specific value
of resistor.
 Non-linearity is very low. It is an inherent performance
limitation of the device and cannot be removed by external
adjustment but can only be designed by the manufacturer.
 Input impedance is very high to avoid loading down the
input signal source and Output impedance is very low.
 Common-mode rejection is very high.

3.1.4 Disadvantage of Instrumentation Amplifier

  The biggest disadvantage of Instrumentation Amplifier is
the occurrence of noise when used for long range
transmission purpose

3.1.5 Differential Instrumentation Amplifier Transducer

Bridge
Figure 14.25 shows a simplified circuit of a Differential
Instrumentation Amplifier Transducer Bridge.In this circuit
a resistive transducer (whose resistance changes as a function of
some physical energy) is connected to one arm of the bridge. Let
RT be the resistance of the transducer and ΔR the change in
resistance of the resistive transducer. Hence the total resistance
of the transducer is (RT ± ΔR).

Fig. 4 Differential Instrumentation amplifier using Transducer

bridge

The condition for bridge balance is V b = Va, i.e. the bridge is

balanced when Vb = Va, or when
RB ( E ) R ( E)
= A
R B + RC R A + R T
 R C RT
=
RB R A

The bridge is balanced at a desired reference condition, which

depends on the specific value of the physical quantity to be
measured. Under this condition, resistors R A, RB and RC are so
selected that they are equal in value to the transducer resistance
RT. (The value of the physical quantity normally depends on the
transducers characteristics, the type of physical quantity to be
measured, and the desired applications.)

Initially the bridge is balanced at a desired reference condition.

As the physical quantity to be measured changes, the resistance
of the transducer also changes, causing the bridge to be
unbalanced (Vb # ). Hence, the output voltage of the bridge is a
function of the change in the resistance of the transducer. The
expression for the output voltage V 0, in terms of the change in
resistance of the transducer is calculated as follows.

Let the change in the resistance of the transducer be ΔR. Since

RB and RC are fixed resistors, the voltage Vb is constant, however,
the voltage Va changes as a function of the change in
the transducers resistance. Therefore, applying the voltage
divider rule we have
R A ( E) RB ( E)
V a= ∧V b =
R A + ( RT + ∆ R ) R B + RC
The output voltage across the bridge terminal is V ab, given
by Vab=Va-Vb
Therefore,
RA (E ) RB ( E )
V ab= −
R A + ( RT + ∆ R ) R B + RC
R A =R B=RC =R T =R ,then

V ab=
R (E )
−
2 R+∆ R 2 R
R ( E)
=E
R
(
−
2 R+ ∆ R 2
1
)
V ab=E
( 2 R−2 R−∆ R
2 ( 2 R+ ∆ R )
=
)−∆ R ( E )
2 ( 2 R+ ∆ R )
… .14 .15

The output voltage Vab of the bridge is applied to the Differential

Instrumentation Amplifier Transducer Bridge through the voltage
followers to eliminate the loading effect of the bridge circuit. The
gain of the basic amplifier is (R F/R1) and therefore the output
voltage Vo of the circuit is given by

V 0=V ab
( )
RF
=
−∆ R ( E )
X
RF
R 1 2 (2 R+ ∆ R ) R1
… .(14.16)

It can be seen from the Eq. (14.16) that V o is a function of the

change in resistance ΔR of the transducer. Since the change is
caused by the change in a physical quantity, a meter connected
at the output can be calibrated in terms of the units of the
physical quantity.
3.1.6 Applications of Instrumentation Amplifier
Transducer Bridge

We shall now consider some important applications of

instrumentation amplifiers using resistance types transducers. In
these transducers, the resistance of the transducer changes as a
function of some physical quantity. Commonly used resistance
transducers are thermisistors, photoconductor cells, and strain
gauges.

3.2 LOG AMPLIFIER

A logarithmic amplifier (or a log amplifier) is an electronic circuit
that produces an output that is proportional to the logarithm of
the applied input. Other applications for log/anti-log amplifiers
include signal compression and process control. Signals are often
compressed in order to decrease their dynamic range (i.e., the
difference between the highest and lowest level signals). In
telecommunications systems, this may be required in order to
achieve reasonable voice or data transmission with limited
resources. An op-amp based logarithmic amplifier produces a
voltage at the output, which is proportional to the logarithm of
the voltage applied to the resistor connected to its inverting
terminal.

I E =( e
( q V E /kT )−1
)Since
I C =I E
For a grounded base transistor,

I C =I s ( e )
(q V E / kT )−1
Where
I s=Emitter saturation current 10−13 A
k = Boltzmann’s Constant
T= Absolute temperature (in K)
Therefore,
e(
q V E / kT )
=( I C /I s ) +1=I C /I s (neraly equal)
Taking natural log on both sides, we get
¿
V E=( kT /q ) ln ( I C / I s )
Also

V E=−V 0

Fig. 5. Representation of Log Amplifier

3.2.1 Applications of the logarithmic amplifier

Log amplifier is used for mathematical applications and also in
different devices as per their need. Some of the applications of
the log amplifier are as follows:
 Log amplifiers are used for mathematical applications,
mainly in multiplication. It is also used in the division and
other exponential operations too. As it can perform
multiplication operation, hence it is used in analog
 computers, in synthesizing audio effects, measuring
instruments that require multiplication operation such as in
calculating power (multiplication of current and voltage).
 As we know that when we need to calculate the decibel
equivalent of a given quantity, we require the use of a
logarithmic operator, and hence, log amplifiers are used to
calculate decibel (dB) value of a quantity.
 Monolithic logarithmic amplifiers are used in certain
situations, like in Radio Frequency domain, for efficient
spacing (reducing components and space needed by
them), and also to improve bandwidth and noise rejection.
 It is also used in different ranges of applications such as rot
mean square converter, an analog-to-digital converter, etc.

An anti-logarithmic amplifier, or an anti-log amplifier, is an

electronic circuit that produces an output that is proportional to
the anti-logarithm of the applied input. This section discusses
about the op-amp based anti-logarithmic amplifier in detail. An
op-amp based anti-logarithmic amplifier produces a voltage at
the output, which is proportional to the anti-logarithm of the
voltage that is applied to the diode connected to its inverting
terminal.

The circuit diagram of an op-amp based anti-logarithmic

amplifier is shown in the following figure 6.
 Fig.6. Anti-logarithmic amplifier
V 0=R f I s e(
V ¿/ V T )

Note that, in the above equation the parameters n, V T and Is are

constants. So, the output voltage V 0 will be proportional to the
anti-natural logarithm(exponential) of the input voltage V i, for a
fixed value of feedback resistance Rf.

3.3.1 Output and working principle of antilog amplifier

As observed in the circuit shown above, the negative feedback is
achieved by connecting the output to the inverting input
terminal. According to the concept of the virtual ground between
the input terminals of an amplifier, the voltage V 1 at the inverting
terminal will be zero. Because of ideally infinite input impedance,
the current flowing through the diode due to the applied input
voltage in the inverting terminal will not enter the op-amp;
instead, it will flow along the feedback path through the resistor
R as shown in the figure.

The compliment or inverse function of the logarithmic amplifier is

‘exponential’, anti-logarithmic or simply known as ‘antilog’.
Consider the circuit given in the figure. The diode current is
Where, VD is the diode voltage. According to the concept of
virtual ground, V1=0 as the non-inverting terminal is grounded as
shown in the figure. Therefore the voltage across the diode can
be expressed as VD = Vi – V1 or VD = Vi Hence, the current through
the diode is

Due to the ideal characteristics of an op-amp (infinite input

impedance), the current flowing through the diode ( i D) flows
along the feedback path through the resistor R, as we can
observe in the figure.
Therefore iD = i2
And, V0 = -i2R = -iDR

Replacing iD in the above equation we get

The parameters n, VT and IS are constants (they are only depend

on the diode characteristics which are always constant for a
particular diode). Therefore if the value of the feedback resistor
R is fixed, then the output voltage V 0 is directly proportional to
the natural anti-logarithm (exponential) of the applied input
voltage Vi. The above equation then can be simply represented
as
Where K = – ISR and a =
Therefore we can notice that the anti-logarithmic op-amp
produces its output signal as the exponential value of the input
voltage signal applied.
The gain of the anti-log amplifier is given by the value of K that is
equal to -ISR.
The –ve sign point out that there is a phase difference of
180degrees between the applied input s and the output of the
anti-log amplifier.

3.4 ANALOG MULTIPLIER ICS

Analog multiplier is a circuit whose output voltage at any instant

is proportional to the product of instantaneous value of two
individual input voltages. Important applications of these
multipliers are multiplication, division, squaring and square –
rooting of signals, modulation and demodulation. These analog
multipliers are available as integrated circuits consisting of op-
amps and other circuit elements. The Schematic of a typical
analog multiplier, namely, AD633 is shown in figure.
 Fig 7 Multiplier IC and its symbol

 The AD633 multiplier is a four – quadrant analog multiplier.

 It possesses high input impedance; this characteristic
makes the loading effect on the signal source negligible.
 It can operate with supply voltages ranging from ±18V
 IC does not require external components.
 The typical range of the two input signals is ±10V.

3.4.1 Schematic representation of a multiplier

The schematic representation of an analog multiplier is shown in
figure. The output V0 is the product of the two inputs V x and Vy is
divided by a reference voltage V ref. Normally, the reference
voltage Vref is internally set to 10V. Therefore, V0 =V xVy/10. In
other words, the basic input – output relationship can be defined
by KVx Vy when K = 1/10, a constant. Thus for peak input
voltages of 10V, the peak magnitude of output voltage is 1/10
*10 *10 =10V. Thus, it can be noted that, as long as V x < 10V
and Vy < 10V, the multiplier output will not saturate.

Multiplier quadrants
The transfer characteristics of a typical four-quadrant multiplier
are shown in figure. Both the inputs can be positive or negative
to obtain the corresponding output as shown in the transfer
characteristics.

3.4.2 Applications of Multiplier ICs

The multiplier ICs are used for the following purposes:
1. Voltage Squarer
2. Frequency doublers
3. Voltage divider
4. Square rooter
5. Phase angle detector
6. Rectifier
 Fig. 7. transfer characteristics of a typical four quadrant
multiplier

Voltage Squarer

Fig. 8 Voltage squarer Circuit

Figure shows the multiplier IC connected as a squaring circuit.

The inputs can be positive or negative, represented by any
corresponding voltage level between 0 and 10V. The input
voltage Vi to be squared is simply connected to both the input
terminals, and hence we have, Vx = Vy = Vi and the output is V0
= KVi2. The circuit thus performs the squaring operation. This
application can be extended for frequency doubling applications.

Frequency doublers:
Figure shows the squaring circuit connected for frequency
doubling operation. A sine-wave signal Vi has a peak amplitude
of Av and frequency of f Hz. Then, the output voltage of the
doublers circuit is given by
2 2
A v sin 2 πft∗A v sin 2 πft A v 2 Av
V 0= = sin 2 πft= (1−cos 4 πft )
10 10 20

Assuming a peak amplitude Av of 5V and frequency f of 10KHz,

V0 =1.25–1.25 cos2 20000) t. The first term represents the dc
term of 1.25V peak amplitude. The input and output waveforms
are shown in figure. The output waveforms ripple with twice the
input frequency in the rectified output of the input signal. This
forms the principle of application of analog multiplier as rectifier
of ac signals.

Fig.9. (a) Circuit diagram (b)input-output waveform of frequency

doubler

The dc component of output V 0 can be removed by connecting a

1µF coupling capacitor between the output terminal and a load
resistor, across which the output can be observed.
Voltage Divider:
In voltage divider circuit the division is achieved by connecting
the multiplier in the feedback loop of an op-amp.
The voltages Vden and Vnum represent the two input voltages, Vdm
forms one input of the multiplier, and output of op-amp VoA
forms the second input.

The output VOA forms the second input. The output VOM of the
multiplier is connected back of op- amp in the feedback loop.
Then the characteristic operation of the multiplier gives
Vom = KVOA Vdm (1)

Fig. 3.10 Divider circuit

As shown in figure, no input signal current can flow into the

inverting input terminal of op-amp, which is at virtual ground.
Therefore, at the junction a, i1 + i2 =0, the current i1 = Vnum / R,
where R is the input resistance and the current i 2 = Vom /R. With
virtual ground existing at a,
i1+i2 = Vnum / R + Vom /R = 0
KVOA Vden = - Vnum
or
voA=- vnum/Kvden
where Vnum and Vden are the numerator and denominator voltages
respectively. Therefore, the voltage division operation is
achieved. Vnum can be a positive or negative voltage and Vden can
have only positive values to ensure negative feedback.
When Vdm is changed, the gain 10/Vdm changes, and this feature
is used in automatic gain control (AGC) circuits.

Square Rooter:
The divider voltage can be used to find the square root of a
signal by connecting both inputs of the multiplier to the output of
the op-amp. Substituting equal in magnitude but opposite in
polarity (with respect to ground) to Vi. But we know that Vom is
one- term (Scale factor) of V0 * V0 or -Vi = Vom = V2/1 0
Solving for V0 and eliminating √-1 yields. V0 = √10|Vi |
Eqn. states that V0 equals the square root of 10 times the
absolute magnitude of Vi.
The input voltage Vi must be negative, or else, the op-amp
saturates.
The range of Vi is between -1 and -10V. Voltages less than -1V
will cause inaccuracies in the result.
The diode prevents negative saturation for positive polarity Vi
signals. For positive values of Vi the diode connections are
reversed.
Phase Angle detector:
The multiplier configured for phase angle detection
measurement is shown in figure. When two sine-waves of the
same frequency are applied to the inputs of the multiplier, the
output V0 has a dc component and an AC component.
The trigonometric identity shows that Sin A sin B =1/2 (cos (A-B)
– cos (A+B)).
When the two frequencies are equal, but with different phase
angles, e.g. A=2πft +θ for signal Vx and B= 2πft for signal V y,
then using the identity
[sin (2 ft+ )][sin2 ft)]=1/2[cos -cos(4 ft + )]=1/2(dc- the double
frequency term)
Therefore, when the two input signals V x and Vy are applied to
the multiplier, V0 (dc) is given by

v xp v yp
V v ( dc )= cos θ
20
where Vxp and Vyp are the peak voltage amplitudes of the signals
Vx and Vy. Thus, the output V0(dc) depends on the factor cos θ. A
dc voltmeter can be calibrated as a phase angle meter when the
product of Vxp and Vyp is made equal to 20. Then, a (0-1) V range
dc voltmeter can directly read cos θ, with the meter calibrated
directly in degrees from a cosine table. The input and output
waveforms are shown in figure.

Then the above eqn becomes V0 (dc) = cos θ, if we make the

product Vxp Vyp = 20 or in other words, Vxp – Vyp = 4.47V.
 Fig.3.11 Phase angle measurement

Fig.3.12 Input-output waveforms of phase angle detector

3.5 ACTIVE FILTERS USING OPERATIONAL AMPLIFIER

Active filters
An electric filter is often a frequency selective circuit that passes
a specified band of frequencies and blocks or alternates signal
and frequencies outside this band. Filters may be classified as
1. Analog or digital.
2. Active or passive
3. Audio (AF) or Radio Frequency (RF)

1. Analog or digital filters:

Analog filters are designed to process analog signals, while
digital filters process analog signals using digital technique.

2. Active or Passive:
Depending on the type of elements used in their construction,
filter may be classified as passive or Active elements used in
passive filters are Resistors, capacitors, inductors. Elements used
in active filters are transistor, or op-amp.

Active filters offer the following advantages over passive filters:

1. Gain and Frequency adjustment flexibility:
Since the op-amp is capable of providing gain, the i/p signal is
not attenuated as it is in a passive filter. [Active filter is easier to
tune or adjust].
2. No loading problem:
Because of the high input resistance and low o/p resistance of
the op-amp, the active filter does not cause loading of the source
or load.
3. Cost:
Active filters are more economical than passive filter. This is
because of the variety of cheaper op-amps and the absence of
inductors.

The most commonly used filters are these:

1. Low pass Filters
2. High pass Filters
3. Band pass filters
4. Band –reject filters
5. All pass filters.

3.5.1 Frequency response of the active filters

Fig. 3.13 Frequency response of Low Pass filter and High

pass filter
Fig.3.14 Frequency response of Band Pass filter and Band reject
filter

Low pass filters

 It has a constant gain from 0 Hz to a high cutoff frequency
f1.
 At fH the gain in down by 3db.
 The frequency between 0 Hz and fH are known as the pass
band frequencies where as the range of frequencies those
beyond fH, that are attenuated includes the stop band
frequencies.
 Butterworth, Chebyshev and Cauer filter are some of the
most commonly used practical filters.
 The key characteristics of the butter worth filter are that it
has a flat pass band as well as stop band. For this reason,
it is sometimes called flat- flat filters.
 Chebyshev filter -> has a ripple pass band & flat stop
band.
 Causer Filter -> has a ripple pass band & ripple stop band.
It gives best stop band response among the three.

High pass filter:

High pass filter with a stop band 0 <f< f L and a pass band f> f L

fL -> low cut off frequency

f -> operating frequency.
Band pass filter:
It has a pass band between 2 cut off frequencies f H and fL where
fH > fL and two, stop bands: 0<f< fL and f > fH between the band
pass filter (equal to fH - fL).
Band –reject filter: (Band stop or Band elimination)
It performs exactly opposite to the band pass.
It has a band stop between 2 cut-off frequency fL and fH and 2
pass bands: 0<f< fL and f> fH fC -> center frequency.

Note:
The actual response curves of the filters in the stop band either
R or S or both with Rin frequencies. The rate at which the gain of
the filter changes in the stop band is determined by the order of
the filter.

Ex: 1st order low pass filter the gain rolls off at the rate of
20dB/decade in the stop band. (i.e) for f > fH.
2nd order LPF -> the gain roll off rate is 40dB/decade.
1st order HPF -> the gain rolls off at the rate of 20dB (i.e.) until
f:fL
2nd order HPF -> the gain rolls off at the rate of 40dB/decade

3.5.2 First order LPF Butterworth filter

First order LPF that uses an RC for filtering op-amp is used in the
non inverting configuration. Resistor R1 & Rf determine the gain
of the filter. According to the voltage –divider rule, the voltage at
the non-inverting terminal (across capacitor) C is,
 Fig. 3.15 First order LPF Butterworth filter

Gain A= (1+Rf/R1)
Voltage across capacitor V1= Vi / (1+j2πfRC)
Output voltage V0 for non inverting amplifier =A V1
= (1+Rf/R1) Vi/(1+j2πfRC)
Overall gain V0/Vi = (1+Rf/R1) Vi/(1+j2πfRC)
Transfer function H(s) =A/(jf/fh+1) if fh =1/2πRC
H (jω) = A/( jωRC+1) = A/( jωRC+1).

The gain magnitude and phase angle of the equation of the LPF
can be obtained by converting eqn. (1) b into its equivalent polar
form as follows.
1. At very lowω)|frequency, f < fH
|H (jω) =A
2. At f =fH
|H (jω)| =A/√2=0.707A
3. At f> fH
|H (jω)| <<A ≅ 0
When the frequency increases by tenfold (one decade), the volt
gain is divided by 10. The gain falls by 20 dB (=20log10) each
time the frequency is reduces by 10. Hence the rate at which the
gain rolls off fH = 20 dB or 6dB/octave (twofold Rin frequency).
The frequency f = fH is called the cut off frequency because the
gain of the filter at this frequency is down by 3 dB (=20 log
0.707).

Filter design
A LPF can be designed by implementing the following steps.
1. Choose a value of high cut off frequency fH.
2. Select a value of C less than or equal to 1μf.
3. Choose the value of R using fh=1/2πRC
4. Finally select values of R1 and RF dependent on the desired
pass band gain AF Using A=(1+Rf/R1)

3.5.3 Second order LP Butterworth filter

A second order LPF having a gain 40dB/decade in stop band. A
First order LPF can be converted into a II order type simply by
using an additional RC network. The gain of the II order filter is
set by R1 and RF, while the high cut off frequency f H is determined
by R2, C2, R3 and C3.
Fig 3.16 Second order LP Butterworth filter
1
Let Y 1=Y 2 =
R
Y 3=s C 3∧Y 4 =s C 4
Then the transfer function is
1
2
R 1
H ( s )= =
1
R
2
2
(
+s C4 +s C3
R )
1+sR C4 ( 2+ sR C 3 )

Let the time constant τ 1 =R C 3∧τ 2=R C 4

Sub s=jω ,we get
1 1
H ( jω )= =
1+ jω τ 2 ( 2+ jωτ 1 ) ( 1−ω2 τ 1 ) + j ( 2 ω τ 2 )

Therefore its magnitude is

|H ( jω )|=[ ( 1−ω 2 τ 1 τ 2 ) + ( 2 ω τ 2 )2 ]
2 −1/ 2

A maximally flat Butterworth filter will have a minimum rate of

change.
Therefore
d|H|
|
dω ω=0
=0

Differentiating |H ( jω )|, we obtain

 d| H| −1
[ ] [
−3 / 2
]
2

dω
=
2
( 1−ω 2 τ 1 τ 2 ) + ( 2ω τ 2 )2 −4 ω τ 1 τ 2 ( 1−ω 2 τ 1 τ 2 ) + 8 ω τ 22

Letting the derivative to zero at ω=0 ,we get

d|H|
|
dω ω=0 [
= −4 ω τ 1 τ 2 ( 1−ω2 τ 1 τ 2 ) + 8 ω τ 22 ]
[
¿ 4 ω τ 2 −τ 1 ( 1−ω τ 1 τ 2 ) + 2 τ 2
2
]
The above equation is satisfiedd when 2τ 2=τ 1 . That is, C 3=2 C4.
Therefore the magnitude of the transfer function becomes

1
|H|=
[ 1+ 4 ( ω τ ) ] 2
4 1/ 2

1
The cut-off frequency occurs when |H |=
4
or 4 ( ω3 db τ 2 ) =1
√2
Therefore
1 1
ω 3 db=2 π f 3 db= =
τ 2 √2 √2 R C4
1
We know that the cutoff frequency is ω H =ω3 db=
RC
Comparing the above equations, we get
C 4=0.707 C
C 3=1.414 C
The magnitude of the voltage transfer function for the second
order low-pass Butterworth filter is
1
|H ( j f )|=

√ ( )
4
f
1+
fH
Fig. Second order Low pass Butterworth and filter with
unity gain and its transfer function

Filter Design
 Choose a value for a high cut off freq. (fH ).
 To simplify the design calculations, set R 2 = R3 = R and
C2 = C3 = C then choose a value of C<=1μf.
 Calculate the value of R R =1/2πfhC
 Finally, because of the equal resistor (R 2 = R3) and
capacitor (C2 = C3 ) values, the pass band volt gain A F = 1
+ RF / R1 of the second order had to be = to 1.586. R F =
0.586 R1. Hence choose a value of R1 <=100kΩ.
 Calculate the value of RF.

3.5.4 First order HP Butterworth filter

High pass filters are often formed simply by interchanging
frequency-determining resistors and capacitors in low-pass
filters.
(i.e) I order HPF is formed from a I order LPF by interchanging
components R & C. Similarly II order HPF is formed from a II order
LPF by interchanging R & C.
Fig. 2.57 First order HPF and its frequency response

Here I order HPF with a low cut off frequency of fL. This is the
frequency at which the magnitude of the gain is 0.707 times its
passband value. Here all the frequencies higher than f L are
passband frequencies. The output voltage V 0 of the first order
active high pass filter is

( )
V 0= 1+
Rf j2 πfRC
V
R i 1+ j 2 πfRC i
The gain of the filter

( ) ( )f
f
V0 fL
=A
( ff )
Vi
1+ j
L

Frequency response of the filter

|H ( if )|=| |=
V
0
( f )
A
f

is
L

√ )
V
(
2
i f
1+
f L

 At high frequencies f>fL gain = A.

  At f= fL gain = 0.707 A.
 At f < fL the gain decreases at a rate of -20 db /decade.
The frequency below cutoff frequency is stop band.

3.5.5 Second – order High Pass Butterworth Filter

First order Filter, II order HPF can be formed from a II order LPF
by interchanging the frequency

Fig. 2.58 Second order HPF and its frequency response

3.6 COMPARATOR
To obtain for better
performance, we shall also look at integrated designed specificall
y as comparators and converters. A comparator as its name
implies, compares a signal voltage on one input of an op-amp
with a known voltage called a reference voltage on the other
input.

Comparators are used in circuits such as,

Digital Interfacing Schmitt Trigger Discriminator Voltage level
detector and oscillators

3.6.1 Non-inverting Comparator

A fixed reference voltage Vref of 1 V is applied to the negative

terminal and time varying signal voltage V in is applied tot the
positive terminal. When Vin is less than Vref the output becomes
V0 at –Vsat [Vin < Vref => V0 (-Vsat)]. When Vin is greater than Vref,
the (+) input becomes positive, the V 0 goes to +Vsat. [Vin > Vref=>
V0 (+Vsat)]. Thus the V0 changes from one saturation level to
another. The diodes D1 and D2 protects the op-amp from damage
due to the excessive input voltage Vin. Because of these diodes,
the difference input voltage Vid of the op-amp diodes are called
clamp diodes. The resistance R in series with Vin is used to limit
the current through D1 and D2 . To reduce offset problems, a
resistance Rcomp = R is connected between the (-ve) input and
Vref.
Input and Output Waveforms
3.6.2 Inverting Comparator
This fig shows an inverting comparator in which the reference
voltage Vref is applied to the (+) input terminal and Vin is applied
to the (-) input terminal. In this circuit V ref is obtained by using a
10K potentiometer that forms a voltage divider with dc supply
volt +Vcc and -1 and the wiper connected to the input. As the
wiper is moved towards +Vcc, Vref becomes more positive. Thus
a Vref of a desired amplitude and polarity can be obtained by
simply adjusting the 10k potentiometer
3.6.3 Zero Crossing Detector [ Sine wave to Square wave
converter]
One of the application of comparator is the zero crossing
detector or ―sine wave to Square wave Converter . The basic
comparator can be used as a zero crossing detector by setting
Vref is set to Zero. (Vref =0V).

This Fig shows when in what direction an input signal V in crosses

zero volts. (i.e) the o/p V0 is driven into negative saturation when
the input the signal Vin passes through zero in positive direction.
Similarly, when Vin passes through Zero in negative direction the
output V0 switches and saturates positively.
Drawbacks of Zero- crossing detector:

In some applications, the input V in may be a slowly changing

waveform, (i.e) a low frequency signal. It will take V in more time
to cross 0V, therefore V0 may not switch quickly from one
saturation voltage to the other. Because of the noise at the op-
amp‘s input terminals the output V 0 may fluctuate between 2
saturations voltages +Vsat and –Vsat. Both of these problems can
be cured with the use of regenerative or positive feedback that
cause the output V0 to change faster and eliminate any false
output transitions due to noise signals at the input. Inverting
comparator with positive feedback . This is known as ―Schmitt
Trigger .

3.6.7 Schmitt Trigger [Square Circuit]

This circuit converts an irregular shaped waveform to a square
wave or pulse. The circuit is known as Schmitt Trigger or
squaring circuit. The input voltage V in triggers (changes the state
of) the o/p V0 every time it exceeds certain voltage levels called
the upper threshold Vut and lower threshold voltage. These
threshold voltages are obtained by using theh voltage divider R 1
– R2, where the voltage across R1 is feedback to the (+) input.
The voltage across R1 is variable reference threshold voltage that
depends on the value of the output voltage. When V 0 = +Vsat, the
voltage across R1 is called ―upper threshold voltage V ut. The
input voltage Vin must be more positive than V ut in order to
cause the output V0 to switch from +V sat to –Vsat. As long as Vin<
Vut , V0 is at +Vsat, using voltage divider rule,

V0 is at –Vsat. Vlt is given by the following eqn.

Thus, if the threshold voltages Vut and Vlt are made larger than
the input noise voltages, the positive feedback will eliminate the
false o/p transitions. Also the positive feedback, because of its
regenerative action, will make V0 switch faster between
+Vsat and –Vsat. Resistance Rcomp
R1 || R2 is used to minimize the offset problems. The comparator
with positive feedback is said texhibit hysteresis, a dead band
condition. (i.e) when the input of the comparator exceeds V ut its
output switches from +Vsat to –Vsat and reverts to its original
state, +Vsat when the input goes below Vlt. The hysteresis voltage
is equal to the difference between Vut and Vlt.

3.7 MULTIVIBRATORS

3.7.1 Astable Multivibrator

The two states of circuit are only stable for a limited time and the
circuit switches between them with the output alternating
between positive and negative saturation values.

Fig. Astable multivibrator circuit

Analysis of this circuit starts with the assumption that at

time t=0 the output has just switched to state 1, and the
transition would have occurred.
An op-amp Astable multivibrator is also called as free running
oscillator. The basic principle of generation of square wave is to
force an op-amp to operate in the saturation region (±Vsat).

A fraction β =R2/(R1+R2) of the output is feedback to the

positive input terminal of op-amp. The charge in the capacitor
increases & decreases upto a threshold value called ±βVsat. The
charge in the capacitor triggers the op-amp to stay either at
+Vsat or –Vsat.

Asymmetrical square wave can also be generated with the help

of Zener diodes. Astable multi vibrator do not require a external
trigger pulse for its operation & output toggles from one state to
another and does not contain a stable state.Astable multi
vibrator is mainly used in timing applications & waveforms
generators.

Design
 The expression of fo is obtained from the charging period
t1 & t2 of capacitor as T=2RCln (R1+2R2)/R1
 To simplify the above expression, the value of R1 & R2
should be taken as R2 = 1.16R Such that fo simplifies to fo
=1/2RC.
 Assume the value of R1 and find R2.
 Assume the value of C & Determine R from fo =1/2R C
 Calculate the threshold point from βVSATl = R1lVTl/ R1-R2
l/βVSATl w h e r e β is the feedback ratio.

3.7.2 Monostable Multivibrator using Op-amp

Circuit diagram:

Fig. 5.7 Monostable multivibrator using Op-amp

 Fig. 5.8 Input Output Waveform

A multivibrator which has only one stable and the other is quasi
stable state is called as Monostable multivibrator or one-short
multivibrator. This circuit is useful for generating signal output
pulse of adjustable time duration in response to a triggering
signal. The width of the output pulse depends only on the
external components connected to the op-amp. Usually a
negative trigger pulse is given to make the output switch to
other state. But, it then return to its stable state after a time
interval determining by circuit components. The pulse width T
can be given as T = 0.69RC. For Monostable operation the
triggering pulse width Tp should be less then T, the pulse width
of Monostable multivibrator. This circuit is also called as time
delay circuit or gating circuit.
Design:
1. Calculating β from expression
R1
β=
R1 + R2

2. The value of R and C from the pulse width time expression.

( 1+V D /V sat )
T =RCln
1−β
( 1+V D /V sat )
T =RCln
0.5
T =0.69 RC

3. Triggering pulse width T p must be much smaller than T. Tp <

T.

3.7.3 Triangular Wave Generator Circuit

Fig. 5.9 Circuit diagram of Triangular waveform generator

This signal generator gives two waveforms: a triangle-wave and
a square- wave. The central component of this circuit is the
integrator capacitor CI. Basically we are interested in performing
two functions on CI: charge it, discharge it - repeat
indefinitely. The output waveforms are shown here and it is
apparent that a square wave generator followed by an integrator
acts as a triangular wave generator.

Fig. 5.10 Output waveform from generator

Fig. 5.11 Basic triangular waveform generator

The triangle peaks and period may not accurately meet +/-10V
swing at 100 us. The main reason is that current source and
thresholds are derived from Zener diodes - not exactly the most
accurate reference.

3.7.4 Linear Ramp Generator

A triangle wave implies that the circuit generates a linear voltage

ramp. One way to achieve this goal is by charging discharging CI
with a constant current. The Op Amp Integrator provides for this.

Fig. 5.12 Linear Ramp Generator

Ramp Up
Connect RI to VN and With V- held at the virtual ground (0V), a
constant current flows from V- to VN.
Iin = VN / RI.
CI integrates Iin creating a positive linear ramp at Vo. The ramp
is linear because Vo changes proportionally to the time elapsed
ΔT.
ΔVo = - VN / (CI ∙ RI) ∙ ΔT
Ramp Down
Connect RI to VP and constant current flows from VP to V-,
Iin = - VP / RI.
Now Vo ramps down linearly ΔVo = - VP / (CI ∙ RI) ∙ ΔT
Ramp Up: ΔVo/ΔT= -VN/(CIRI)
Ramp Down: ΔVo /ΔT = - VP / ( CI∙RI )
These equations show the parameters available to control the
ramp up / down speeds. Asymmetrical voltage swings are got by
including a reference voltage VREF to the comparator's negative
input.
Vth+ =VREF∙(R1+R2)/R2-VN∙R1/R2
Vth- = VREF ∙ (R1+R2)/R2 -VP ∙ R1 / R2

Upper and Lower Bounds

When do we switch from charging to discharging CI? Basically,
there is a need to pick two levels - an upper and a lower
threshold - to define the bounds of the triangle wave. The circuit
ramps up or down, reversing at the upper and lower thresholds.
 With one leg of RI at VN, the output ramps up until
the Upper Threshold (Vth+ ) is reached. Then RI is
switched from VN to VP.
 With one leg of RI at VP, the output ramps down until
the Lower Threshold (Vth- ) is reached. Then RI is
switched from VP to VN.
Comparator:
An Op Amp Comparator with two thresholds. Produce circuit
changes in output state from VN to VP (or vice-versa) depending
on the upper Vth+ and lower Vth- thresholds.
Vth+=-VN∙R1/R2
Vth- = -VP ∙ R1 / R2

Comparator Working:
 When Vin > Vth+, the output switches to VP, the POSITIVE
output state.
 When Vin < Vth-, the output switches to VN, the NEGATIVE
output state.

Zener diodes D1 and D2 set the positive and negative output

levels:
VP=VfD1+VZD2 VN = VfD2 + VZD1.
These output levels do double duty - they set the comparator
thresholds, and set the voltage levels for the next stage - the
integrator.

3.8 WAVEFORM GENERATOR

Nonsinusoidal oscillators generate complex waveforms such as t
hose just discussed. Because the outputs of these oscillators are
generally characterized by a sudden change, or relaxation,
these oscillators are often called relaxation oscillators. The pulse
repetition rate of these oscillators is usually governed by the
charge and discharge timing of a capacitor in series with a
resistor.

However, some oscillators contain inductors that along with

circuit resistance, affect the output frequency. These RC and LC
networks within oscillator circuits are used for frequency
determination. Within this category of relaxation oscillators are
multivibrators, blocking oscillators, and sawtooth- and
trapezoidal-wave generators. Many electronic circuits are not in
an "on" condition all of the time. In computers, for example,
waveforms must be turned on and off for specific lengths of time.

The time intervals vary from tenths of microseconds to several

thousand microseconds. Square and rectangular waveforms are
normally used to turn such circuits on and off because the sharp
leading and trailing edges make them ideal for timing purposes.

3.8.1 Saw-Tooth Wave Generator

Fig.5.13 Saw-Tooth Wave Generator Circuit Diagram and output
waveform

The saw tooth wave oscillator which used the operational

amplifier. The composition of this circuit is the same as the
triangular wave oscillator basically and is using two operational
amplifiers. At the circuit diagram above, IC(1/2) is the Schmitt
circuit and IC(2/2) is the Integration circuit. The difference with
the triangular wave oscillator is to be changing the time of the
charging and the discharging of the capacitor. When the output
of IC (1/2) is positive voltage, it charges rapidly by the small
resistance (R1) value.
(When the integration output voltage falls) When the output of
IC(1/2) is negative voltage, it is made to charge gradually at the
big resistance(R2) value. The output waveform of the integration
circuit becomes a form like the tooth of the saw. Such voltage is
used for the control of the electron beam (the scanning line) of
the television, When picturing a picture at the cathode-ray tube,
an electron beam is moved comparative slow. (When the
electron beam moves from the left to the right on the screen).
When turning back, it is rapidly moved.(When moving from the
right to the left).

Like the triangular wave oscillator, the line voltage needs both of
the positive power supply and the negative power supply. Also,
to work in the oscillation, the condition of R3>R4 is necessary.
However, when making the value of R4 small compared with R3,
the output voltage becomes small. The near value is good for R3
and R4. The oscillation frequency can be calculated by the
following formula.

f=
1
( )
R3
2C ( R1 + R2 ) R 4

With the circuit diagram,the oscillation frequency is as follows.

f = (1/2C (R1+R2))*(R3/R4)
= (1/(2x0.1x10-6x(5.6x103+100x103))x(120x103/100x103)
= (1/(21.12x10-3))x1.2
= 56.8 Hz
3.9 SINE WAVE GENERATORS (Oscillators)

Sine wave oscillator circuits use phase shifting techniques that

usually employ
 Two RC tuning networks
 Complex amplitude limiting circuitry

3.9.1 RC Phase Shift Oscillator

Fig. 5.3 RC Phase Shift oscillator

RC phase shift oscillator using op-amp in inverting amplifier

introduces the phase shift of 180º between input and output. The
feedback network consists of 3 RC sections each producing 60º
phase shift. Such a RC phase shift oscillator using op-amp is
shown in the figure.
The output of amplifier is given to feedback network. The output
of feedback network drives the amplifier. The total phase shift
around a loop is 1800 of amplifier and 180 due to 3 RC
sections, thus 360 º. This satisfies the required condition for
positive feedback and circuit works as an oscillator.
 1
f oscillation =
2 π √ R 2 R3 ( C1 C 2+C 1 C 3 ) + R1 R 3 ( C 1 C2 +C 1 C 3 ) R 1 R2 C1 C2
Oscillation criterion
2 R1 R 3 C2 R2 +C 2 R3 +C 3 R3 2C 1 R1 +C 1 R2 +C 3 R 3 2C 1 R 1+2 C 2 R1 +C 1 R2 +C 2
R feedback=2 ( R 1+ R 2+ R 3 )+ + + +
R2 C1 C2 C3

The loop phase shift is –180° when the phase shift of each
section is –60°, and this occurs when ω = 2πf = 1.732/RC
because the tangent 60° = 1.73. The magnitude of β at this point
is (1/2)3, so the gain, A, must be equal to 8 for the system gain to
be equal to 1.

3.9.2 Wien Bridge Oscillator

Figure 5. 3 give the Wien-bridge circuit configuration. The loop is
broken at the positive input, and the return signal is calculated in
Equation 2 below.

Fig. 5.4 Wein Bridge Oscillator

R
V RETURN RCs+1 1 1
= = =
V OUT R
RCs+1
+ R+
1
Cs
3+ RCs+
1
RCs
3+ j RCω−
1
RCω ( )
Where
s= jω∧ j=√ 1

When ω = 2πf = 1/RC, the feedback is in phase (this is positive

feedback), and the gain is 1/3, so oscillation requires an amplifier
with a gain of 3. When RF = 2RG, the amplifier gain is 3 and
oscillation occurs at f = 1/2πRC. The circuit oscillated at 1.65 kHz
rather than 1.59 kHz with the component values shown in Figure
3, but the distortion is noticeable.

Fig. 5.5 Wein Bridge circuit schematic with non-linear feedback

Figure 4 shows a Wien-bridge circuit with non-linear feedback.

The lamp resistance, RL, is nominally selected as half the
feedback resistance, RF, at the lamp current established by RF
and RL. The non-linear relationship between the lamp current
and resistance keeps output voltage changes small.

If a voltage source is applied directly to the input of

an ideal amplifier with feedback, the input current will be:
 v ¿−v out
i ¿=
Zf

Where vin is the input voltage, vout is the output voltage,

and Zf is the feedback impedance. If the voltage gain of the
amplifier is defined as:

Input admittance:
v out
A v=
v¿

Rewritten as:
i¿
Y i=
v¿
1− A v
Y i=
Zf
From the wien bridge is written as
1
Z f =R+
jωC
( 1− A v ) ( ω 2 C 2 R+ jωC )
Y i= 2
1+ ( ωCR )

If Av is greater than 1, the input admittance is a negative

resistance in parallel with an inductance.
The inductance is:
2 2 2
ω C R +1
L¿ = 2
ω C ( A v −1 )
If a capacitor with the same value of C is placed in parallel with
the input, the circuit has a natural resonance at:
1
ω=
√T ¿ C

Substituting and solving for inductance yields:

2
R C
L¿ −
A v −2

If Av is chosen to be 3: Lin = R2C

Substituting this value yields:
1 1
ω= ∨f =
RC 2 πRC

Similarly, the input resistance at the frequency above is:

−2 R
R¿ =
A v −1
For Av = 3: Rin = − R
If a resistor is placed in parallel with the amplifier input, it will
cancel some of the negative resistance. If the net resistance is
negative, amplitude will grow until clipping occurs.

Similarly, if the net resistance is positive, oscillation amplitude

will decay. If a resistance is added in parallel with exactly the
value of R, the net resistance will be infinite and the circuit can
sustain stable oscillation at any amplitude allowed by the
amplifier.

Increasing the gain makes the net resistance more negative,

which increases amplitude. If gain is reduced to exactly 3 when
suitable amplitude is reached, stable, low distortion oscillations
will result. Amplitude stabilization circuits typically increase gain
until suitable output amplitude is reached. As long as R, C, and
the amplifier are linear, distortion will be minimal.

3.10 CLAMPER

The clamping network is one that will ―clamp a signal to a

different dc level. The network must have a capacitor, a diode,
and a resistive element, but it can also employ an independent
dc supply to introduce an additional shift. The magnitude of R
and C must be chosen such that the time constant τ= RC is large
enough to ensure that the voltage across the capacitor does not
discharge significantly during the interval the diode is non
conducting.

Throughout the analysis we will assume that for all practical

purposes the capacitor will fully charge or discharge in five-time
constants. The network of Fig. will clamp the input signal to the
zero level (for ideal diodes). The resistor R can be the load
resistor or a parallel combination of the load resistor and a
resistor designed to provide the desired level of R.
Diode ―on and the capacitor charging to V volts.

During the interval 0 → T/2 the network will appear, with the
diode in the ―on state effectively ―shorting out the effect of the
resistor R. The resulting RC time constant is so small (R
determined by the inherent resistance of the network) that the
capacitor will charge to V volts very quickly. During this interval
the output voltage is directly across the short circuit and V o =0 V.
When the input switches to the -V state, the network will appear
With an open circuit equivalent for the diode determined by the
applied signal and stored voltage across the capacitor—both
―pressuring current through the diode from cathode to anode.

Now that R is back in the network the time constant determined

by the RC product is sufficiently large to establish a discharge
period much greater than the period T/2 → T, and it can be
assumed on an approximate basis that the capacitor holds onto
all its charge and, therefore, voltage (since V = Q/C) during this
period. Since vo is in parallel with the diode and resistor, it can
also be drawn in the alternative position shown in Fig. 2.94.
Applying Kirchhoff‘s voltage law around the input loop will result
in -V – V – Vo = 0vand Vo =2V

Fig. Determining Vo with the diode ―off.

Fig. Sketching Vo for the network

The negative sign resulting from the fact that the polarity of 2V is
opposite to the polarity defined for Vo. The resulting output
waveform appears with the input signal. The output signal is
clamped to 0 V for the interval 0 to T/2 but maintains the same
total swing (2V) as the input. For a clamping network:

The total swing of the output is equal to the total swing of the
input signal.
This fact is an excellent checking tool for the result obtained. In
general, the following steps may be helpful when analyzing
clamping networks:

1. Start the analysis of clamping systems by considering that

part of the input signal that will forward bias the diode. The
statement above may require skipping an interval of the
input signal (as demonstrated in an example to follow), but
the analysis will not be extended by an unnecessary
measure of investigation.
2. During the period that the diode is in the ―on state,
assume that the capacitor will charge up instantaneously
to a voltage level determined by the network.
3. Assume that during the period when the diode is in the
―off state the capacitor will hold on to its established
voltage level.
4. Throughout the analysis maintain a continual awareness of
the location and reference polarity for to ensure that the
proper levels for are obtained.
5. Keep in mind the general rule that the total swing of the
total output must match the swing of the input signal .

1. Positive Clamper

During the negative half cycle of the input signal, the diode
conducts and acts like a short circuit. The output voltage V o 0
volts . The capacitor is charged to the peak value of input
voltage Vm. and it behaves like a battery.During the positive half
of the input signal, the diode does not conduct and acts as an
open circuit. Hence the output voltage Vo= Vm+ Vm This gives a
positively clamped voltage

2. Negative Clamper

During the positive half cycle the diode conducts and acts like a
short circuit. The capacitor charges to peak value of input
voltage Vm. During this interval the output Vo which is taken
across the short circuit will be zero During the negative half
cycle, the diode is open. The output voltage can be found by
applying KVL.
 V 0=−2V m

3.11 CLIPPER
Positive Clipper:
A circuit that removes positive parts of the input signal can be
formed by using an op-amp with a rectifier diode. T he clipping
level is determined by the reference voltage V ref, which should
less than the i/p range of the op-amp (V ref < Vin). The Output
voltage has the portions of the positive half cycles above Vref
clipped off.

The circuit works as follows:

During the positive half cycle of the input, the diode D 1 conducts
only until Vin = Vref. This happens because when V in <Vref, the
output volts V0 of the op-amp becomes negative to device D 1 into
conduction when D1 conducts it closes feedback loop and op-amp
operates as a voltage follower. (i.e.) Output V0 follows input until
Vin = Vref.

When Vin > Vref => the V0 becomes +ve to derive D1 into off. It
opens the feedback loop and op- amp operates open loop. When
Vin drops below Vref (Vin<Vref) the o/p of the op-amp V0 again
becomes –ve to device D1 into conduction. It closes the feedback
path. (o/p follows the i/p).
Thus diode D1 is on for vin<Vref (o/p follows the i/p) and D1 is off
for Vin>Vref. The op-amp alternates between open loop (off) and
closed loop operation as the D 1 is turned off and on respectively.
For this reason the op-amp used must be high speed and
preferably compensated for unity gain.

Fig.2.44 Positive Clipper

Fig. 2.45 Positive clipper input output waveform

Ex: for high speed op-amp HA 2500, LM310, μA 318. In addition
the difference input voltage (Vid=high) is high during the time
when the feedback loop is open (D 1 is off) hence an op-amp with
a high difference input voltage is necessary to prevent input
breakdown. If Rp (pot) is connected to –VEE instead of +Vcc, the
ref voltage Vref will be negative (Vref = -ve). This will cause the
entire o/p waveform above –Vref to be clipped off.

Negative Clipper:

Fig. 2.46.Negative clipper

Fig.2.47 Input output waveforms

The positive clipper is converted into a –ve clipper by simply
reversing diode D1 and changing the polarity of V ref voltage. The
negative clipper clips off the –ve parts of the input signal below
the reference voltage. Diode D1 conducts -> when Vin > -Vref and
therefore during this period o/p volt V0 follows the i/p volt Vin.
The –Ve portion of the output volt below –Vref is clipped off
because (D1 is off) Vin<-Vref. If –Vref is changed to –Vref by
connecting the potentiometer Rp to the +Vcc, the V0 below
+Vref will be clipped off. The diode D1 must be on for V in >
Vref and off for Vin.

Positive and Negative Clampers:

In clamper circuits a predetermined dc level is added to the

output voltage. (or) The output is clamped to a desired dc level.
1. If the clamped dc level is +ve, the clamper is positive
clamper
2. If the clamped dc level is –ve, the clamper is negative
clamper.

Other equivalent terms used for clamper are dc inserter or

restorer. Inverting and Non-Inverting that uses this technique.
Fig.2.48 Positive-Negative clambers

Fig.2.49 Input and output waveform with +vref

Capacitor:
The Value of the capacitors in these circuits depends on different
input rates and pulse widths.
1. In both circuits the dc level added to the o/p voltage is
approximately equal to Vcc/2.
2. This +ve fixed dc level is needed to obtain a maximum
undistorted symmetrical sine wave.
Peak clamper circuit:

Fig. 2.50 Peak clamber circuit

In this circuit, the input waveform peak is clamped at Vref. For
this reason, the circuit is called the peak clamper. First consider
the input voltage Vref at the (+) input: since this volt is +ve, V‘0
is also +ve which forward biases D 1. This closed the feedback
loop.

Voltage Vin at the (-) input: During its –ve half cycle, diode
D1 conducts, charging c; to the –ve peak value of V p. During the
+ve half cycle, diode D1 in reverse biased. Since this voltage Vp
is in series with the +ve peak volt Vp the o/p volt V0 = 2 Vp.
Thus the nett o/p is Vref plus 2 Vp. So the – ve peak of 2 Vp is at
Vref. For precision clamping, CiRd << T/2
 Fig. 2.51 Input and output waveform with -V ref

Where Rd = resistance of diode D1 when it is forward biased.

T = time period of the input waveform.
Resistor R is used to protect the op-amp against excessive
discharge currents from capacitor Ci especially when the dc
supply voltages are switched off. A +ve peak clamping is
accomplished by reversing D1 and using –ve reference voltage (-
Vref).

Note:
Inv and Non-Inv clamper – Fixed dc level
Peak clamper – Variable dc level

Applications
Wave shaping circuits are commonly used in digital computers
and communication such as TV and FM receiver. Wave shaping
technique include clipping and clamping. In op-amp clipper
circuits a rectifier diode may be used to clip off a certain portion
of the input signal to obtain a desired o/p waveform.

The diode works as an ideal diode (switch) because when on, the
voltage drop across the diode is divided by the open loop gain of
the op-amp. When off (reverse biased) the diode is an open
circuit. In an op-amp clamper circuits, however a predetermined
dc level is deliberately inserted in the o/p volt. For this reason,
the clamper is sometimes called a dc inverter.

Peak Detector
Square, Triangular, Saw tooth and pulse waves are typical
examples of non-sinusoidal waveforms. A conventional AC
voltmeter cannot be used to measure these sinusoidal
waveforms because it is designed to measure the RMS value of
the pure sine wave. One possible solution to this problem is to
measure the peak values of the non-sinusoidal waveforms. Peak
detector measures the +ve peak value of the square wave input.

Fig. 2.43 Peak detector circuit and input and output waveform
i) During the positive half cycle of Vin: the o/p of the op-amp
drives D1 on. (Forward biased) Charging capacitor C to the
positive peak value Vp of the input volt Vin.

ii) During the negative half cycle of Vin: D1 is reverse biased

and voltage across C is retained. The only discharge path for C is
through RL since the input bias IB is negligible.

For proper operation of the circuit, the charging time constant

(CRd ) and discharging time constant (CR L) must satisfy the
following condition.
CRd <= T/10
Where Rd = Resistance of the forward-biased diode. T = time
period of the input waveform.
CRL >= 10T (2)
Where RL = load resistor.

If RL is very small so that eqn. (2) cannot be satisfied.

 Use a (buffer) voltage follower circuit between capacitor C
and RL load resistor.
 R is used to protect the op-amp against the excessive
discharge currents.
 Rcomp = minimizes the offset problems caused by input
current
 D2 conducts during the –ve half cycle of Vin and prevents
the op-amp from going into negative saturation.
Note: -ve peak of the input signal can be detected simply by
reversing diode D1 and D2

3.12 HIGH SPEED SAMPLE AND HOLD CIRCUITS

Introduction:
Sample-and-hold (S/H) is an important analog building block with
many applications, including analog-to-digital converters (ADCs)
and switched-capacitor filters. The function of the S/H circuit is to
sample an analog input signal and hold this value over a certain
length of time for subsequent processing.

Taking advantages of the excellent properties of MOS capacitors

and switches, traditional switched capacitor techniques can be
used to realize different S/H circuits [1]. The simplest S/H circuit
in MOS technology is shown in Figure 1, where Vin is the input
signal, M1 is an MOS transistor operating as the sampling switch,
Ch is the hold capacitor, ck is the clock signal, and Vout is the
resulting sample-and-hold output signal.
As depicted by Figure 4. , in the simplest sense, a S/H circuit can
be achieved using only one MOS transistor and one capacitor.
The operation of this circuit is very straightforward.
Fig. 4.7 Simplest sample and hold circuits in MOS technology

Figure 4, in the simplest sense, a S/H circuit can be achieved

using only one MOS transistor and one capacitor. The operation
of this circuit is very straightforward. Whenever ck is high, the
MOS switch is on, which in turn allows Vout to track Vin. On the
other hand, when ck is low, the MOS switch is off. During this
time, Ch will keep Vout equal to the value of Vin at the instance
when ck goes low.

Unfortunately, in reality, the performance of this S/H circuit is not

as ideal as described above. The two major types of errors occur.
They are charge injection and clock feed through, that are
associated with this S/H implementation. Three new S/H
techniques, all of which try to minimize the errors caused by
charge injection and/or clock feed through.

Series Sampling:
The S/H circuit of Figure 4. is classified as parallel sampling
because the hold capacitor is in parallel with the signal. In
parallel sampling, the input and the output are dc-coupled. On
the other hand, the S/H circuit shown in Figure 2 is referred to as
series sampling because the hold capacitor is in series with the
signal.
Fig. 4.8 Series sampling

When the circuit is in sample mode, both switches S2 and S3 are

on, while S1 is off. Then,S2 is turned off first, which means Vout is
equal to VCC (or VDD for most circuits) and the voltage drop
across Ch will be VCC – Vin. Subsequently, S3 is turned off
and S1 is turned on simultaneously. By grounding node X, Vout is
now equal to VCC –Vin, and the drop from VCC to VCC – Vin is equal
to the instantaneous value of the input.

As a result, this is actually an inverted S/H circuit, which requires

inversion of the signal at a later stage. Since the hold capacitor is
in series with the signal, series sampling can isolate the
common- mode levels of the input and the output.
This is one advantage of series sampling over parallel sampling.
In addition, unlike parallel sampling, which suffers from signal-
dependent charge injection, series sampling does not exhibit
such behavior because S2 is turned off before S3. Thus, the fact
that the gate-to-source voltage, VGS, of S2 is constant means that
charge injection coming from S2 is also constant (as opposed to
being signal-dependent), which means this error can be easily
eliminated through differential operation.

Limitations:
On the other hand, series sampling suffers from the nonlinearity
of the parasitic capacitance at node Y. This parasitic capacitance
introduces distortion to the sample-and hold value,
thus mandating that Ch be much larger than the parasitic
capacitance. On top of this disadvantage, the settling time of the
S/H circuit during hold mode is longer for series sampling than
for parallel sampling. The reason for this is because the value
of Vout in series sampling is being reset to VCC (or VDD) for
every sample, but this is not the case for parallel sampling.

Switched Op-Amp Based Sample-and-Hold Circuit:

This S/H technique takes advantage of the fact that when a MOS
transistor is in the saturation region, the channel is pinched off
and disconnected from the drain. Therefore, if the hold capacitor
is connected to the drain of the MOS transistor, charge injection
will only go to the source junction, leaving the drain unaffected.
Based on this concept, a switched op- amp (SOP) based S/H
circuit, as shown in Figure 4.9
Fig. 4.9 Switched op-amp based sample and hold circuit

During sample mode, the SOP behaves just like a regular op-
amp, in which the value of the output follows the value of the
input. During hold mode, the MOS transistors at the output node
of the SOP are turned off while they are still operating in
saturation, thus preventing any channel charge from flowing into
the output of the SOP. In addition, the SOP is shut off and its
output is held at high impedance, allowing the charge on Ch to
be preserved throughout the hold mode. On the other hand, the
output buffer of this S/H circuit is always operational during
sample and hold mode and is always providing the voltage
on Ch to the output of the S/H circuit.

S/H circuits that operate in closed loop configuration can achieve

high resolution, but their requirements for high gain circuit block,
such as an op-amp, limits the speed of the circuits. As a result,
better and faster S/H circuits must be developed.

Fig. 4.10. High speed Sample and Hold circuit with MOSFET
The above figure shows a sample and holds circuit with MOSFET
as Switch acting as a sampling device and also consists of a
holding capacitor Cs to store the sample values until the next
sample comes in. This is a high speed circuit as it is apparent
that CMOS switch has a very negligible propagation delay.
Three S/H circuits to reduce error
 Series sampling
 SOP based S/H circuit
 Bottom plate S/H circuit with bootstrapped switch
3.13 DIGITAL TO ANALOG CONVERTER(DAC)

The process of converting digital signal into equivalent analog

signal is called D/A conversion. The electronics circuit, which
does this process, is called D/A converter. The circuit has „n’
number of digital data inputs with only one output. Basically,
there are two types of D/A converter circuits: Weighted resistors
D/A converter circuit and Binary ladder or R–2R ladder D/A
converter circuit.

3.13.1 Weighted resistors D/A converter

Here an OPAMP is used as summing amplifier. There are four

resistors R, 2R, 4R and 8R at the input terminals of the OPAMP
with R as feedback resistor. The network of resistors at the input
terminal of OPAMP is called as variable resistor network. The four
inputs of the circuit are D, C, B & A. Input D is at MSB and A is at
LSB. Here we shall connect 8V DC voltage as logic–1 level. So we
shall assume that 0 = 0V and 1 = 8V.

Fig.Weighted resistors D/A converter

Now the working of the circuit is as follows. Since the circuit is

summing amplifier, its output is given by the following equation

v 0=R ( DR + 2CR + 4BR + 8AR )

Working of the circuit

When input DCBA = 0000, then putting these value in above

equation (1) we get

v 0=R ( R0 + 20R + 40R + 80R )=0 V

When digital input of the circuit DCBA = 0001, then putting these
value in above equation (1) we get

v 0=R ( R0 + 20R + 40R + 80R )=0 V

When digital input of the circuit DCBA = 0010, then putting these
value in above equation (1) we get

v 0=R ( R0 + 20R + 40R + 80R )=−R 84 VR =−2V

…………… so on.

In this way, when digital input changes from 0000 to 1111 (in
BCD style), output voltage (Vo) changes proportionally. This is
given in the conversion chart. There are some main
disadvantages of the circuit.

They are
1) Each resistor in the circuit has different value.
2) So error in value of each resistor adds up.
3) The value of resistor at MSB is the lowest. Hence, it draws
more current.
4) Also, its heat & power dissipation is very high.
5) There is the problem of impedance matching due to different
values of resistors.

3.13.2 R–2R Ladder D/A Converter

It is modern type of resistor network. It has only two values of

resistors the R and 2R. These values repeat throughout in the
circuit. The OPAMP is used at output for scaling the output
voltage. The working of the circuit can be understood as follows.
For simplicity, we ignore the OPAMP in the above circuit (this is
because its gain is unity). Now consider the circuit, without
OPAMP. Suppose the digital input is DCBA = 1000. Then the
circuit is reduced to a small circuit.

( 2 R2+2R R ) X (+ V )= V2
output =

Reduced circuit of R-2R ladder, when we consider that all

inputs=0

Now suppose digital input of the same circuit is changed to DCBA

= 0100. Then the output voltage will be V/4, when DCBA = 0010,
output voltage will be V/8, for DCBA = 0001, output voltage will
be V/16 and so on. The general formula for the above circuit of
R–2R ladder, including the OPAMP also, will be

v 0=−R ( 2DR + 4CR + 8BR + 16AR )

You can take (R) common from the above formula and simplify it.
With the help of this formula, we can calculate any combination
of digital input into its equivalent analog voltage at the output
terminals.

A to D Converter- Specifications

Like DAC, ADCs are also having many important specifications.

Some of them are Resolution, Quantization error, Conversion
time, Analog error, Linearity error, DNL error, INL error & Input
voltage range.

Resolution:
The resolution refers to the finest minimum change in the signal
which is accepted for conversion, and it is decided with respect
to number of bits. It is given as 1/2 n, where ‘n’ is the number of
bits in the digital output word. As it is clear, that the resolution
can be improved by increasing the number of bits or the number
of bits representing the given analog input voltage.
Resolution can also be defined as the ratio of change in the value
of input voltage Vi, needed to change the digital output by 1 LSB.
It is given as
Resolution = ViFS / (2n – 1)
Where ‘ViFS’ is the full-scale input voltage.
‘n’ is the number of output bits.

Quantization error:
If the binary output bit combination is such that for all the values
of input voltage Vi between any two voltage levels, there is a
unavoidable uncertainty about the exact value of Vi when the
output is a particular binary combination. This uncertainty is
termed as quantization error. Its value is ± (1/2) LSB. And it is
given as,
QE = ViFS / 2(2n – 1)
Where ‘ViFS’ is the full-scale input voltage. ‘n’ is the number of
output bits. Maximum the number of bits selected, finer the
resolution and smaller the quantization error.

Conversion Time:
It is defined as the total time required for an A/D converter to
convert an analog signal to digital output. It depends on the
conversion technique and propagation delay of the circuit
components.
Analog error:
An error occurring due to the variations in DC switching point of
the comparator, resistors, reference voltage source, ripples and
noises introduced by the circuit components is termed as Analog
error.

Linearity Error:
It is defined as the measure of variation in voltage step size. It
indicates the difference between the transitions for a minimum
step of input voltage change. This is normally specified as
fraction of LSB.

Differential Non-Linearity(DNL) Error:

The analog input levels that trigger any two successive output
codes should differ by 1 LSB. Any deviation from this 1 LSB value
is called as DNL error.

Integral Non-Linearity (INL) Error:

The deviation of characteristics of an ADC due to missing codes
causes INL error. The maximum deviation of the code from its
ideal value after nulling the offset and gain errors is called as
Integral Non-Linearity Error.

Input Voltage Range:

It is the range of voltage that an A/D converter can accept as its
input without causing any overflow in its digital output.
Analog Switches
There were two types of analog switches. Series and Shunt
switch. The Switch operation is shown for both the cases VGS=0
VGS= VGs (off)

Fig. 4.13 Series and shunt Analog switches