C.K.PITHAWALA COLLEGE OF ENGG. & TECH. ,SURAT.

B.E.- I YEAR
Subject Name: Basic Electronics
Subject Code: 3110016

Chapter 6: Field effect transistors

 The bipolar junction transistor (BJT) relies on two types of charge: free electrons
and holes. This is why it is called bipolar: the prefix bi stands for “two.” Another
kind of transistor called the field-effect transistor (FET) is unipolar because its
operation depends on only one type of charge, either free electrons or holes. In
other words, an FET has majority carriers but not minority carriers.
 Furthermore, the FET is the preferred device for most switching applications
because there are no minority carriers in an FET. As a result, it can switch off
faster since no stored charge has to be removed from the junction area.
 There are two kinds of unipolar transistors: JFETs and MOSFETs.
1. Construction of JFET
 The junction field effect transistor is generally classified into two types based on
their polarities and they are:
• N-Channel junction field effect transistor
• P-Channel junction field effect transistor
 A JFET consists of a p-type or n-type silicon bar containing two PN junctions at
the sides as shown in Fig.1.
 The bar forms the conducting channel for the charge carriers.
 If the bar is of N-type, it is called N-channel JFET as shown in Fig. 1 (i) and if the
bar is of P-type, it is called a P-channel JFET as shown in Fig. 1 (ii).
 The top of the N -type or P-Type channel is connected through an ohmic contact to
a terminal referred to as the drain (D), while the lower end of the same material is
connected through an ohmic contact to a terminal referred to as the source (S).
 The two PN juctions are connected together and a common terminal called gate is
taken out.
  In the absence of any applied potentials the JFET has two p-n junctions under no-
bias conditions. The result is a depletion region at each junction. Recall that a
depletion region is that region void of free carriers and therefore unable to support
conduction through the region.

Figure-1

2. Schematic Symbol of JFET

Figure-2
 3. Working of JFET OR Drain Characteristic of JFET
JFET operation can be compared to a water spigot.

The source of water pressure is the accumulation of electrons at the negative pole of
the drain-source voltage.
The drain of water is the electron deficiency (or holes) at the positive pole of the
applied voltage.
The control of flow of water is the gate voltage that controls the width of the n-channel
and, therefore, the flow of charges from source to drain.

Let us consider the working of an n channel JFET transistor.

 Case 1: VGS = 0, VDS > 0

 At the drain terminal, voltage VDS is some positive voltage greater than zero. But
the source terminal is at ground 0V.
 The positive potential of VDS attracts electrons from the channel towards the
source. The conventional current ID flows from the drain to the source.
 The width of the depletion region increases towards the drain terminal.
 The depletion region towards the source terminal is narrower than the above
layers.
 The gate-to-source terminal is at a lower potential compared to the drain-to-
source bias. It implies that the PN junction at the gate terminal is reversed
biased.
 Pinch off voltage: As VDS increases, the depletion region starts to get bigger
 near the drain terminal. When drain-to-source voltage VDS reaches the pinch-off
voltage VP, it appears that both the depletion layers would adjoin. However, the
depletion regions never touch due to electrostatic repulsion and allow current
flow.
 The current ID increases with increasing VDS until the pinch-off point. The current
ID reaches saturation to become constant and does not increase with increasing
VDS . The drain current at the pinch-off point is termed IDSS. The JFET acts as a
constant current source beyond pinch-off voltage VP.

(i) (ii)

Figure-3 (i) VGS = 0, VDS > 0 (ii) VGS = 0, VDS =Vp

Case 2: VGS < 0, VDS > 0

Figure-4 VGS < 0, VDS > 0

 A negative voltage of -1 V has been applied between the gate and source terminals
for a low level of VDS.
 The effect of the applied negative-bias VGS is to establish depletion regions similar to
those obtained with VGS= 0 V but at lower levels of VDS.
 Therefore, the result of applying a negative bias to the gate is to reach the saturation
level at a lower level of VDS.
 The resulting saturation level for ID has been reduced and in fact will continue to
decrease as VGS is made more and more negative.
 Note that the pinchoff voltage continues to drop in a parabolic manner as V GS
becomes more and more negative.
 Eventually, when VGS= -VP will be sufficiently negative to establish a saturation level
that is essentially 0 mA, and for all practical purposes the device has been “turned
off.”
Figure -5 Drain curves for N channel JFET

4. Transfer Characteristics OR Transconductance curve of JFET:

 Transfer Characteristics of JFET are a plot of ID versus VGS.
 The gate-source voltage of a FET controls the level of the drain current, so, the
transfer characteristic shows how ID is controlled by VGS.
 The transfer characteristic extends from ID = IDSS at VGS = 0, to ID = 0 at VGS = Vp.
 Figure 5.6 shows a circuit for experimentally determining a table of quantities for
plotting the transfer characteristic of a given FET. The drain-source voltage is
maintained constant, VGS is adjusted in convenient step, and the corresponding
levels of VGS and ID are recorded. The characteristic shows that, as -VGS is
increased, ID is progressively reduced from IDSS at VGS = 0, to ID = 0 at VGS = -Vp
 The transfer characteristic for a FET can be derived from the drain characteristics. A
line is drawn vertically on the drain characteristics to represent a constant VDS level.
The corresponding ID and VGS values along this line are noted and then used to plot
the transfer characteristic.

Figure -6 Circuit to determine Transfer characteristic of N channel JFET

Figure -7 Transfer characteristic of N channel JFET
5. Difference between BJT and FET
Bipolar Junction Transistor (BJT) Field Effect Transistor (FET)
Bipolar device. Unipolar device.
In BJT, the operation is depends upon both In FET, the operation is depends upon the flow of
minority and majority current carriers. Thus it is majority carriers only i.e. holes for P-Channel FET
known as Bipolar device. and electrons for N-Channel FET. Therefore they
are called as Unipolar devices.
Lower switching speed. Higher switching speed
BJT suffers from minority carrier storage effects. FET does not suffer from minority carrier storage
So it has lower switching speed and cut off effects. So it has higher switching speed and cut
frequencies. off frequencies.
Current controlled device. Voltage controlled device.
In BJT, the base current controls the output In FET, the Gate voltage controls the output
current. current.
Less input impedance. High input impedance
The input circuit of BJT is forward biased. So BJT The input circuit of FET is reverse biased. So FET
has low input impedance. exhibits much higher input impedance
(>100Mohms) and lower output impedance. As
they have high degree of isolation between input
and output, FET acts as a buffer amplifier.
Comparatively BJT has more noisy operation. Less noisy
FET doesn’t have junctions and the current
conduction is happening through N-type or P-
type semiconductor material. So its operation is
less noisy.
Relatively more affected by radiations Less affected.
Due to reduction in minority carrier lifetime, the As FET operation does not depends upon the
performance of BJT is degraded by neutron minority carriers, they can tolerate much higher
radiation. level of radiation.
Lesser thermal stability. More thermal stability.
BJT has a positive temperature coefficient at high FET has a negative temperature coefficient at
current levels. It leads to thermal breakdown. high current levels. It prevents the FET from
thermal breakdown issue.
In IC fabrication, BJTs are occupying more space. FETs are easier to fabricate and occupying less
space.
BJTs are cheaper to produce. Comparatively FETs are more costly.
6. Transconductance

 Transconductance is the ratio of change in drain current (δID) to change in the gate to
source voltage (δVGS) at a constant drain to source voltage (VDS = Constant).

 This value is maximum at VGS = 0. This is denoted by gmo. This maximum value (gmo)
is specified in a JFET data sheet. The transconductance at any other value of gate to
source voltage (gm) can be determined as follows. The expression of drain current (ID)
is

 By partial differentiating the expression of drain current (ID) in respect of gate to

source voltage (VGS)

 At VGS = 0, the transconductance gets its maximum value and that is

 Therefore, we can write,

7. JFET Amplifier
 Figure-5.12a shows a common-source (CS) amplifier. The coupling and bypass
capacitors are ac shorts. Because of this, the signal is coupled directly into the gate.
Since the source is bypassed to ground, all of the ac input voltage appears between
the gate and the source.
 The amplifier circuit consists of an N-channel JFET. The JFET gate voltage Vg is
biased through the potential divider network set up by resistors R1 and R2 and is
biased to operate within its saturation region which is equivalent to the active
 region of the bipolar junction transistor.

Figure-8 (a) CS amplifier; (b) ac-equivalent circuit

 Any suitable pair of resistor values in the correct proportions would produce the
correct biasing voltage so the DC gate biasing voltage Vg is given as:

 Note that this equation only determines the ratio of the resistors R1 and R2, but in
order to take advantage of the very high input impedance of the JFET as well as
reducing the power dissipation within the circuit, we need to make these resistor
values as high as possible, with values in the order of 1MΩ to 10MΩ being
common.
 The input signal, (Vin) of the common source JFET amplifier is applied between
the Gate terminal and the zero volts rail, (0v). With a constant value of gate voltage
Vg applied the JFET operates within its “Ohmic region” acting like a linear resistive
device. The drain circuit contains the load resistor, Rd. The output voltage, Vout is
developed across this load resistance.
  As with the common emitter bipolar circuit, the DC load line for the common source
JFET amplifier produces a straight line equation whose gradient is given as: -1/(Rd +
Rs) and that it crosses the vertical Id axis at point A equal to VDD/(Rd + Rs). The
other end of the load line crosses the horizontal axis at point B which is equal to the
supply voltage, VDD.

 The actual position of the Q-point on the DC load line is generally positioned at the
mid center point of the load line (for class-A operation) and is determined by the
mean value of Vg which is biased negatively as the JFET is a depletion-mode device.
Like the bipolar common emitter amplifier the output of the Common Source JFET
Amplifier is 180o out of phase with the input signal.

 FETs have a few disadvantages like high drain resistance, moderate input impedance
and slower operation. To overcome these disadvantages, the MOSFET which is an
advanced FET is invented.

8. The JFET Analog Switch

 In this application, the JFET acts as a switch that either transmits or blocks a small
ac signal. To get this type of action, the gate-source voltage VGS has only two
values: either zero or a value that is greater than VGS(off). In this way, the JFET
operates either in the ohmic region or in the cutoff region.
Shunt Switch
 Figure-9a shows a JFET shunt switch. The JFET is either conducting or cut off,
depending on whether VGS is high or low. When VGS is high (0 V), the JFET
operates in the ohmic region. When VGS is low, the JFET is cut off. Because of
this, we can use Figure-9b as an equivalent circuit.

Figure-9 JFET analog switches: (a) Shunt type; (b) shunt-equivalent circuit; (c) series type; (d)
series-equivalent circuit

 For normal operation, the ac input voltage must be a small signal, typically less
than 100 mV. A small signal ensures that the JFET remains in the ohmic region
when the ac signal reaches its positive peak. Also, RD is much greater than RDS to
ensure hard saturation: RD ˃˃ RDS
 When VGS is high, the JFET operates in the ohmic region and the switch of Figure-
9b is closed. Since RDS is much smaller than RD, Vout is much smaller than Vin.
When VGS is low, the JFET cuts off and the switch of Figure-9b opens. In this case,
Vout = Vin. Therefore, the JFET shunt switch either transmits the ac signal or
blocks it.
Series Switch
 Figure-9c shows a JFET series switch, and Figure-9d is its equivalent circuit.
When VGS is high, the switch is closed and the JFET is equivalent to a resistance of
RDS.
  In this case, the output approximately equals the input. When VGS is low, the JFET
is open and Vout is approximately zero. The on-off ratio of a switch is defined as
the maximum output voltage divided by the minimum output voltage:
𝒗𝒐𝒖𝒕 (𝒎𝒂𝒙)
𝑶𝒏 − 𝑶𝒇𝒇 𝑹𝒂𝒕𝒊𝒐 =
𝒗𝒐𝒖𝒕 (𝒎𝒊𝒏)
 When a high on-off ratio is important, the JFET series switch is a better choice
because its on-off ratio is higher than that of the JFET shunt switch.
9. MOSFETs
 The metal-oxide semiconductor FET, or MOSFET, has a source, gate, and drain.
The MOSFET differs from the JFET, however, in that the gate is insulated from
the channel. Because of this, the gate current is even smaller than it is in a JFET.
 There are two kinds of MOSFETs, the depletion-mode type and the enhancement-
mode type. The enhancement-mode MOSFET is widely used in both discrete and
integrated circuits.
 In discrete circuits, the main use is in power switching, which means turning large
currents on and off. In integrated circuits, the main use is in digital switching, the
basic process behind modern computers. Although their use has declined, depletion
mode MOSFETs are still found in high-frequency front-end communications
circuits as RF amplifiers.

10. The Depletion-Mode MOSFET

 Figure-19.43 shows a depletion-mode MOSFET, a piece of n material with an
insulated gate on the left and a p region on the right. The p region is called the
substrate.

Figure-19.43 Depletion-mode MOSFET

 Electrons flowing from source to drain must pass through the narrow channel
between the gate and the p substrate. A thin layer of silicon dioxide (SiO2) is
deposited on the left side of the channel.
 Silicon dioxide is the same as glass, which is an insulator. In a MOSFET, the gate
is metallic. Because the metallic gate is insulated from the channel, negligible gate
current flows even when the gate voltage is positive.
 Construction of D-MOSFET:

Working of D-MOSFET:
 Figure-19.47 shows a depletion-mode MOSFET with a negative gate voltage. The
VDD supply forces free electrons to flow from source to drain. These electrons flow
through the narrow channel on the left of the p substrate.
 As with a JFET, the gate voltage controls the width of the channel. The more
negative the gate voltage, the smaller the drain current. When the gate voltage is
negative enough, the drain current is cut off. Therefore, the operation of a
depletion-mode
 MOSFET is similar to that of a JFET when VGS is negative. Since the gate is
insulated, we can also use a positive input voltage, as shown in Figure-5.15b.
 The positive gate voltage increases the number of free electrons flowing through
the channel. The more positive the gate voltage, the greater the conduction from
source to drain.
Figure- (a) 19.47: D-MOSFET with negative gate; (b) 19.48: D-MOSFET with positive gate
  There is also a p-channel D-MOSFET. It consists of a drain-to-source p-channel,
along with an n- type substrate. Once again, the gate is insulated from the channel.
 The action of a p-channel MOSFET is complementary to the n-channel MOSFET.
The schematic symbols for both n-channel and p-channel D-MOSFETs are shown
in Figure-10.

Figure-10 D-MOSFET schematic symbols: (a) n-channel; (b) p-channel

11. The Enhancement-Mode MOSFET

 The depletion-mode MOSFET was part of the evolution toward the enhancement
mode MOSFET, abbreviated E-MOSFET. Without the E-MOSFET, the personal
computers that are now so widespread would not exist.
Construction:
 Figure 11 shows the construction of a metal oxide semiconductor FET (MOSFET).
 Starting with a high-resistive p-type substrate, two blocks of heavily-doped n-type
material are diffused into the substrate, and then the surface is coated with a layer of
silicon dioxide. Holes are cut through the silicon dioxide to make contact with the n-
type blocks.
 Metal is deposited through the holes for source and drain terminals, as illustrated, and
a metal plate is deposited on the surface area between drain and source. This plate
functions as a gate.
 Figure – 11 MOSFET Construction
E-MOSFET Working:
 Consider the situation illustrated in Fig. 12a. The drain terminal of the MOSFET is
positive with respect to the source, and the gate is open-circuited.
 The two n-type blocks and the p-type substrate form back-to-back pn-junctions
connected by the resistance of the p-type material, as illustrated.
 The pn-junction close to the drain terminal is reverse biased, so that only a very small
(reverse-leakage) current flows from D to S.
 Now assume that the source terminal is connected to the substrate and that a positive
gate voltage is applied, as shown in Fig. 12b.
 Negative (minority) charge carriers within the substrate are attracted to the (positive)
plate that constitutes the gate. Since these charge carriers (electrons) cannot cross
the silicon dioxide to the gate, they accumulate close to the surface of the substrate,
as shown.

Figure - 12
 The minority charge carriers constitute an n-type channel between drain and source,
and as the gate-source voltage is made more positive, more electrons are attracted
into the channel, causing the channel resistance to decrease.
 A drain current flows along the channel between the D and S terminals, and because
the channel resistance is controlled by the gate-source voltage (Vgs), the drain
current is also controlled by Vgs.
 The channel conductivity is said to be enhanced by the positive gate-source voltage,
and so the device is known as an Enhancment MOSFET (EMOSFET or EMOS
transistor).
 The minimum VGS that creates channel is called the threshold voltage, symbolized
by VGS(th). When VGS is less than VGS(th), the drain current is zero.
 With zero gate voltage, a JFET is on, whereas an E-MOSFET is off. Therefore,
the E-MOSFET is considered to be a normally off device.
 Typical drain and transfer characteristics for an n-channel EMOS device are shown
in figure below. Note that on both characteristics the drain current increases as the
positive gate-source bias voltage is increased.
 Because the gate of the MOSFET is insulated from the channel, there is no gate-
source leakage current and the device has an extremely high (gate) input resistance:
typically 10° © or greater.

Figure: 13 Transfer characteristic and Drain curve for E-MOSFET

 Symbol:
 Two graphic symbols for the n-channel EMOS transistor are shown below.

Figure: 14
 One symbol shows the source and substrate connected internally, while the other
has a separate substrate terminal.
 The line representing the device channel is broken into three sections to indicate
that the channel does not exist until an appropriate gate voltage is applied.
 To show that the device has an insulated gate, the gate symbol does not make
direct contact with the channel.
 The arrowhead points from the p-type substrate to the n-type channel.

A p-channel EMOS transistor is constructed by starting with an n-type substrate and

diffusing p-type drain and source blocks, as illustrated in figure below. The device
characteristics are similar to those in n-channel EMOS, except that all voltage
polarities and current directions are reversed. The drain-source voltage is negative,
and a negative gate-source voltage is required to create the p-type channel. The
arrowheads in the circuit symbols are also reversed.

Figure: 15
Comparison between BJT, FET and MOSFET

TERMS BJT FET MOSFET

Device type Current controlled Voltage controlled Voltage Controlled
Current flow Bipolar Unipolar Unipolar
Terminals Not Interchangeable Interchangeable
interchangeable

Operational No modes Depletion mode Both Enhancement and

modes only Depletion modes
Input impedance Low High Very high
Output Moderate Moderate Low
resistance

Operational Low Moderate High

speed

Noise High Low Low

Thermal stability Low Better High

12. VMOSFET
 Figure 16a shows a device referred to as a VMOSFET because of its V-shaped
configuration, and because it uses a vertical channel between drain
and source.
 The V-cut penetrates from the surface of the device through n+, p, and n- layers
almost to the n+ substrate.
 The n+ layers are low-resistive, and the n- is a high-resistive region.
 The silicon dioxide layer covers both the horizontal surface and the V-cut
surface. The gate is a metal film deposited on the silicon dioxide surface in the
V-cut.
 The drain terminal is at the bottom of the n+ substrate, and the source connection
is made to the top n+ region and to the p region.
 Figure: 16 VMOSFET construction and operation. The vertical channel gives an
improved frequency response, lower channel resistance, and greater power dissipation
than other FETs.

 The VMOSFET operates in the enhancement mode; no channel exists until a

positive gate source voltage is applied.
 An n-type channel is created as shown in Fig. 16b when Vs is made positive and
a current flows vertically from drain to source.
 Some versions of VMOSFETs use a vertical channel but do not use the V-cut.
 Typical VMOSFET drain and transfer characteristics are shown in Fig. 17. It
can be seen that they are similar to the enhancement-mode device
characteristics, although much higher drain current levels are usually involved
with a VMOSFET than with other MOSFETs.
Figure: 17 Typical transfer and drain characteristics for a VMOSFET.