RF Power Field Effect Transistors: MRFE6VP61K25HR6 MRFE6VP61K25HSR6
RF Power Field Effect Transistors: MRFE6VP61K25HR6 MRFE6VP61K25HSR6
RF Power Field Effect Transistors: MRFE6VP61K25HR6 MRFE6VP61K25HSR6
MRFE6VP61K25HR6 MRFE6VP61K25HSR6
1.8-600 MHz, 1250 W CW, 50 V LATERAL N-CHANNEL BROADBAND RF POWER MOSFETs
Capable of Handling a Load Mismatch of 65:1 VSWR, @ 50 Vdc, 230 MHz, at all Phase Angles, Designed for Enhanced Ruggedness, 1250 Watts Pulsed Peak Power, 20% Duty Cycle, 100 sec Capable of 1250 Watts CW Operation Features Unmatched Input and Output Allowing Wide Frequency Range Utilization Device can be used Single--Ended or in a Push--Pull Configuration Qualified Up to a Maximum of 50 VDD Operation Characterized from 30 V to 50 V for Extended Power Range Suitable for Linear Application with Appropriate Biasing Integrated ESD Protection with Greater Negative Gate--Source Voltage Range for Improved Class C Operation Characterized with Series Equivalent Large--Signal Impedance Parameters RoHS Compliant In Tape and Reel. R6 Suffix = 150 Units, 56 mm Tape Width, 13 inch Reel. For R5 Tape and Reel options, see p. 12. Table 1. Maximum Ratings
Rating Drain--Source Voltage Gate--Source Voltage Storage Temperature Range Case Operating Temperature Total Device Dissipation @ TC = 25C Derate above 25C Operating Junction Temperature (1,2) Symbol VDSS VGS Tstg TC PD TJ Value --0.5, +125 --6.0, +10 -- 65 to +150 150 1333 6.67 225 Unit Vdc Vdc C C W W/C C
RFin/VGS 3
1 RFout/VDS
RFin/VGS 4
2 RFout/VDS
(Top View)
1. Continuous use at maximum temperature will affect MTTF. 2. MTTF calculator available at http://www.freescale.com/rf. Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. 3. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf. Select Documentation/Application Notes -- AN1955.
MRFE6VP61K25HR6 MRFE6VP61K25HSR6 1
Min 125
Typ
Max 1 10 20
Unit
Gate--Source Leakage Current (VGS = 5 Vdc, VDS = 0 Vdc) Drain--Source Breakdown Voltage (VGS = 0 Vdc, ID = 100 mA) Zero Gate Voltage Drain Leakage Current (VDS = 50 Vdc, VGS = 0 Vdc) Zero Gate Voltage Drain Leakage Current (VDS = 100 Vdc, VGS = 0 Vdc) On Characteristics Gate Threshold Voltage (1) (VDS = 10 Vdc, ID = 1776 Adc) Gate Quiescent Voltage (VDD = 50 Vdc, ID = 100 mAdc, Measured in Functional Test) Drain--Source On--Voltage (1) (VGS = 10 Vdc, ID = 2 Adc) Dynamic Characteristics (1) Reverse Transfer Capacitance (VDS = 50 Vdc 30 mV(rms)ac @ 1 MHz, VGS = 0 Vdc) Output Capacitance (VDS = 50 Vdc 30 mV(rms)ac @ 1 MHz, VGS = 0 Vdc) Input Capacitance (VDS = 50 Vdc, VGS = 0 Vdc 30 mV(rms)ac @ 1 MHz)
1.7 1.4
2.7 2.9
pF pF pF
Functional Tests (In Freescale Test Fixture, 50 ohm system) VDD = 50 Vdc, IDQ = 100 mA, Pout = 1250 W Peak (250 W Avg.), f = 230 MHz, Pulsed, 100 sec Pulse Width, 20% Duty Cycle Power Gain Drain Efficiency Input Return Loss Gps D IRL 23.0 72.5 24.0 74.0 --14 26.0 --10 dB % dB
Pulsed RF Performance (In Freescale Application Test Fixture, 50 ohm system) VDD = 50 Vdc, IDQ = 100 mA, Pout = 1250 W Peak (250 W Avg.), f = 230 MHz, Pulsed, 100 sec Pulse Width, 20% Duty Cycle Load Mismatch (VSWR 65:1 at all Phase Angles) 1. Each side of device measured separately. No Degradation in Output Power
VBIAS
COAX1
Z3 RF INPUT Z1 Z2 C1 Z4 C3 C2
Z5
Z7
Z9
L1
Z13
Z6
C4 Z8
C5 Z10
L2
Z14
Z12
COAX2 VBIAS
R2 + C6 C7 C8 C9
+ C23
+ C24
VSUPPLY
DUT
C14
C15
Z16
Z24
Z28
COAX4
+ C25 C26
+ C27
+ C28
VSUPPLY
0.192 x 0.082 Microstrip 0.175 x 0.082 Microstrip 0.170 x 0.100 Microstrip 0.116 x 0.285 Microstrip 0.116 x 0.285 Microstrip 0.108 x 0.285 Microstrip
Z11*, Z12* Z13, Z14 Z15, Z16 Z17*, Z18* Z19*, Z20* Z21, Z22
0.872 x 0.058 Microstrip 0.412 x 0.726 Microstrip 0.371 x 0.507 Microstrip 0.466 x 0.363 Microstrip 1.187 x 0.154 Microstrip 0.104 x 0.507 Microstrip
1.251 x 0.300 Microstrip 0.127 x 0.300 Microstrip 0.116 x 0.300 Microstrip 0.186 x 0.082 Microstrip 0.179 x 0.082 Microstrip
C10
C11 C12
C13
C22
C23
C1
C3
C18 C19
COAX2
R2
L4 COAX4 C25
C6
C7 C8
--
C27
---
--
C24
C20
C28
TYPICAL CHARACTERISTICS
2000 Pout, OUTPUT POWER (dBm) PULSED 1000 Ciss 66 65 64 63 62 61 60 59 35 VDD = 50 Vdc, IDQ = 100 mA, f = 230 MHz Pulse Width = 100 sec, 20% Duty Cycle 36 37 38 39 40 41 42 P3dB = 61.9 dBm (1553 W) P2dB = 61.7 dBm (1472 W) Ideal
C, CAPACITANCE (pF)
100
Coss
10 Crss 1 Measured with 30 mV(rms)ac @ 1 MHz VGS = 0 Vdc 0 10 20 30 40 50 VDS, DRAIN--SOURCE VOLTAGE (VOLTS)
Note: Each side of device measured separately. Figure 4. Capacitance versus Drain-Source Voltage
26 25 Gps, POWER GAIN (dB) 24 23 Gps 22 21 D 20 100 1000 Pout, OUTPUT POWER (WATTS) PULSED 30 2000 50 40 VDD = 50 Vdc, IDQ = 100 mA, f = 230 MHz Pulse Width = 100 sec, 20% Duty Cycle 90 80 D, DRAIN EFFICIENCY (%) Gps, POWER GAIN (dB) 70 60 26 25 24 23 22 21 20 19 18 17 16 0
VDD = 50 Vdc, IDQ = 100 mA, f = 230 MHz Pulse Width = 100 sec, 20% Duty Cycle
Figure 6. Pulsed Power Gain and Drain Efficiency versus Output Power
90 80 D, DRAIN EFFICIENCY (%) 70 60 50 40 30 20 VDD = 50 Vdc, IDQ = 100 mA, f = 230 MHz Pulse Width = 100 sec, 20% Duty Cycle 0 200 400 600 800 1000 1200 1400 1600 VDD = 30 V 35 V 40 V 45 V 50 V Gps, POWER GAIN (dB) 26
VDD = 50 Vdc, IDQ = 100 mA, f = 230 MHz 25 Pulse Width = 100 sec, 20% Duty Cycle 24 23 25_C TC = --30_C
--30_C 25_C
85_C 70 60 50
40 30 20 2000
Figure 9. Pulsed Power Gain and Drain Efficiency versus Output Power
TYPICAL CHARACTERISTICS
109 108 MTTF (HOURS) 107 106 105 104 90 110 130 150 170 190 210 230 250 TJ, JUNCTION TEMPERATURE (C) This above graph displays calculated MTTF in hours when the device is operated at VDD = 50 Vdc, Pout = 1250 W CW, and D = 74.6%. MTTF calculator available at http://www.freescale.com/rf. Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product.
Zsource
f = 230 MHz
VDD = 50 Vdc, IDQ = 100 mA, Pout = 1250 W Peak f MHz 230 Zsource 1.29 + j3.54 Zload 2.12 + j2.68
Zsource = Test circuit impedance as measured from gate to gate, balanced configuration. Zload = Test circuit impedance as measured from drain to drain, balanced configuration.
--
-Z source Z
+ load
PACKAGE DIMENSIONS
REVISION HISTORY
The following table summarizes revisions to this document.
Revision 0 1 Date Nov. 2010 Jan. 2011 Initial Release of Data Sheet Fig. 1, Pin Connections, corrected pin 4 label from RFout/VGS to RFin/VGS, p. 1 Description
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MRFE6VP61K25HR6 MRFE6VP61K25HSR6
Document Number: RF Device Data MRFE6VP61K25H Rev. 1, 1/2011 Freescale Semiconductor
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