Chipledge Siiling for excelence SCAN Compression Lab Manual 4 Lab (4a & 4b) Learning Objective In this Lab, you will configure Scan compression for different compression ratios and insert sean along with Scan compression. You will understand different types of Test Mode configuration. There are questions added in the Lab manual in order to improve your knowledge and analysis skills. i Labga | Scan compression with compression ratio of 10 1 Tabgb | Sean compression by configuring exact scan chain length At the end of the Lab, you should be ableto, © Configure Sean compression. Insert sean with compression © Understand different compression blocks © Understand multiple test mode operations Laboratory Tasks Lab 4a: Scan compression with compression ratio Copy the lab database to your home directory. p -/dft/scan_labs/s ChipEdge Technologies Pvt LtdChipEdge Sing fr Go through the directory structure & files Input/aig_top.v > Synthesized design netlist Scripts -> Scripts directory to invoke DC and run sean compression Seripts/run -> Run script to invoke DC Seripts/scan_compress.tel -> To insert sean with compression Reports, ~> Directory to save all reports Output -> To write out sean inserted netlist and SPF invoke the DFT Compiler in Shell mode. This is another way of saving the sereen output to the logfile. linux > tesh nux >which de_s s/labsa inux > de_shell -output_log file Log file will be save in logs directory. Set the library paths dc_shell> set lib_path (//toels/libraries/28nm/SAED32_EDK dc_shell> set searchfpath [list . $lib_path ] dc_shell> lappefd “seach_path "/€ools/Libraries/28nm/SAED32_EDK/lib/stdcell_lvt/db_nldm /tools/Libraries/28nm/SAED32_EDK/1ib/stdcell_rvt/db_nidm /tools/1ibraries/28nm/SAED32_EDK/1ib/stdcell_hvt/db_nldm /tools/libraries/28nm/SAED32_EDK/tech/milkyway " dc_shell> set_app_var target_library {saed32Ivt_ss0p95vl25c.db saed32rvt_ss0p95v125c.db saed32hvt_550p95v125c. db} dc_shell> set_app_var link library {* saed321vt_ss0p95v125c.db Saed32rvt_ss0p95v125c.db saed32hvt_ss0p95v125c.db} ChipEdge Technologies Pvt Ltdsa FA, ChiplEdgé ‘Sling for extelence Read the dig_ de_shell > read file input/dig _top.v -format verilog Set current design to TOP module, dig_top de_shell > set current_design dig top Link the design with libraries de_shell > link Set the Scan architecture type to multiplexed Sean dce_shell > set_scan_configuration -style multiplexed flip flop Convert normal flops into Sean flops dc_shell > compile -scan ChipEdge Technologies Pvt Ltd“4 is g A. x ChiplEdgé ‘Sling for extelence Enable the Sean insertion with Compression dc_shell > set_dft_configuration -scan_coi Why do we need multiple TESTMODE signals? Define the clocks de_shell > set_dft_sii inal -view existing dft -type \ ScanClock -port clkin ~| dc_shell > set_dft_signal -view existing dft -type)\ ScanClock -port clk 500khz -timing [list 40 60] List out the names and number of clocks in the design Define the reset with active state dc_shell > set_dft_ gnal ing _dft -type Reset \ -port resetym\-aetive state 0 Define the Testmode signal with active state de_shell > set{Ft, Signal -view existing _dft -type \ TestMode -port test_override -active_state 1 How many number of primary inputs and primary outputs Create the Compress_mode port to select between Intern ScanCompress de_shell > create_port COMPRESS _MODE -dir IN ChipEdge Technologies Pvt Ltd“4 is g A. x ChiplEdgé ‘Sling for extelence Define Compress_mode signal as Testmode dc_shell > set_dft_signal -view spec -type TestMode \ port COMPRESS MODE -activ » state 1 Why do we need multiple TESTMODE signals Create and define Scan Enable signal de_shell > create port SCAN_EN -dir IN dc_shell > ew spec -type ScanEnable \ Also create and define SCAN ports dc_chell > create port SCAN_INI dir IN > create port SCAN_IN2 -dix"TN, dc_chell > create port scaN_ouTbidiz our de_shell > create_port SCANQUT2, -di?\oUT ft_signal -view spee"-type ScanDataIn port SCAN_INI dic_shell > set_dft_signal -yiew spec -type ScanDataln -port SCAN_IN2 de_shell > set_dft signal’ -view spec -type ScanDatadut -port SCAN_OUTI dic_shel1 > set_dgt_signal -view spec -type ScanDataout -port SCAN_OUT2 List ont resets, sets, testmode, sean enable, sean input and sean output ports Define number of Scan channels to 2 de_shell > set_scan_configuration -chain_count 2 ChipEdge Technologies Pvt Ltd«A Chipledge ‘ing for excelence Define number of internal Sean chains to 20 de_shell > set_scan_compressi| configuration -chain count 20 What is the compression ratio in this configuration? Create test protocol before checking DRC di shell > create_test_pr. Check the DRC before scan insertion dc_shell > dft_dre List out all the DFT DRC violations How many sequential elements able to be stitched in sean chains, How many sequential elements not able to be stitched in sean ehains Preview the design before Sean compression dft -test de_shell > prev: ints all Analyze the scan chain configuration in Ipterna1_Scan mode and Compression mode What is the Sean chain length ofall Sean chains Check the x-tolerance level Scan stitching along with compression a > shell\> inge¥t aft Which Tes tMoce signal is used for Scan compression? Write scan compression Netlist dce_shell > write file -format Verilog -hierarchy \ -output output/dig_t p_compr.v ChipEdge Technologies Pvt LtdA Chipledgé ‘ling for excelence Write test protocol file for normal scan mode and compression mode.Use test_moce option to select between two modes. de_shell > write test_protecol -output output/dig_top_scan.spf\ ~test_modeInternal_scan de_shell > write test_protocol -output output/dig top compress. spf\ Report scan chain details for both test modes. dc_shell > report_scan_path -test_mode all\ > reports/scan_ce. ompress.rpt Report Scan compression configuration and dft configuration de_shell > report_scan_compression_configuration’ \ > reports/scan_compress_config! pt By opening the report, in a linux terminal Understand sean compression steps and all scan configurations. Exit DFT Compiler shell. a > shell > exit Lab 4b: Sean compression with exact internal sean chain length configuration Invoke the DFT Compiler in Shell mode. > tesh linux >wh. linux > de_sh Set the library paths dc_shell> set lib path /tools/libraries/28nm/SAED32_EDK dc_shell> set search_path [list . $lib_path ] ChipEdge Technologies Pvt LtdChipedge ‘ing for excelence shell> lappend search_path /tools/libraries/28nm/SAED32_EDK/lib/stdcell_lvt/db_nldm /tools/libraries/28nm/SAED32_EDK/lib/stdcell_rvt/db_nldm /tools/libraries/28nm/SAED32_EDK/lib/stdcell_hvt/db_nldm /tools/libraries/28nm/SAED32_EDK/tech/milkyway " de_shell> set_app_var target_library {saed32lvt_ss0p95v125c.db saed32rvt_ss0p95v125c.db saed32hvt_Ss0p95v125c.db} dc_shell> set_app var link library {* saed32lvt_ss0p95v125c.db Saed32rvt_ss0p95v125c. db, saed32hvt_ss0p95v125c. db} Read the scan mapped netlist to save run time. de_shell > read file input/dig top _scan_mappéd.v “format verilog Set Current design to TOP module, ie dig_top de_shell > set current_design dig top Link the design with libraries de_shell > link Enable the Scan insertion with Compression de_shell > set_dft_configwration -scan_compression enable Define the clocks dc_shell >sset.dft signal -view existing dft -type \ ng [list 40 60] ScanClock -port clkin -t. de_shelS set_dft_signal -view existing dft -type SeanClock -port clk_500khz -timing [list 40 60] Define the reset with active state dc_shell > set_dft_signal -view existing dft -type Reset \ -port reset_n - active state 0 ChipEdge Technologies Pvt LtdChipEdge sing for ee Define the Testmode signal with active state de_shell > set_dft_signal -view existing _dft -type \ TestMode -port test_override -active_state 1 wort to select Create the Compress_mo. ScanCompress de_shell > create port COMPRESS _MODE -dir IN Internal_scan and Define Compress_mode signal as Testmode do shell > set_dét_signal ~ iew spec -type Testéode {poet \ COMPRESS_MODE ~active state 1 Create and define Scan Enable signal dc shell > create port SCAN EN -dir Iv de_shell > set_dft_signal -view Spee -type Scangnable \ -port SCAN_EN. Also create and define SCAN ports. Use FOR loop to make task simple. Note that all the commands need to be executed in one step, for the “for” loop to work. dc_shell > forgfset\Ij1} ($ix= 4} {incr I 1} dc_shebl > create _port -dir in SCAN_INTS. de_shell $ Greate port -dir out SCAN_OUT[$i] ew spec -type ScanDataIn -port SCANIN[$i] -test_mode all de_shell dft_signal -view spec -type ScanDataOut \ -port SCANOUT[$i} -test_modeall } Define number of Sean channels to 4 de_shell > set_scan_configuration ~chain_count 4 ChipEdge Technologies Pvt LtdChipEdge sing for ee Define max chain length for internal sean chains de_shell > set_scan_compression_configuration -max_length 300 Create test protocol before checking DRC de_shell > create_test_protocol Check the DRC before sean insertion de_shell > dft_dre -verbose Preview the design before Scan compression de_shell > pre dft -test_points all Analyze the sean chain configuration in Internal_Scan mode and Compression mode Check the Sean chain length of all Sean chains Scan stitching along with compression de_shell > insert_dft Write scan compression Netlist dce_shell > write £118 -format Verilog -hierarchy \ -cutpubyeutput/dig_top_compr.v Write test protocol file for normal sean mode and compression mode Use -test_mode option to select between two modes. de_shell > write _test_protocol -output output/ \ ¢_top_by, pf -test_modeInternal_scan de_shell > write_test_protecol -output output/ \ dig top _compr.spf -test_modeScanCompression_mode 10 ChipEdge Technologies Pvt Ltd=a pe ChiplEdgé ‘Sling for extelence Report scan chain details for both test modes. de_shell > rep. t_scan_path -tes > reports/scan_chains Report Scan compression configuration and dit configuration de_shell > report_scan_compression_configuration > \ /sean_compres: reports check the difference between the scan inserted netlist and the scan compressed netlist ? Exit DFT Compiler shell. de_shell > exit 1. What are the inputs for SCAN Compression? Commands used for fixing DFT DRC 3. What are the ways to fix DFT DRC’s? 4, Command used for scan stitching and inserting compression? 5, What are the output files from Sean Compression? 6. What are blocks / modules added after Sean compression? aL ChipEdge Technologies Pvt LtdChipEdga Siilng for exeatence 7. What is x-masking and how to handle it? 8. Will the tool balance sean chain automatically? 9. What is the best compression ratio and max chain length for compression? seeeereeeeeeeeee End of Labgtttereeeerent ChipBdge Technologies Pet Ltd 10