Chipl=dge Shing fr eXcelence SCAN Insertion Lab Manual 3 Lab3a Learning Objective In this Lab, you will apply the scan constraints, analyze and fix DRCs, and perform sean insertion. At the end of the Lab, you should be able to, Analyze and understand Sean DRC issues © Scan DRC fixing by manually editing the netlist © Stitch the sean chains ‘© Write the output files in different formats as required for ATPG Tasks: SCAN DRC Analysis, Fixing and Sean Insertion Tn the last lab, we have done till create test protocol , but not the DRC rule checks. In this lab, we will be starting with DRC checks. can_lab3 . Invoke the DC shell in the terminal but not in the xterm window. ChipBdge Technologies Pvt LtdChipl=dge Pas age linux >which de_shell Run DRC cheeks de_shell >dft_dre Total DRC violations List the name, number and cause of Violations 1) 2) How many total sequential cells in the design How many Sequential cells with violations, How many Sequential cells without violations Analyze the DRC violations by opening the gui window shell > gui_start ChipBdge Technologies Pvt Ltdrk ChiplEdgé seco In the GUI window, run the DFT DRC again as per below menu. desc cn Tepe So te) ie Et ew Select Hah Usk Herwchy Design ses Scherate Ting] ast Power Ande. Widow He FE wld Tne kai On the left side window you will see pre-dit violations as shown below and right side window shows the violated pins. Fle Edt View Select Hghight Ust Hierarchy Design Altibutes Schematic Timing Test fower AnalyzeRTL Winde isAS| (00 >Qo|l* */2 e898 BB we lle coroner 1) Wolion categorie [Count Showing 5 oS vlotions ERED a elaton'd 7 [olan Pn ‘outa reglaOuK out2_regi SVC out2-regl2yCX out2_reg( CLx out2_reglOVCLx include: ? Exclude: ee Double clicking the violated pin will provide schematic view of that particular violation ChipBdge Technologies Pet LtdDRC fixing by manually editing the netlist Copy the scan compiled netlist with some other name for editing purpose As we ean see in the above schematic, clock signal to the out2_regfo] is generated from clk_int_reg flop. since this is internally generated clock, this is D1 clock violation and need to be fixed by making it port level controllable using top level clock pin. This ean be made controllable by manually inserting 2:1 mux cell in the netlist at the clock input of out2_regfo]. Similarly Dg violation (internally generated reset) need to be fixed with port level reset as one of the input and the mux testmode as select signal. After inserting these two cells save the netlist ChipEdge Technologies Pvt Ltdera ChiplEdgé Sling for excelence Alternative way of DRC fixing Ina bigger design manually editing the netlist to fix the DRCs is complex and prone to mistakes. In such cases you ean use autofix command as below. Fix the Clock DRC using Autofix de_shell > set_dft_configuration -fix_clock enable de_shell > set_dft_signal -view spec -type TestData\=port clk de_shell >set_dft_signal -view spec -type TestMode “port \ TestMode -active state 1 de_shell > set_autofix_configuration -type Glock -control \ TestMode -test_data clk Fix the Reset DRC using Autofix dc_shell > set_dft_configuration -fix_reset enable de_shell > set_dft_signal @viewsspec -type dc_shell > set_autofix_@onfiguration -typ e TestMode -test data reset Lets exit the shell and run the DRC fixed netlist de_shell > exit Open the below seript and familiar with the commands, This seript has all the commands upto test protocol. Linux > gvim scripts/counter_drc_fix.tel Invoke the DC shell to run the flow on the DRC fixed netlist. linux > de_shell -output_log file logs/dre_fix.log ChipEdge Technologies Pet Ltdrk ChiplEdgé Sling for excelence Source the below script to load the DRC fixed netlist and other sean configuration commands. dc_shell > source scripts/counter_drce_fix.tcl Create test protocol and run the DRC checks de_shell > create test_protocol Now check the DRC violations and fill the following questions Total DRC violations List the name, number and cause of Violations ) —___ =e 2) How many total sequential cells in the design How many Sequential cells with violations How many Sequential cells without violations Ifthe violations are fixed completely, we can proceed to stitch the scan chains. Preview the design before stitching dc_shelI\> previewdtt Stich the sean chain de_shell > insert_dft Write out Sean inserted netlist in Verilog format de_shell > write file -format Verilog -hierarchy\ -output outputs/scan_inserted.v ChipBdge Technologies Pet LtdChipledgé Sang for ee Open the scan inserted netlist and check how scan chain is stitched de_shell > sh gvim outputs/scan_inserte Write Reports (Number of Sean Chains, Scan Cells) de_shell > report_scan_path -chain all > reports/ scan_chain. rpt open the scan chain report and check different scan flops in the design, scan input, sean ouptput pins..ete. de_shell > sh gvi de_shell > report_scan_path -cell all > reports/Sean_cells.rpt open the scan cells report and understand the report de_shell >sh gvim reports/scan_cells.rpteg Write outputs in different file formats and understand each file, by opening each file. de_shell > write test_protocal -outpit’ outputs \ /scan_inserted. spf de_shell > write_test_motieloformat dde -output \ outputs /scan. inserted. dde dc_shell > wrif@%test/model -format ctl \ ~otitpat_gutputs/scan_inserte: ChipEdge Technologies Pet LtdChipedGe . inledae What are the output files of the scan insertion What is the full form of SPF. What is the full form of CTL. What is the fullform of DDC What information contains in SPF What information contains in CTL. What is the difference between SPF, CTL, and DDC. What is the use of ereate test protocol How to conform whether sean insertion is done proper or not eeeneneeRen EH E Nd of the Labgat****terrenanncnenane ChipBdge Technologies Pet Ltd