Chipledga Siding for ettelence SCAN Insertion Lab Manual 2 Lab2a Learning Objective In this Lab, you will learn about netlist, libraries, invoking the tool, apply the scan constraints. This Lab is more of command based & executing the command based labs helps for better understanding. At the end of the Lab, you should be able to, Define Clock and reset constraints © Convert normal flop into sean flop Define Scan constraint and configuration Tasks: Understand the sean flow Copy the lab database to your home direetory > ed scan’ Tab: ChipEdge Technologies Pvt Ltd=, afk ChiplEdgé Pee In the previous lab, you have understood about the netlist, libraries, lets start the tool and run the scan flow step by step. invoke the DFT Compiler tool in shell mode. linux > tesh Linux >which dc_shell linux > de_shell -output_log file logs/lab2a.log Log file will be saved in logs directory. The result of all the commands executed will be captured in the log file. You are within the DFT compiler shell now. All the tool related commands need to be executed within this shell, but not in the linux shell. Set the library paths de_shell> set lib path /tools/libraries/28nm/SAED32_EDK dc_shell> set search_path [list . lib path ] dc_shell> lappend search_path "/€ools/libraries/28nm/SAED32 £DK/lib/stdcell_lvt/db_nldm /tools/libraries/28nm/SAED32_EDK/Vib/stdcell_rvt/db_nldm /tools/libraries/28nm/SAED32UEDK/1ib/stdcell_hvt/db_nldm /tools/libraries/28nm/SAED32_EDK/tech/milkyway " dc_shell> set_app_var target library {saed321vt_ss0p95v125c.db saed32rvt_ss0p95vi25c. db_saed32hvt_ss0p95v125c.db} de_shell> set_applvar link library {* saed32lvt_ss0p95v125c.db saed32rvt_ss0p95wi25c¢db saed32hvt_ss0p95v125c. db} Read the netlist dc_shell >\read_file inputs/counter.vs -format Verilog Set current design to top module de_shell > set current_design up_down_counter Link the design with the libraries dc_shell > link In the logfile, check the list of libraries linked to the design. ChipEdge Technologies Pvt LtdChipledge Siding for ettelence Set the Scan architecture type to multiplexed Sean de_shell > set_scan_configuration -style multiplexed flip flop ‘To know the purpose and usage of any command, you can use “nan” command. For example to know the "set_scan_configuration” command, use dc_shell> man set_: Convert normal flops to sean flops de_shell > compile -scan Write sean mapped netlist de_shell > write file -format vefilog -output \ output: ile scan.v Open the scan mapped netlist in a separate linux window, but not in de_she1J and check how D flip flop is transformed into sean lip flop. linux > gvim outptits/compile _scan.v What is the name of the sean flipflop ? What extra pins are added to the sean flop compared to D flop and how are these pins connected? Define the scan clock, on existing clock port with name “clk” de_shell > set_dft_signal -view existing dft -t, ist 40 60] Note: ChipEdge Technologies Pvt LtdChipledge ipl=dge pi-cge Tf the command is successful, tool will return “1”, else it will return “o”. This is applicable to all commands. Define the reset with active state dc_shell > set_dft_signal - reset -port reset -active_state 0 Create and define the Testmode signal dc_shell > create port TestMode -dir IN dc_shell > set_dft_signal -view spec -type TestMode \\ port TestMode -active_state 1 Create and define Scan Enable signal de_shell > create port SCAN_EN -dir IN) de_shell > set_dft_signal -view spec -type ScanEnable \ -port SCAN_EN Create and define Scan input and output ports hell > create_port§$CAN_IN\-dir IN de_shell > se dft,sighal\-view spec -type ScanDataIn \ ~port¢SCAN. IN, dc_shell >«create\port SCAN_OUT -dir OUT al -view spec -type ScanDataOut \ ur Define scan chain dc_shell > set_scan_path chainl ~— SCAN_IN -scan_data_out SCAN_OUT scan data in \ Set scan configuration to single chain. de_shell > set_scan configuration -chain count 1 ChipEdge Technologies Pvt LtdChipiedga Siding for ettelence Create test protocol de_shell > create _test_protocol Exit the tool. In the next lab, you will be doing DRC rule checking and fixing. de_shell > exit Ae eRE EKER END of Laboat ttt tentie sien tien ChipEdge Technologies Pvt Ltd