GENERAL REGISTER ORGANISATION

• When we are using multiple general purpose registers, instead of a single

accumulator register, in the CPU organization then this type of organization is
known as general register based CPU organization.
• In this type of organization , the computer uses two or three address fields in
their instruction format.
• For example:
MUL R1 R2 R3
This is an instruction of an arithmetic multiplication written in assembly
language. It uses three address fields R1, R2 and R3. The meaning of this
instruction is:
R1<- R2*R3
This instruction also can be written using only two address fields as:---
MUL R1 R2
The meaning of this instruction is: R1<- R1*R2
• The CPU bus system is managed by the control unit. The control unit
explicit the data flow through the ALU by choosing the function of the
ALU and components of the system.
• Consider R1 ← R2 + R3, the following are the functions implemented
within the CPU −
• MUX A Selector (SELA) − It can place R2 into bus A.
• MUX B Selector (SELB) − It can place R3 into bus B.
• ALU Operation Selector (OPR) − It can select the arithmetic addition
(ADD).
• Decoder Destination Selector (SELD) − It can transfers the result into
R1.
 • The multiplexers of 3-state gates are performed with the buses. The
state of 14 binary selection inputs determines the control word. The
14-bit control word defines a micro-operation.

CONTROL WORD

• There are 14 binary selection inputs in the unit, and their combined value
specifies control word.
• It consists of four fields:

SEL A SEL B SEL D OPR

3bits 3 bits 3 bits 5 bits

✓ Three fields contain three bits each, and one field has five bits.
✓ The three bits of SEL A select a source register for the A input of the ALU.
✓ The three bits of SEL B select a register for the B input of the ALU.
✓ The three bits of SEL D select a destination register using the decoder and
its seven loads output.
✓ The five bits of OPR select one of the operations in the ALU.
Encoding of register selection field
BINARY CODE SEL A SEL B SEL D
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
Encoding of ALU Operations

OPR Select Operation Symbol

00000 Transfer A TSFA

00001 Increment A INCA

00010 Add A + B ADD

00101 Subtract A - B SUB

00110 Decrement A DECA

01000 ADD A and B AND

01010 OR A and B OR

01100 XOR A and B XOR

01110 Complement A COMA

10000 Shift right A SHRA

11000 Shift left A SHLA

There are some ALU micro-operations are shown in the table.
ALU Micro-Operations

Micro-
SEL SE SEL OP Control Word
operati
A LB D R
on

R1 ← 0 0 0 001
SU
R2 – R2 R3 R1 1 1 0 01
B
R3 0 1 1

R4 ← 1 1 1 010
R4 ∨ R4 R5 R4 OR 0 0 0 10
R5 0 1 0

R6 ← 1 0 1 000
INC
R6 + - R6 R1 1 0 1 01
A
R1 0 0 0

0 0 1 000
R7 ← TSF
R1 - R7 0 0 1 00
R1 A
1 0 1

0 0 0 000
Output No TSF
R2 – 1 0 0 00
← R2 ne A
0 0 0

Output 0 0 0 000
Inp No TSF
← - 0 0 0 00
ut ne A
Input 0 0 0

1 0 1 110
R4 ← SH
R4 - R4 0 0 0 00
shl R4 LA
0 0 0
 1 1 1 011
XO
R5 ← 0 R5 R5 R5 0 0 0 00
R
1 1 1

Encoding of ALU operations

Operation Symbol
Transfer A TSFA
Increment A INCA
Add A+B ADD
Subtract A-B SUB
Decrement A DECA
And A and B AND
OR A and B OR
XOR A and B XOR
Complement A COMA
Shift right A SHRA
Shift left A SHLA
The advantages of General register-based CPU organization –
• The efficiency of the CPU increases as large number of registers
are used in this organization.
• Less memory space is used to store the program since the
instructions are written in a compact way.
The disadvantages of General register based CPU organization –
• Care should be taken to avoid unnecessary usage of registers.
Thus, compilers need to be more intelligent in this aspect.
• Since a large number of registers are used, thus extra cost is
required in this organization.
STACK ORGANISATION
• A storage device that stores information in such a manner that the item stored
last is the first item received.
• Also called last-in-first out(LIFO)list.
• The stack is a memory unit with an address register called a stack pointer
(SP), which always points at the top element in the stack.
• The two operations of a stack are the insertion (PUSH) and deletion (POP)
of elements.
• PUSH operation increments the SP.
• POP operation decrement the SP.

REGISTER STACK

• A stack can be placed in a portion of a large memory or it can be organized

as a collection of finite number of registers.
• The organisation of a 64-word register stack.
• The stack pointer register (SP) contains a binary number whose value is equal
to the address of the word that is currently on top of the stack.
• Three items are placed in the stack: A, B and C in that order.
• Item C is on top of the stack so that the content of SP is now 3.
• The stack is popped by reading the memory word at address 3 and
decrementing the content of SP.
• Item B is now on the top of the stack since SP holds address 2.
• To insert a new item , the stack is pushed by incrementing SP.
 ADDRESS
FULL EMPTY
63

3
SP C
2
B
1
A
0

DR

❖ In a 64-word stack, the stack pointer contains 6 bit because 2^6 = 64.
❖ Since SP has only 6 bits.
❖ When 63 is incremented by 1, the result is 0 since 111111+1= 1000000 in
binary, but SP can accommodate only the six least significant bits.
❖ Similarly, when 000000 is decremented by 1, the result is 111111.
❖ The one bit register FULL is set to 1 when the stack is full, the one bit register
EMPTY set to 1 when the stack is empty of items.
❖ DR is the data register that holds the binary data to be written into or read
out of the stack.
❖ Insertion of element
SP<- SP+1
M[SP] <- DR Write item on top of the stack
If (SP=0) then (FULL <- 1) Check if stack is full
EMPTY <- 0 Mark the stack not empty

Deletion of element

SP<- SP-1
M[SP] -> DR Write item on top of the stack
If (SP=0) then (EMPTY <- 1) Check if stack is full
FULL <- 0 Mark the stack not empty
 MEMORY STACK
❖ A stack can exist as a stand-alone.
❖ Stack can be implemented in a random-access memory (RAM) attached to a
CPU.
❖ The implementation of a stack in the CPU is done by assigning a portion of
memory to a stack operation and using a processor register as a stack
pointer.
❖ A portion of computer memory divided into three segments: program, data
and stack.
❖ The program counter PC points at the address of the next instruction in the
program.
❖ The address register (AR) points at an array of data.
❖ The stack pointer SP points at the top of the stack.
❖ The three register are connected to a common address bus, and either one
can provide an address for memory.
❖ PC is used during the phase to read an instruction.
❖ AR is used during the execute phase to read operand.
❖ SP is used to push or pop items into or from the stack.
Stack Pointer is first going to point at the address 3001, and then the stack
will grow with the decreasing addresses. It means that the first item is going
to be stored at address 3001, the second item at address 3000, and the items
can keep getting stored in the stack until it reaches the last address 2000
where the last item will be held.
Here the data which is getting inserted into the Stack is obtained from
the Data Register and the data retrieved from the Stack is also read by the
Data Register.
Example :
The items in the stack communicate with a data register. A new item is
inserted with the push operation as follows:
PUSH:
SP <-SP – 1
M[SP] <- DR
The stack pointer is decremented so that it points at the address of the
next word. A memory write operation inserts the word from DR into the
top of the stack. A new item is deleted with a pop operation as follows:
POP:
DR <- M[SP]
SP <- SP + 1
INFIX TO POSTFIX

❖ A stack organisation is very effective for evaluating arithmetic

expressions.
❖ The common arithmetic expressions are written in infix notation,
with each operator written between the operands.
A*B+C*D
❖ That the arithmetic operation can be represented in prefix notation.
These representation, often referred to as polish notation, place sthe
operator before the operands.
❖ The postfix notation referred to as reverse polish notation (RPN),
places the operator after the operands.
❖ Examples –
A+B INFIX NOTATION
+AB PREFIX OR POLISH NOTATION
AB+ POSTFIX OR REVERSE POLISH NOTATION

The reverse polish notation is in a form suitable for stack manipulation.

A*B+C*D
The expression written in reverse polish notation as AB*CD*+.

Precedence Order and Associativity of Operators

The precedence order of operators is given in the below table.

Precedence Type Operators Associativity

1 Postfix () [] -> . ++ — Left to Right

+ – ! ~ ++ —
2 Unary (type)* & Right to Left
size of

3 Multiplicative */% Left to Right

 4 Additive +– Left to Right

5 Shift <<, >> Left to Right

6 Relational < <= > >= Left to Right

7 Equality == != Left to Right

8 Bitwise AND & Left to Right

9 Bitwise XOR ^ Left to Right

10 Bitwise OR | Left to Right

11 Logical AND && Left to Right

12 Logical OR || Left to Right

13 Conditional ?: Right to Left

= += -+ *= /=
14 Assignment %= >>= <<= Right to Left
&= ^= |=

15 Comma , Left to Right

RULES:
• Priority - ^, */, +-
• No two operators of the same priority can stay together in stack column
• Lowest priority cannot be placed before highest priority.
 A*B+C*D infix to postfix

SYMBOL SCANNED STACK POSTFIX DESCRIPTION

EXPRESSION
1 ( ( START
2 A ( A
3 * (* A
4 B (* AB
5 + (+ AB* ‘*’ Is at
higher
precedence
than ‘+’
6 C (+ AB*C
7 * (+ AB*C
8 D (+ AB*CD
9 ) EMPTY AB*CD*+ END
 a-b-c infix to postfix

SY SCANNE STAC POSTFI DESCRIPTION

MB D K X
OL EXPRES
SION
1 a A START
2 - - A
3 b - Ab
4 - -- ab- No two operators of same
priority are stay together
5 c - ab-c
6 - ab-c-
 A*(B+C+D) infix to postfix
SYMBOL SCANNED STACK POSTFIX DESCRIPTION
EXPRESSION
1 A A START
2 * * A
3 ( *( A
4 B *( AB
5 + *(+ AB
6 C *(+ ABC
7 + *(++ AB*C+ No two
operators of
same
priority are
stay
together
8 D *(+ AB*C+D
9 ) *(+) AB*C+D+
AB*C+D+*
 a + b * c infix to postfix
SYMBOL SCANNED STACK POSTFIX DESCRIPTION
EXPRESSION
1 a a START
2 + + a
3 b + ab
4 * +* ab
5 c +* abc* * has highest
priority than
+
6 abc*+
 A+B*(C+D)/F+D*E
SYMBOL SCANNED STACK POSTFIX DESCRIPTION
EXPRESSION
1 A A START
2 + + A
3 B + AB
4 * +* AB
5 ( +*( AB
6 C +*( ABC
7 + +*(+ ABC
8 D +*(+ ABCD
9 ) +*(+) ABCD+
10 / +*/ ABCD+* No two
operators of
same
priority are
stay
together
11 F +/ ABCD+*F
12 + +/+ ABCD+*F/+ / has highest
priority than
+
13 D + ABCD+*F/+D
14 * + * ABCD+F/+D
15 E +* ABCD+F/+DE
16 + * ABCD+F/+DE*
ABCD+F/+DE*+
 INSTRUCTION FORMAT

▪ In computer organization, instruction formats refer to the

way instructions are encoded and represented in machine
language.
▪ There are several types of instruction formats, including zero,
one, two, and three-address instructions.Each type of
instruction format has its own advantages and disadvantages
in terms of code size, execution time, and flexibility.
▪ Modern computer architectures typically use a combination
of these formats to provide a balance between simplicity and
power.
Types of instruction format include:
• Zero(0) Address Instruction format
• One(1) Address Instruction format
• Two(2) Address Instruction format
• Three(3) Address Instruction format
 Types Of Instruction Format
1. Zero(0) Address Instruction format
• The instruction format in which there is no address field is called zero address
instruction.
• In zero address instruction format, stacks are used.
• In zero order instruction format, there is no operand.
• Assembly language instruction – PUSH A, PUSH B etc.

Stack transfer operation – TOS <- A, TOS <- B etc.

Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location

PUSH A TOP = A

PUSH B TOP = B

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

2. One(1) Address Instruction format
• The instruction format in which the instruction uses only one address field is
called the one address instruction format
• In this type of instruction format, one operand is in the accumulator and the
other is in the memory location
• It has only one operand
• It has two special instructions LOAD and STORE
• Assembly language instruction – LOAD C, ADD B, STORE T etc.

Operation Register instruction – AC <- M[T], AC <- M[C] etc.

Expression: X = (A+B)*(C+D)
AC is accumulator
M[] is any memory location
M[T] is temporary location

LOAD A AC = M[A]

ADD B AC = AC + M[B]

STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC
3. Two(2) Address Instruction format
• The instruction format in which the instruction uses only two address fields
is called the two address instruction format
• This type of instruction format is the most commonly used instruction format
• As in one address instruction format, the result is stored in the accumulator
only, but in two addresses instruction format the result can be stored in
different locations
• This type of instruction format has two operands
• It requires shorter assembly language instructions
• Assembly language instruction – MOV R1, A; ADD R1, B etc.

Operation Register instruction – R1 <- M[A], R2 <- M[C] etc.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

MOV R2, C R2 = M[C]

ADD R2, D R2 = R2 + M[D]

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1
4. Three(3) Address Instruction format
• The instruction format in which the instruction uses the three address fields
is called the three address instruction format
• It has three operands
• It requires shorter assembly language instructions
• It requires more bits.
• Assembly language instruction – ADD R1, A, B etc.

Operation Register instruction – R1 <- M[A] + M[B] etc.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]

MUL X, R1, R2 M[X] = R1 * R2