A COURSE ON RECONF)GURABLE

PROCESSORS
ABDULHADI SHOUFAN AND SORIN A. HUSS
Integrated Circuits and Systems Lab.

Technische Universität Darmstadt, Germany

_________________________________________________________________
Reconfigurable computing is an established field in computer science. Teaching this field to computer science
students demands special attention due to limited student experience in electronics and digital system design.
This paper presents a compact course on reconfigurable processors, which was offered at the Technische
Universität Darmstadt, and is intended for instructors aiming to introduce a new course in reconfigurable
computing. Therefore, a detailed description of the course structure and content is provided. In contrast to
courses on digital system design, which use FPGAs as a case platform, our course places this platform at the
centre of its focus and highlights its features as a basis for reconfigurable computing. Both declarative
knowledge and functioning knowledge are considered in defining learning outcomes based on a novel What-
Why-How-Model. Lab activities were designated to deepen the functioning knowledge. The written exam is
aligned to learning outcomes and shows that most students acquired the intended outcomes.

Categories and Subject Descriptors: K.3 [Computer and Education]: Computer and Information Science
Education – Computer science education; Curriculum

General Terms: Educational WWH-Model, Reconfigurable Computing, FPGA, Coprocessors

Additional Key Words and Phrases: Design process, VHDL, configuration resources, configuration
technologies

_________________________________________________________________

1. INTRODUCTION
Field Programmable Gate Arrays (FPGAs) present a trade-off between software
solutions with high availability, high flexibility, and low costs, and application
specific integrated circuits (ASICs) with high performance, low power, and small
space. By combining the advantages of these two extremes, FPGAs increase in
importance. As an alternative to ASICs, FPGAs were originally introduced for
engineers facing high demands on short time-to-market. With their increasing
integration densities and their computational capabilities on the one hand, and
with their rising performance on the other, FPGAs are invading computer
architectures considerably, for example, as application accelerators [Intel 2008].
Thus, understanding system design with FPGAs is not limited to students focused
primarily on hardware design. Rather, students focused on software and
algorithms, such as most computer science majors, will benefit from these
architectures to build high-performance coprocessors, which serve several
applications due to reconfigurability. To qualify those students for this field,
special courses on reconfigurable computing should be offered. Unfortunately,
most related work on teaching configurable hardware is either specific to
students of electrical engineering with corresponding previous knowledge [
LOYA-HERNANDEZ 2007, SKLYAROV 2005], or uses FPGA platforms to
teach different topics such as digital design foundations and computer
architectures [TEUSCHER 1999, HALL 2006, VERA 2006, STANLEY 2007,
TORRESEN 2007] with corresponding abstractions from the FPGA platform.

This paper describes a course on reconfigurable processors, which we have

offered in the computer science department at Technische Universität Darmstadt
(TUD) since 2002. The description in this paper relates to the course’s state as of
the winter semester 2007/2008. In contrast to other courses, which use the FPGA
as a case platform, our course places this platform at the centre of investigation
as an enabler of reconfigurable computing. This investigation ranges from the
effect of a switch transistor on timing behaviour to using embedded processors
on FPGAs to set up systems-on-chip. We believe that this thorough learning of
today’s FPGA platforms is a precondition, not only for its usage in applied
reconfigurable computing, but also for understanding the present limits of these
platforms as a motivation for further research work in the field of reconfigurable
computing.

The paper targets classroom instructors aiming to introduce a concise course on

reconfigurable computing and looking for a structure and content suitable for
computer science students with previous knowledge on logical design only. In
summary, the course has the following didactical features:
1. The course comprises 13 90-minute lectures and 6 labs, which corresponds to
a total of 4.5 credit points according to the European Credit Transfer System
(ECTS). One credit point in ECTS corresponds to 25 to 30 working hours by
students [ECTS 2009]. The presented course assumes a workload of about
135 hours, where 20 hours thereof are lecture time. The remaining hours are
spent in labs and self-study. ECTS attaches 60 credit points to the workload
of a full-time year of formal learning. This workload mostly ranges from
1,500 to 1,800 hours of work.

2. The course is structured based on a new What-Why-How Model (WWH-

Model) which presents a guiding theme for all course topics. By this means,
instructors are able to extend selected topics or to add new ones without
affecting the logical and didactical structure of the course. In the scope
constructive alignment [Biggs2007], the WWH-Model can be employed to
define the intended learning outcomes.

3. The course aims at increasing both the width of declarative knowledge by the
variety of lecture topics and the depth of functioning knowledge by lab
design assignments.

4. The lectures are supported by interactive slides, demonstrations using

commercial tools, and by an excursion a semiconductor fabrication plant at
the Institute for Semiconductor Technology at TUD.

5. Student learning outcomes are evaluated both by formative assessment in the

labs and by a summative assessment by a written exam.

The remainder of the paper is organized as follows. Section 2 outlines

reconfigurable computing and points out its importance in education. Section 3
describes the structure of the course reconfigurable processors at TUD. Section 4
details the lecture content. The lab is outlined in Section 5. The assessment
methods are described in Section 6. Section 7 presents the course evaluation by
students and Section 8 concludes the paper.
2. RECONFIGURABLE COMPUTING IN EDUCATION
2.1 Why Teaching Reconfigurable Computing

Reconfigurable computing refers to the computing on a reconfigurable platform,

which is currently an FPGA, but can include other adaptable fabric. Many
computer scientists consider FPGAs to be more than just hardware chips for fast
prototyping. Due to a performance boost of several orders of magnitude and, at
the same time, power saving of more than one order of magnitude, some
researchers use the concept of reconfigurable computing even to express a
paradigm shift in computing, which could or should replace computing paradigm
based on von Neumann architecture [Zomaya2006]. Whatever the understanding
of reconfigurable computing, its original benefit results from combining two
features which are never combined by other architecture solutions such as array
processors, supercomputers, and graphical processing units:

1. High performance due to hardware capability.

2. Economic efficiency due to reconfigurability, which allows the use of same

platform for many computing purposes. This feature is often referred to as
flexibility.

Thus, reconfigurable computing aims at constructing high-performance

application-specific processors or coprocessors which share the same platform.
To achieve this aim, researchers and industries have been trying to answer two
main questions, which we call the allocation and the mapping questions:

1. Allocation question: What should the reconfigurable platform look like?

2. Mapping question: How should we map applications onto the reconfigurable

platform?

Understandably, the allocation question is more critical as the reconfigurable

platform is the technological enabler of reconfigurable computing. Nevertheless,
answering this question was always restricted by industrial concerns about
economies of scale. Despite several proposals on novel platforms mostly
featuring coarser granularity [Hauck2007], FPGAs remain the most economic
choice to support reconfigurable computing. Given the reconfigurable platform,
the mapping question largely amounts to a platform-based design process, which
has large similarities with other platform-based design approaches. The
difference is that the design approach for reconfigurable computing must
consider several applications or several application portions sharing the platform.
The dream of a platform-independent design approach of reconfigurable systems
will remain a dream as long as the more modest dream of Electronic System-
Level Design (ESL) is not brought to reality.

Knowing its importance and its challenges, which were recently recognized by
the Association for Computer Machinery by establishing the Transactions on
Reconfigurable Technology and Systems journal [ACM2009], it is evident that
learning reconfigurable computing at universities is essential for its success.

2.2 Reconfigurable Computing in IEEE/ACM Curriculum

Obviously, reconfigurable computing is a field of computer engineering. The

IEEE/ACM curriculum in computer engineering in its last report [IEEE-
ACM2004], however, did not address this field explicitly. This can simply be
seen by the fact that neither the word “reconfigurable” nor any of its derivatives
appear anywhere in this report. Although this situation seems to be advantageous
regarding the freedom in defining the learning outcomes for a new course on
reconfigurable computing, a reasonable amount of care should be exercised to
keep in line with pedagogical precepts of the IEEE/ACM curriculum and to
define the scope of such a course in relation to other units in that curriculum,
which address FPGAs in some or other way. To be more specific, the
IEEE/ACM curriculum in computer engineering addresses FPGAs in 3 areas of
knowledge and 4 units, as summarized in Table I.
 Table I. FPGA-related topics and learning outcomes in the IEEE/ACM
curriculum in computer engineering

Knowledge Unit Topics Learning Outcomes

Area (i.e. Course)

Digital CE-DIG6: Totally 7 topics. The Totally 4 learning

Logic Digital systems last one: outcomes. The last
design Programmable logic one: Utilize
devices (PLDs) and programmable
field-programmable devices such as
gate arrays (FPGAs), FPGAs and PLDs to
PLAs, ROMs, PALs, implement digital
complex PLDs. system designs.

Embedded CE-ESY8: Totally 4 topics. The Totally 3 learning

Systems Embedded last one: Platform outcomes. Not one
multiprocessors FPGAs as relates to FPGAs
multiprocessors

VLSI Design CE-VLS5: Totally 10 topics. The Totally 8 learning

and Semiconductor 9th one: FPGA and outcomes. Not one
Fabrication memories and related devices relates to FPGAs
logic arrays

CE-VLS10: Totally 7 topics. The Totally 3 learning

Semi-custom 6th one: FPGA and outcomes. Not one
design related devices addresses FPGAs
technologies explicitly.

From this table it is obvious that FPGAs do not take a central role in any unit, as
they do in reconfigurable computing. Therefore, it is highly advantageous to
introduce a new unit (course) which tackles reconfigurable computing with
FPGAs at its center and addresses other aspects of reconfigurable computing
based on a thorough understanding of this platform. Putting the FPGA at the
center is essential for two reasons. First, it is almost the only reconfigurable
platform, which can be deployed in labs to enhance functioning knowledge.
Secondly, to understand why and how reconfigurable computing aims at new
platforms, it is essential to understand all the details and limits of current FPGAs.

2.3 Reconfigurable Processors Learning Outcomes

Knowing that reconfigurable computing aims at the development of

reconfigurable processors or coprocessors, and to highlight the applied aspects of
our course, we entitled it “Reconfigurable Processors”. Please note that the word
‘processor‘ in our course does not refer to the central processing unit and that any
coprocessor is a processor in the end. In the style of constructive alignment
[Biggs2007] we formulate the learning outcomes of our course as follows:

1. Define a reconfigurable processor and explain its main features.

2. Compare reconfigurable processors with other processor types

3. Design a reconfigurable processor based on modern FPGAs

4. Identify fine-grain and coarse-grain reconfigurable resources

5. Explain some applications of reconfigurable processors

While learning outcomes 1, 2, 4, and 5 mostly aim at widening the declarative

knowledge of students, learning outcome 3 tends to deepen the functioning
knowledge by applying practical approaches and commercial tools to design
reconfigurable processors on FPGAs. Learning outcome 3 is therefore supported
by lab sessions. The width of declarative knowledge helps to define the relation
of this course to other courses at TUD, where this knowledge is deepened or
applied, i.e. becoming functioning knowledge (see next subsection). Our course,
for instance, describes SystemC as a high-level design approach for
reconfigurable computing. The details of SystemC are treated in depth in the
course Embedded Systems I. Another example relates to the data flow computer,
which is outlined in our course with reference to the course Computer
Architectures, which details such data flow architectures.
2.4 Reconfigurable Processors in the TUD Curriculum

In the department of computer science at TUD the following courses are offered,
which relate in some way to Reconfigurable Processors. Besides each course or
course set, the main topic of that course is given. The core courses are
prerequisites for our course, which is an elective one.

Core courses

1. Technical Principles of Computer Science I and II: Basics of Logical Design

and Computer Architecture

2. Computer Microsystems: Modeling, Simulation and Synthesis of Digital

Circuits and Systems.

Elective Courses

1. Embedded Systems I and II: Design Methodology of Embedded Systems,

Hardware/Software Codesign, SystemC, Computational Models, TLM, and
SysML.

2. Computer Architectures: Parallel Computing Models, Parallel Algorithms

and Data Flow Architectures.

3. Processor Architectures for Embedded Systems: Very Long Instruction

Word-Architectures (VLIW)

3. COURSE CONSTRUCTION
The WWH-Model represents a suitable means to introduce students to a new
course, to derive the learning outcomes, and to define the course structure and
topics aligned to the learning outcomes. In this respect, the WWH-Model can be
seen as an application of the constructive alignment [Biggs2007] to a large
extent. In the following we first discuss how this model is used to introduce the
new course. Afterwards, we explain the relation between the model and the
learning outcomes already given in Section 2.3. Lastly, the lecture structure is
derived based on that model.

3.1 What-Why-How Model

A course title is the most essential keyword, which often presents a novel and
sometimes mysterious concept for students. An early understanding of the
dimensions of this keyword is essential for familiarizing students with the new
topic. In engineering fields, a course title has often three dimensions which are
highlighted by asking questions of the form: what?, why?, and how? (See Figure
1.).

Fig. 1. What-Why-How Model for course construction.

The question “What?” is usually answered based on students’ previous

knowledge and experience already acquired elsewhere. Instructors may use this
question to verify the suitability of the course in some curriculum or to define the
prerequisites for the course. The question “Why?” points out the relevance of the
new topic. This can normally be answered by presenting some requirements
which can not be fulfilled by objects or methods learnt in other courses. The
question “How?” addresses the engineering aspect and describes how to put the
learnt material into practice. The number of questions and the way they are asked
depend strongly on the course topic and on the word choice in the title.

Specific to the course “Reconfigurable Processors”, the authors follow the

WWH-Model presented in Figure 1, which is introduced in the first 90-minute
lecture to outline the course topics and to derive its structure. The numbers in
Figure 1 refers to the sequence in which the questions are answered in the first
lecture for didactical purposes. The first question is answered based on the
familiarity of computer science students with the concept of processor: A
reconfigurable processor (RP) is a processor which changes its functionality by
changing its architecture, as opposed to a general purpose processor (GPP) which
never changes its functionality because of its hard-wired architecture. However,
GPPs can execute largely different tasks due to the fine granularity of operations
they can perform. Any complex task must be divided into a sequence of these
fine-grain operations, which are then executed on the GPP sequentially. In
contrast, reconfigurable processors perform coarse-grain operations, which make
them less flexible than GPPs. This statement introduces the next question: Why a
reconfigurable processor? Originally, the advantage of using RPs results from
their performance as hardware platforms. Thus, question 2 amounts to: Why is
hardware faster than software? A 4-fold answer can be given: Hardware is faster
than software because of its ability to support wider data paths, to execute
course-grain operations, to use several computational units which operate in
parallel or in pipeline mode, and to use internal memories, which accelerates data
access. Question 3 addresses the reconfiguration resources. For a processor to be
reconfigurable it must contain architecture elements which are changeable.
Generally, architectural elements of a processor perform one of three tasks: They
either perform computation, interface the processor with outside, or transfer data.
Therefore, each reconfigurable processor must contain configurable logic cells,
configurable input/output blocks, and configurable routing resources. Figure 2
illustrates how a logic cell (look-up table) can be configured to implement an
AND gate (left), how to configure an output block to pass a signal through a 3-
state buffer (middle), and how to configure a switch matrix to perform desirable
routing (right).

Fig. 2. Architectural configuration elements.

From this figure it is obvious that a reconfiguration of the architectural elements

demands the writing of new configuration bits. This statement leads to question 4
in Figure 1, which can now be put as follows: How to generate the configuration
bits, how to write them into the reconfigurable processor, and how they are kept
on this processor? Generating the bit stream is based on a complex design
process, which includes system specification, design entry, simulation, synthesis,
placing, routing, and timing analysis, as depicted in Figure 3. For a general
understanding of this design process in the first lecture, we apply it to a simple
digital circuit, an adder, based on a VHDL model. The Integrated Software
Environment (ISE) from Xilinx [XILINX 2008] is then used to synthesize the
code, place and route the netlist, and generate the bit stream which is then written
to a Spartan-3 FPGA on a Starter Board from Digilent [DIGILENT 2008]. The
adder uses some buttons and the DIP-switches on the board to enter the
summands. 7-segment displays show the entered summands and the result.
Afterwards, the VHDL code is modified slightly to make a multiplier. The design
process is started again and the multiplier is demonstrated for persuasion.
The last question in Figure 1 relates to employing a reconfigurable processor and
can be answered by giving examples for different applications such as signal
processing and cryptography.

Fig. 3. Typical design process of FPGAs.

3.2 WWH Model and Learning Outcomes.

As mentioned earlier, the WWH model can assist in writing learning outcomes.
The constructor may ask as many questions as the learning outcomes or vice
versa. For our course, Table II maps to the questions from the WWH model to
the learning outcomes given in Section 2.3.
 Table II. From WWH-Model to Learning Outomes

WWH Model Question Learning Outcome

What is a reconfigurable processor? Define a reconfigurable processor and

explain its main features.
Compare reconfigurable processors
Why reconfigurable processors?
with other processor types

How can a reconfigurable processor be Design a reconfigurable processor

reconfigured? based on modern FPGAs

Identify fine-grain and coarse-grain

What is reconfigured exactly?
reconfigurable resources

How can a reconfigurable processor be Explain some applications of

employed? reconfigurable processors

3.2 Lecture Structure

Depending on the WWH-Model the lecture is structured as depicted in column 2

of Table III. The order of handling these topics given in column 3 presents an
alternative which seemed to be reasonable for students in our department.
Depending on the situation in other departments some topics may be shifted. In
the following some points, which justify the selected lecture order of Table III
are discussed.

System specification and design entry are the most important and time-
consuming tasks performed by designer. Today, the standard way for design
entry relies on hardware description languages such as VHDL. VHDL represents
the designer interface with the design tools and ultimately with the design
running on the FPGA. Changing the function of the FPGA begins with re-coding
the VHDL model. Therefore, learning VHDL is essential at the start of the
course. Lectures 4 to 7 make use of VHDL to point out how different language
constructs affect the configuration resources on the FPGA. Treating the topics of
Lectures 8, 9 earlier would be less motivating, especially as these topics are not
supported by labs. Lectures 8 and 9 are planned between two more challenging
topic blocks: lectures 2 to 7 on the one hand and lectures 10 to 12 on the other.

Table III. Lecture structure based on the WWH-Model

Question from Lecture

Topic
WWH-Model No.
All questions in
Introduction 1
overview
Introduction into synthesizable VHDL
2
modeling (1)
How can a
Introduction into synthesizable VHDL
reconfigurable 3
modeling (2)
processor be
Configuration technologies 10
reconfigured?
Partial and dynamic configuration 11
High-level design of reconfigurable processors 12
Configuration of logic cells 4
What is reconfigured Configuration of I/O blocks 5
exactly? Configuration of routing resources 6
Configuration of coarse-grain elements 7
Why reconfigurable Integrated circuits: history and classification 8
processors? Processors: history and classification 9
How can a
reconfigurable
Applications 13
processor be
employed?

4. LECTURE CONTENT
4.1 Lecture 1

Lecture 1 introduces the course by presenting the WWH-Model, answering its

questions succinctly, and deriving the learning outcomes and the lecture
structure, as depicted in the last section. Additional organization issues typically
belong to this lecture. We recommend presenting the WWH-Model of Figure 1
and the course structure of Table III at begin of every lecture, so that students can
recognize the course progress.
4.2 Lecture 2

Because of its hardware relation, VHDL is not easy to learn, especially for
students of computer science. Understanding VHDL depends on an accurate
understanding of hardware properties. Therefore, lecture 2 starts with an
overview of essential hardware properties and illustrating how VHDL reflects
these properties by its different language constructs. Figure 4 outlines the fact
that a hardware unit has an interface and an internal architecture. The architecture
can be described by its structure as a connection of smaller components or by the
function it realizes. A hardware function relates to processing signals by applying
some operation on them and to the time of this processing. Timing behavior of
hardware can be specified by the processing delay, on the one hand, and by the
speed of hardware reaction on changes of input signals, on the other.
Asynchronous logic is specified by immediate reaction. Synchronous logic, in
contrast, reacts only after a clock edge.

Fig. 4. General description of a hardware module.

 Figure 5 outlines how VHDL reflects the hardware properties pointed out in
Figure 4. Based on this outline, small VHDL examples are then presented which
illustrate the different language constructs. Afterwards, more detailed aspects in
VHDL are treated with focus on their synthesizability. These include:

1. Sequential versus concurrent statements

2. Signal versus variables

3. The role of sensitivity list

4. Incomplete if and case statements

5. Multiple-valued logic

6. Combinatorial loops

Recommended literature: [ASHENDEN 2002]

Fig. 5. General view on how VHDL describes hardware.

4.3 Lecture 3

In lecture 3, two essential modeling aspects in VHDL are treated, which

should always be considered when synthesis is intended. These aspects are the
bit-accurate modeling and the cycle-accurate modeling. Bit-accurate modeling is
important to building efficient data paths. The necessity of bit-accurate modeling
can be demonstrated by using the integer type to model an 8-bit adder. The
synthesis of this model will result in a 32-bit adder, which is highly inefficient.
Cycle-accurate modeling corresponds to hardware description on the register
transfer level (RTL), which is supported by most commercial synthesis tools. The
advantage of cycle-accurate modeling can be demonstrated by writing a behavior
model and an RTL model for a simple system, and by synthesizing them and
showing which maximal clock frequency each model achieves. Other important
topics in this lecture are parallelism, pipelining and finite state machines.

Recommended literature: [ASHENDEN 2002]

4.4 Lecture 4

The most important property of FPGAs is the availability of configurable

logic cells to realize logic functions. Lecture 4 treats two well-known types of
these cells which rely on look-up tables and multiplexers. The following topics
are discussed:

1. Mapping VHDL models to logic cells. This task, denoted as logic synthesis,
is demonstrated by applying the ISE design process to a VHDL model and by
inspecting the resulted netlist. Additionally, the placed and routed design is
inspected using the FPGA Editor, which shows how look-up tables are
configured. The FPGA Editor, which is delivered by Xilinx as an accessory
program under ISE, is very powerful for both verification and configuration.
Because of its advanced graphical interface, we highly recommend using
FPGA Editor in class room to illustrate several aspects of FPGA fabric and
design.
2. Basics of logic synthesis and the interplay between synthesis algorithms, the
size of a look-up table and the synthesis result. This effect is considered by
FPGA vendors to decide on an appropriate size for look-up tables. This was
observed by using 6-input LUTs in the Virtex-5 family instead of 4-input
LUTs in older generations.

3. The Electronic Data Interchange Format (EDIF).

4. Building structural VHDL models based on vendor libraries, and showing the
advantage, e.g. performance, and disadvantage, e.g. portability, of this
modeling style.

Recommended literature: [GEREZ 2005]. Documentation available at different

FPGA vendor websites

4.5 Lecture 5

As processors or coprocessors, FPGAs feature flexible interface to support

various input/output standards. This is realized by input/output blocks (IOBs)
which are very sophisticated in modern FPGAs. IOBs allow versatile
configuration possibilities to fit the FPGA to its environment. This lecture treats
the requirements on the FPGA interface and how these requirements can be
fulfilled by configuration. The following topics are handled:

1. Explaining the concepts of wafer, die, chip, pad, and pin and illustrating that
an FPGA with n pins includes n pads and thus n IOBs.

2. Input and output buffers, tri-state buffers, and related topics such as pull-up,
pull-down resistors, bus keepers and slew rate control.

3. Configuring IOBs directly in the VHDL with the aid of vendor-defined

attributes or the use of constraint files. The last approach is often preferable,
as it keeps VHDL models portable.
4. High and low state noise margins and their role in specifying different I/O
standards such as LVTTL, LVCMOS15 and PCI133_3. Additionally, glue
logic is discussed as a solution for the case that an FPGA must be connected
to a chip, which features an I/O standard not supported by the FPGA.

Recommended literature: [SMITH 1997]. Documentation available at different

FPGA vendor websites

4.6 Lecture 6

FPGA routing delay has a major effect on system performance. Routing is

performed automatically with the aid of vendor tools. A manual intervention is
often restricted to defining some timing constraints, which instructs the tools to
find a routing which fulfills some performance requirements. Lecture 6
concentrates on the following topics:

1. Description of different routing structures of modern FPGAs

2. Analysis of the routing delay using the Elmore model

3. Defining timing constraints using user constraint files and VHDL

4. Static timing analysis to inspect the timing behavior of the design. This
includes investigating three paths: flip-flop to flip-flop path (critical path),
which define the clock frequency, input-pad to flip-flop path, which defines
timing constraints on input signals, and the flip-flop to output-pad path,
which defines constraints on output signals. Aside from an analytical
investigation, this topic is demonstrated using the Timing Analyzer from
Xilinx, which is embedded in ISE.

5. Overview on dynamic timing analysis and comparing it with static timing

analysis

6. Overview on placing and routing algorithms

Recommended literature: [SMITH 1997], [GEREZ 2005], Documentation
available at different FPGA vendor websites.

4.7 Lecture 7

High-end FPGAs enable the design of system-on-chip and provide, for this
purpose, coarse-grain resources which are pre-placed and partially routed.
Examples of these resources are embedded memories and embedded multipliers.
Library cells are available which enable the usage of these resources with
different configurations, such as different word widths of a block memory. The
following topics are treated in Lecture 7:

1. Description of different coarse-grain configurable resources including block

memories (BRAMs), multipliers, embedded processors, clock managers and
transceivers.

2. Illustrating the usage of these resources in VHDL models. This can occur
either structurally by direct instantiation of appropriate library elements or
behaviorally in consideration of some coding guidelines provided by
synthesis tool vendors.

3. Using embedded processors demands an introduction to hardware/software

co-design process. For this purpose the embedded design kit (EDK) from
Xilinx is utilized.

Recommended literature: Documentations available at different FPGA vendor

websites

4.8 Lecture 8

After presenting how FPGAs work, a classification of integrated circuits is

given in this lecture using FPGAs as reference. The lecture treats the following
topics:
1. An introduction into semiconductor technology. This topic is supported by an
excursion to a semiconductor fabrication plant in the Institute for
Semiconductor at TUD [IHT 2009].

2. CMOS scaling to show the limits of miniaturization in the semiconductor

technology.

3. Classification of integrated circuits based on the design and manufacturing

process into full-custom ASICs, semi-custom ASICs (standard cells and gate
arrays), FPGAs, structured ASIC, and Standard ICs.

Recommended literature: [SMITH 1997]

4.9 Lecture 9

This lecture gives an overview of the processor development story beginning

from Intel 4040 up to modern processors. Additionally the following aspects are
highlighted:

1. General computer architecture

2. Von Neumann Architecture

3. Data flow computers

4. Current problems of processor technology of today and the paradigm change

towards multi-core processors to cope with power problems.

Recommended literature: [TANENBAUM 2001] [PACTXPP 2008]

4.10 Lecture 10

This lecture treats the configuration technologies of FPGAs including SRAM-

based, Antifuse-based and Flash-based configuration. Additionally the following
topics are discussed:

1. Configuration modes such as SelectMAP, serial, and JTAG configuration.

2. Protecting intellectual property by encrypting the bit stream.

3. Overview of research work on the integrity and authenticity of the bit stream.

Recommended literature: Documentation available at different FPGA vendor

websites

4.11 Lecture 11

Recent work on reconfigurable computing are treated in this lecture. This

includes:

1. Single-context configuration

2. Multi-context configuration

3. Partial configuration

4. Relocation and defragmentation

5. The modular design process for Xilinx PFGAs including the partial
configuration for Virtex II.

Recommended literature: [HAUCK 2007]

4.12 Lecture 12

VHDL is a sophisticated language and allows for hardware description on

different abstraction levels. According to [Cadence 2007], 70% of design starts
are systems-on-chip with embedded processors and software. Thus, a typical
design of modern systems relies on a hardware/software co-design process which
exceeds the capability of VHDL and increases the demand on using high-level
languages which support both hardware and software. For students of computer
science, the design of reconfigurable systems based on high-level languages is of
special interest. This lecture provides an introduction to this design paradigm
which is recently known as Electronic System Level (ESL). Among others the
following topics are discussed:

1. Introduction into SystemC

2. Introduction into HandelC

3. Demonstrating this design methodology using the DK Design Suite from

Agility [AGILITY].

Recommended literature: [BAILEY 2007]

4.13 Lecture 13

As an application for reconfigurable processors the Rekeying Processor

[SHOUFAN 2007] is presented. Other architectures may also be employed. The
rekeying processor is considered because of its versatility from high-performance
computing of cryptographic algorithms to high-flexibility by its reconfigurable
HW/SW architecture.

5. EXERCISE CONTENT
In the lab, students use commercial design tools which include the ISE, EDK,
and PlanAhead from Xilinx, ActiveHDL simulator from Aldec, and DK Design
Suite from Agility. Two hardware platforms are available for lab purposes:
Spartan III Starter Board [DIGILENT 2008] and Xilinx University Program
Board [XILINX 2008]. The lab assignments are divided into two classes: short
assignments and projects assignments.

Short assignments: The purpose of these assignments is to solve, verify,

expand, and exercise some design aspects with direct relation to lecture topics.
These assignments are normally given during the lecture directly after handling
the corresponding topics to point out their context. Some of these assignments
relate to the design of FSMs in VHDL, partial configuration using the modular
design process, and the design of a simple SoC using the embedded processor
PowerPC on Virtex-II Pro.

Project assignments: Two large projects are handled in the course of the
semester to cope with the design process of reconfigurable architectures. Both
projects relate to cryptographic topics, as security hardware is an important
research area at our institute. Students implement the following algorithms:

1. The encryption algorithm specified in the Advanced Encryption Standard

(AES) [NIST 2001], which ensures data confidentiality.

2. The Meyer hash function, which ensures data integrity [MATYAS 1985].

Beginning with the algorithm specification from [NIST 2001] or [MATYAS

1985] students write a behavior VHDL model and simulate it. Then, they
convince themselves that such models raise large problems for synthesis, e.g.
because of too long critical paths or combinatorial loops. Students then refine the
model by adding bit-accurate and cycle-accurate aspects to it. The resulting RTL
model can then be simulated and synthesized. Following this, the design is placed
and routed and finally the bit stream is generated. In between, several timing
analysis steps are performed and different timing constraints are experimented
with. The bit stream is written to the FPGA, which communicates with the host
over a UART interface to exchange data and to verify the functionality.

6. ASSESSMENT
The assessment for our course can be described both as formative and
summative, according to Biggs [Biggs2007]. In the formative assessment, which
is usually applied in the lab, students perform the design assignments described
above to deepen the functioning knowledge. In the lab, students have the
possibility to ask questions and get feedback about their design and the results
reached. Lab assignments are not graded. In this way, we intend that students feel
relaxed in accomplishing the assignments, which is essential for success. The
summative assessment is performed at the end of the semester in form of a
written exam, which takes 90 minutes. In this exam we assess the students to see
whether and how well they acquired the intended functioning and declarative
knowledge. Apparently, the functioning knowledge cannot be assessed
thoroughly in such a short exam. Instead, representative assignments with focus
on essential design aspects are set. We make clear that such assignments are not
evaluated strictly regarding syntax. In real life, advanced editors and compiler
messages assist designers and make learning syntax by rote less necessary. We
expect, for instance, that students declare an array of standard logic vector to
model a memory behavior, which leads to inferring a block RAM by synthesis
program. Forgetting a semi-colon during that or writing stad_logic instead of
std_logic is tolerated. Besides functioning knowledge, the written exam assesses
the declarative knowledge. For this purpose we try to cover as many topics as
possible to prevent chance governing whether a student is successful or not.
Covering several topics in short exam is well done by asking short questions and
false-right or “missing-word” assignments.

As a rule, we present the solution of all assignments and discuss the grading of
each task directly after the exam, usually in the same exam room. This has
several advantages. Students feel relieved, as they can estimate how many points
they will achieve and they do not need to have sleepless nights waiting for their
result. Students perceive the solution presentation as a signal of respect for their
effort, especially as they have the chance to comment on the presented solution
and discuss other alternatives, which may not have crossed our mind. By this
means, we get feedback from students which we consider during evaluating the
exam. Another advantage is that most students know what they wrote, what the
right solutions are, and how many points they will expect. Thus, they ask for an
insight into their exam only if the result does not correspond to this expectation.
This saves their and our time.

In 2007 the exam was written by 25 students and passed by 20 of them, which
corresponds to the general experience with this course. However, the assessment
success rate is not the only signal for achieving the intended learning outcomes.
Rather, a relatively high number of course attendees ask us later to do master and
diploma theses in the field of reconfigurable processors. We can observe that
most those students work on their theses with high interest and independence.
Five running or nearly-completed theses, for example, deal with the design and
implementation of crypto processors for post quantum computer cryptography on
Virtex-5. This research work is being funded by the German Federal Office for
Information Security. Two milestones of this project were already completed
with high success due to the involvement of students, who all learned
reconfigurable design in our course sometime before.

7. COURSE EVALUATION
The Technische Universität Darmstadt has a high-school didactics center
(HDA) for quality assurance in teaching. To assess courses technically and
didactically, the HDA distributes forms which are anonymously filled in by
students. The forms are then evaluated and the results are made available for each
instructor for her or his own courses together with the average of other courses in
the same department and semester. The evaluation form contains various
questions relating to the lecture and the exercise. Each question can be graded by
1 for the best case and 5 for the worst case. For brevity, Table IV shows the
percentage of students, who gave best grade (i.e., 1) for the course
“Reconfigurable Processors” (Column 2). Column 3 shows the average
percentage for all other courses in the department of computer science. The
course was attended by about 25 students, whereas only 19 students filled in the
forms. The relatively lower grades regarding motivation in our course (questions
10 and 17) are very likely because of selecting many case studies and lab
exercises from the field of cryptography. In spite of their sophistication,
cryptographic algorithms do not provide sufficient motivation, apparently. This is
attributed to the fact that a cipher text does have any meaning for a designer.
Therefore, we are planning to update the lab exercises by introducing further,
more interesting topics from the field of DSP or video and audio processing.
 It is worth mentioning that the course was named the best course in the winter
semester 2007/2008 by the student council, which represents student interests in
the department of computer science.

Table IV. Course assessment

Student Average student

percentage gave percentage gave
Question
best mark for the best mark for
course RP other courses

1. The lectures were well structured, a 78.9 25

central theme was obvious
2. The lecturer explained complicated 78.9 16.2
facts in an understandable way
3. The topics were illustrated with 73.7 26.6
examples
4. The lecturer referred to current 68.4 17.7
research
5. The connection between theory and 73.7 20.4
practice was established
68.4 38.1
6. The lecturer was well prepared

7. The lecturer was enthusiastic and 47.4 18.7

managed to fascinate/involve the
auditory
8. Students' questions were answered 73.7 33.8
appropriately
9. The lecturer had regular and 68.4 15.4
sufficiently long office hours
10. The lectures motivated you to occupy 36.8 13.5
yourself with the taught topics
11. The teaching aids (scripts, textbooks,
references to the literature, 68.4 19.7
transparencies) supported your
learning effectively
12. PC­ 73.7 27.7
Presentation/transparencies/writing
on the board supported the lectures
13. The lectures were well organized 68.4 23.5
throughout the semester
14. Which mark would you give the 83.5 16.6
lectures (without exercises)?
57.9 16.1
15. The exercises were clearly structured
 16. You learned a lot through the 47.4 25.7
exercises and assignments
21.1 8.2
17. The exercises were very motivating

18. The topics of the exercises were 68.4 20.3

always well coordinated with the
topics of the lecture
19. The person in charge of the exercises 63.2 28.5
was good
20. The exercises were assisted by 31.6 15.7
electronic platforms (forums, mailing
lists, websites)
21. The room was suitable for working 52.6 22.7
and learning
5.3 14.9
22. The exercises made high demands

23. The exercises (homework, tests) 57.9 13.9

were well organized throughout the
semester
24. Which mark would you give the 52.9 12.3
exercises?

8. CONCLUSION
We presented a course on reconfigurable processors suitable for students of
computer science. In contrast to courses on digital system design, which use
FPGAs as a case platform, our course placed this platform in the center of focus
and highlights its features as a basis for reconfigurable computing. Both
declarative knowledge and functioning knowledge are considered while defining
learning outcomes based on a novel WWH-Model. Lab activities were
designated to deepen the functioning knowledge with tutor feedback. The written
exam is aligned to learning outcomes and shows that most students acquired the
intended outcomes. Relatively high numbers of students are motivated by this
course to do their theses on topics relating to reconfigurable processors.

REFERENCES
ACM. Transactions on Reconfigurable Technology and Systems.
http://trets.cse.sc.edu/index.html

Agility Inc. http://www.agilityds.com/

ASHENDEN, P. 2002. The Designers Guide to VHDL. Morgan Kaufmann ,San Diego, CA.
BAILEY, B., MARTIN, G., AND PIZIALI, A. 2007. ESL Design AND Verification. Morgan Kaufmann, San
Francisco, CA.

B)GGS, J., AND TANG, C. , Teaching for Quality Learning at University. th Edition, McGraw‐(ill
Education, New York, USA.

Cadence. http://www.cadence.com/rl/Resources/white_papers/ )ncisive_ESL.pdf

Digilent Inc. http://www.digilentinc.com/

ECTS: European Credit Transfer and Accumulation System, 2009. ECTS Users’ Guide. Available online at:
http://ec.europa.eu/education/lifelong-learning-policy/doc/ects/guide_en.pdf

GEREZ, S. H. 2005. Algorithms for VLSI Design Automation. John Wiley & Sons Ltd, West Sussex, England.
(reprint with corrections)

GUILLERMO, A.V., PARRA J., KIEF C., PATTICHIS, M., AND POLLARD, H. 2006. Integrating
Reconfigurable Logic in the First Digital Logic Course. In Proceedings of 9th International Conference on
Engineering Education. San Juan, Puerto Ricos, July 2006, T1A1-T1A7.

HALL, T.S., AND HAMBLEN, J.O. 2006. Using FPGAs to Simulate and Implement Digital Design Systems
in the Classroom. In Proceedings of 2000 American Society for Engineering Education Southeastern Setion
Annual Meeting. Tuscaloosa, AL, April 2006.

HAUCK, A., AND DEHON, A. 2007. Reconfigurable Computing. Morgan Kaufmann, Burlington, MA.

IEEE, ACM.Curriculum Guidelines for Undergraduate Degree Programs in Computer Engineering, 2004.
http://www.eng.auburn.edu/ece/CCCE/CCCE-FinalReport-2004Dec12.pdf

IHT. http://www.iht.tu-darmstadt.de/

Intel Corporation 2008. Enabling Consistent Platform-Level Services for Tightly Coupled Accelerators. White
paper 2008. Available on-line at: http://download.intel.com/technology/platforms/quickassist/quickassist_aal_
whitepaper.pdf

LOYA-HERNANDEZ, J.E., GONZALEZ-VAZQUEZ, J.L., AND GARDUNO-MOTA., M.I. 2007. Teaching

Reconfigurable Hardware Using an Interdisciplinary Problem Based Model to Strengthen Digital Systems
Design Skills in Electronic Engineering Undergraduates. In Proceedings of IEEE International Conference on
Microelectronic Systems Education. San Diego, CA, June, 2007.

MATYAS, S., MEYER, C., AND OSEAS 1985. Generating Strong One-Way Functions with Cryptographic
Algorithm. IBM Disclosure Bulletin, 27 (10A): 5658-5659, March 1985.

NIST 2001. U.S. Federal Information Processing Standard. Publication 197. Advanced Encryption Standard
(AES), November 2001.

PACT XPP TECHNOLOGIES. http://www.pactxpp.com/

SHOUFAN, A., LAUE, R., AND HUSS, S. 2007. High-Flexibility Rekeying Processor for Key Management in
Secure Multicast. In Proceedings of IEEE International Symposium on Embedded Computing SEC-07. Niagra
Falls, Canada, May, 2007

SKLYAROV, V., AND SKLIAROVA, I. 2005. Teaching Reconfigurable Systems: Methods, Tools, Tutorials,
and Projects. IEEE Transactions on Education, Vol. 48, NO. 2, May 2005, 290-300.
SMITH, M. J. S. 1997. Application-Specific Integrated Circuits. Addison Wesley.

STANLEY, T.D., XUAN, T.Q., FIFE, L., AND OLTON, D. 2007. Simple Eight Bit, Emulated Computers for
Illustrating Computer Architecture Concepts and Providing a Starting Point for Student Designs. In Proceedings
of 9th Australasian Computing Education Conference. Ballarat, Victoria, Australia, January, 2007.

TANENBAUM, A. S., AND GOODMAN, J. 2001. Computerarchitektur. Prentice Hall, Munich, Germany. (in
German).

TEUSCHER, C., HAENNI, J.O., GOMEZ, F.J., RESTREPO, H.F., AND SANCHEZ, E. 1999.A Tool for
Teaching and Research on Computer Architecture and Reconfigurable Systems. In Proceedings of 25th
Euromicro Conference. Milant, Italy, September, 1999.

TORRESON, J., NORENDAL, J., AND Glette, K. 2007. Establishing a New Course in Reconfigurable Logic
System Design. In Proceedings of 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and
Systems, Krakow, Poland, April 2007, IEEE, 1-4.

TREDENICK, H.L. 2003. The Inevitability of Reconfigurable Systems. ACM Queue, Vol. 1, No. 7, 2003, 21-
38.

Xilinx Inc. http://www.xilinx.com/

ZOMAY. A. Editor . (andbook of )nnovative Computational Paradigms. Chapter . Springer Verlag,

.