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Lab Exercise 2

Intel FPGA DE1-SoC Electronic Hardware Design

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7 views

Lab Exercise 2

Intel FPGA DE1-SoC Electronic Hardware Design

Uploaded by

dhdlrwns123
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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LAB EXERCISE 2

Electronic Hardware Design Lab

September 6, 2024 / KOREA AEROSPACE UNIVERSITY


PART I
 Count the longest string of 1’s in a word.

0110 = r9
0011 = r9>>1
-------------------
0010 = r9  (r9 & r9>>1)
0001 = r9 >> 1
-------------------
0000 = r9 & r9>>1

#2 KOREA AEROSPACE UNIVERSITY


PART II
 Find the longest string of 1’s in multiple words

ONES: /* This subroutine finds the longest string of 1’s in one word*/
/* Make the code provided in Figure 1 a subroutine */
/* Argument (word) is passed by r4, */
/* Return value (count) is passed by r2*/
……….
………..
LOOP:
……….. /*Call ONES iteratively until the end of the words*/

………….
TEST_NUM: .words 0x0000FF00, 0x0000FFA0, 0 /*an example*/
………….
2 words Indicating the end of the words

#3 KOREA AEROSPACE UNIVERSITY


PART IV
 Display the count of the longest string of 1’s on HEX1-0.
 Use the code for Part II in order to find the count of the longest string of
1’s in words.
 Display the resultant count on HEX1-0.

ONES:
……….
………..
LOOP:
……….. /*Call ONES iteratively until the end of the words*/
………..
DISPLAY:
…………
………….
TEST_NUM: .words 0x0000FF00, 0x0000FFA0, 0 /*This is an example*/
………….

#4 KOREA AEROSPACE UNIVERSITY


PART IV, CONT’D

0 1 2 3 4

#5 KOREA AEROSPACE UNIVERSITY


PART IV, CONT’D

#6 KOREA AEROSPACE UNIVERSITY


address_map_nios2.s
/* This files provides address values that exist in the system */

/* Memory */
.equ DDR_BASE, 0x40000000
.equ DDR_END, 0x7FFFFFFF
.equ A9_ONCHIP_BASE, 0xFFFF0000
.equ A9_ONCHIP_END, 0xFFFFFFFF
.equ SDRAM_BASE, 0x00000000
.equ SDRAM_END, 0x03FFFFFF
.equ FPGA_ONCHIP_BASE, 0x08000000
.equ FPGA_ONCHIP_END, 0x0803FFFF
.equ FPGA_CHAR_BASE, 0x09000000
.equ FPGA_CHAR_END, 0x09001FFF

/* Cyclone V FPGA devices */


.equ LEDR_BASE, 0xFF200000
.equ HEX3_HEX0_BASE, 0xFF200020
.equ HEX5_HEX4_BASE, 0xFF200030
.equ HEX7_HEX4_BASE, 0xFF200030 /* Redundant HEX7_HEX4 needed for existing NIOS2 programs. */
.equ SW_BASE, 0xFF200040
.equ KEY_BASE, 0xFF200050
.equ JP1_BASE, 0xFF200060
.equ JP2_BASE, 0xFF200070
.equ PS2_BASE, 0xFF200100
.equ PS2_DUAL_BASE, 0xFF200108
.equ JTAG_UART_BASE, 0xFF201000
.equ JTAG_UART_2_BASE, 0xFF201008
.equ IrDA_BASE, 0xFF201020
.equ TIMER_BASE, 0xFF202000
.equ TIMER_2_BASE, 0xFF202020
.equ AV_CONFIG_BASE, 0xFF203000
.equ PIXEL_BUF_CTRL_BASE, 0xFF203020
.equ CHAR_BUF_CTRL_BASE, 0xFF203030
.equ AUDIO_BASE, 0xFF203040
.equ VIDEO_IN_BASE, 0xFF203060
.equ ADC_BASE, 0xFF204000

/* Cyclone V HPS devices */


.equ HPS_GPIO1_BASE, 0xFF709000
.equ I2C0_BASE, 0xFFC04000
.equ I2C1_BASE, 0xFFC05000
.equ I2C2_BASE, 0xFFC06000
.equ I2C3_BASE, 0xFFC07000
.equ HPS_TIMER0_BASE, 0xFFC08000
.equ HPS_TIMER1_BASE, 0xFFC09000
.equ
.equ
HPS_TIMER2_BASE,
HPS_TIMER3_BASE,
0xFFD00000
0xFFD01000
include this file in your
.equ FPGA_BRIDGE, 0xFFD0501
program.

#7 KOREA AEROSPACE UNIVERSITY

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