4 IOports v21
4 IOports v21
4 IOports v21
Sepehr Naimi
www.NicerLand.com
Topics
AVR pin out
The structure of I/O pins
I/O programming
Bit manipulating
2
I/O unit in AVR
PROGRAM
ROM
Program
Bus Bus
CPU
Interrupt Other
OSC I/O Port
Unit Peripherals
I/O
PINS
3
ATmega328 pinout
+5 V
1. Vital Pins:
1. Power
VCC 28 pin
Ground (PCINT14/RESET) PC6 1 28 PC5 (ADC5/SCL/PCINT13)
4
The structure of I/O pins
777
666
XTAL1 555 PB5 (SCK)
XTAL2 444 PB4 (MISO)
RESET 333 PB3 (MOSI/OC2A)
VCC
DDRx: 7 6 5 4 3 22 2 21 0 PB2 (SS/OC1B)
GND
PORTx: 7 6 5 4 3 12 1 11 0 PB1 (OC1A)
AVCC
PINx: 7 6 5 4 3 02 0 01 0 PB0 (ICP1/CLK0)
PINB
AREF DDRB
Px7 Px6 Px5 Px4 PORTB
Px3 Px2 Px1 Px0
PORTC PORTD
DDRC DDRD
PINC PIND
(ADC0) PC0 PD7 (AIN1)
000 777
(ADC1) PC1 666 PD6 (AIN0)
111
DDRx
(ADC2) PC2 222 555 PD5 (T1) 00 11
DDRx
PORTx
(ADC3) PC3 333 444 PD4 (T0/XCK)
PORTx
00 high
highimpedance Out
Out00
(ADC4/SDA) PC4 4 4 4DDRx.n 333 PD3 (INT1) impedance
(ADC5/SCL) PC5 555 222
PORTx.n 11
PD2 (INT0) pull-up
pull-up Out
Out11
666 111 PD1 (TXD)
777 000
PINx.n PD0 (RXD)
5
Example 1
Write a program that 777
666
DDRx
00 11
DDRx
PORTx
PORTx
00 high
highimpedance
impedance
Out
Out0 0
11 pull-up
pull-up Out
Out1 1
6
Example 2
The following code will toggle all 8 bits of
Port B forever with some time delay
between “on” and “off” states:
7
Example 3
A 7-segment is connected to PORTD.
Display 1 on the 7-segment.
DDRD: 1 1 1 1 1 1 1 1
PORTD: 0 0 0 0 0 1 1 0
ATmega328 0
5 1
LDI R20,0x06 ;R20 = 00000110 (binary) 8 6
PORTD
OUT PORTD,R20 ;PORTD = R20 4 2
LDI R20,0xFF ;R20 = 11111111 (binary)
3
OUT DDRD,R20 ;DDRD = R20
DDRx
L1: RJMP L1 00 11
DDRx
PORTx
PORTx
00 high
highimpedance
impedance
Out
Out0 0
11 pull-up
pull-up Out
Out1 1
8
Example 4
A 7-segment is connected to PORTD.
Display 3 on the 7-segment.
DDRD: 1 1 1 1 1 1 1 1
PORTD: 0 1 0 0 1 1 1 1
ATmega328 0
5 1
LDI R20,0x4F ;R20 = 01001111 (binary) 8 6
PORTD
OUT PORTD,R20 ;PORTD = R20 4 2
LDI R20,0xFF ;R20 = 11111111 (binary)
3
OUT DDRD,R20 ;DDRD = R20
DDRx
L1: RJMP L1 00 11
DDRx
PORTx
PORTx
00 high
highimpedance
impedance
Out
Out0 0
11 pull-up
pull-up Out
Out1 1
9
Example 5: Input
The following code gets the data present at the pins of port C
and sends it to port B indefinitely, after adding the value 5 to
it:
DDRx
ADD R16,R17 ;add 5 to it PORTx 00 11
DDRx
PORTx
OUT PORTB,R16 ;send it to Port0 B high Out
Out0 0
0 highimpedance
impedance
RJMP L2 ;jump L2 1 pull-up Out
1 pull-up Out1 1
10
Pull-up resistor
vcc
1 = Close
PORTx.n 0 = Open
pin n of
port x PINx.n
11
Example
AVR
VCC
PORTC.3
AVR
VCC
PORTC.3
12
I/O bit manipulation programming
SBI and CBI instructions
SBI (Set Bit in IO register)
SBI ioReg, bit ;ioReg.bit = 1
Examples:
SBI PORTD,0 ;PORTD.0 = 1
SBI DDRC,5 ;DDRC.5 = 1
14
Example
Write a program that toggles PORTB.4
continuously.
SBI DDRB,4
L1: SBI PORTB,4
CBI PORTB,4
RJMP L1
15
Example
An LED is connected to each pin of Port D. Write a
program to turn on each LED from pin D0 to pin D7.
Call a delay module before turning on the next LED.
LDI R20, 0xFF
OUT DDRD, R20 ;make PORTD an output port
SBI PORTD,0 ;set bit PD0
CALL DELAY ;delay before next one
SBI PORTD,1 ;turn on PD1
CALL DELAY ;delay before next one
SBI PORTD,2 ;turn on PD2
CALL DELAY
SBI PORTD,3
CALL DELAY
SBI PORTD,4
CALL DELAY
SBI PORTD,5
CALL DELAY
SBI PORTD,6
CALL DELAY
SBI PORTD,7
CALL DELAY
16
SBIC and SBIS
SBIC (Skip if Bit in IO register Cleared)
SBIC ioReg, bit ; if (ioReg.bit = 0) skip next
instruction
Example:
SBIC PORTD,0 ;skip next instruction if PORTD.0=0
INC R20
LDI R19,0x23
17
Example
Write a program to perform the following:
(a) Keep monitoring the PB2 bit until it becomes HIGH;
(b) When PB2 becomes HIGH, write value $45 to Port
C, and also send a HIGH-to-LOW pulse to PD3.
18
Example
VCC
A switch is connected to 4.7k AVR
pin PB0 and an LED to pin PB0
Switch
PB5. Write a program to PB5
19
The structure of I/O pins
RDx
PUD
P
DATA BUS
Q D
DDRxn
Q WR DDRxn
CLK
RESET
DDRx.n
RRx
OUTPUT
PORTx.n
Pxn Q D
PORTxn
Sleep WR PORTxn
Q CLK
PINx.n INPUT
RESET
SYNCHRONIZER
D Q D Q
PINxn
L Q Q RPx
N
RESET RESET
CLKI/O
20
Out 0
RDx
PUD
P
1 1 DATA BUS
Q D 0
DDRxn
Q WR DDRxn
CLK
RESET
RRx
0 0 0 0
Pxn Q D
PORTxn
Sleep WR PORTxn
Q CLK
RESET
SYNCHRONIZER
D Q D Q
PINxn
L Q Q RPx
N
RESET RESET
CLKI/O
21
Out 1
RDx
PUD
P
1 1 DATA BUS
Q D 0
DDRxn
Q WR DDRxn
CLK
RESET
RRx
1 1 1 1
Pxn Q D
PORTxn
Sleep WR PORTxn
Q CLK
RESET
SYNCHRONIZER
D Q D Q
PINxn
L Q Q RPx
N
RESET RESET
CLKI/O
22
The structure of I/O pins
DDRx
00 11
DDRx
PORTx
PORTx
00 high
highimpedance
impedance
Out
Out0 0
RDx
PUD
11 pull-up
pull-up Out
Out1 1 P
DATA BUS
Q D
DDRxn
Q WR DDRxn
CLK
RESET
RRx
Pxn Q D
PORTxn
Sleep WR PORTxn
Q CLK
RESET
SYNCHRONIZER
D Q D Q
PINxn
L Q Q RPx
N
RESET RESET
CLKI/O
23
Input (Tri-state vs. pull up)
RDx
PUD
P
0 0 DATA BUS
Q D
DDRxn
Pull-up WR DDRxn
Q CLK
Resistor
RESET
0 RRx
0
Pxn Q D
PORTxn
WR PORTxn
Q CLK
Sleep RESET
SYNCHRONIZER
0 0 0 0 0
0 D Q D Q
PINxn RPx
N L Q Q
RESET RESET
CLKI/O
The represents how the content of PORTx register affects the pull-up resistor;
while the shows how a data can be read from a pin
24