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Coa lab file 1 - very good file

B.tech (Dr. A.P.J. Abdul Kalam Technical University)

Studocu is not sponsored or endorsed by any college or university

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LABORATORY MANUAL
COMPUTER ORGANIZATION LAB
(KCS- 352)

B. TECH
(II YEAR – ODD SEM)
(2022-23)

DEPARTMENT OF
COMPUTER SCIENCE & ENGINEERING

IMS ENGINEERING COLLEGE

(Affiliated to Dr A P J Abdul Kalam Technical University, Lucknow)
Approved by AICTE - Accredited by NAAC – ‘A’ Grade
NH#24, Adhyatmik Nagar, Ghaziabad, UP, India
www.imsec.ac.in

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PRACTICAL -1

1.1 AIM: Verification of logic gates

Procedure:
1. Identify the pin no’s of the given IC.

2. From the IC No. Find out the type of gate.

3. Check for the proper working of the gate.

4. Connect the circuit as per circuit diagram.

5. For all combination of input condition. Tabulate the output voltage by connecting a
voltmeter at the output end.

6. Verify it with truth Table.

7. Repeat the above procedure for all gates.

Equipment Required & Component Required:

Theory:

• Details of IC used and pin configurations.

• Working of logic gates.

1. OR GATE: Function of OR gate is to give output true when one of the either inputs are
true .In the remaining case output becomes false. Following table justify the statement:-

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2. AND GATE: Function of AND gate is to give the output true when both the inputs are
true. In all the other remaining cases output becomes false. Following table justifies the
statement:-

3. NOT GATE: Function of NOR gate is to reverse the nature of the input .It converts true
input to false and vice versa. Following table justifies the statement :-

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Advanced Gates:

1. XOR GATE: - The function of XOR gate is to give output true only when both the inputs
are true. Following table explain this:-

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Result & Conclusion: All basic Logic Gates are verified.

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1.2 AIM: Verification of Universal gates

Procedure:
1. Identify the pin no’s of the given IC.

2. From the IC No. Find out the type of gate.

3. Check for the proper working of the gate.

4. Connect the circuit as per circuit diagram.

5. For all combination of input condition. Tabulate the output voltage by connecting a
voltmeter at the output end.

6. Verify it with truth Table.

7. Repeat the above procedure for all gates.

Equipment Required & Component Required:

Theory:

• Details of IC used and pin configurations.

• Working of logic gates.

1. NAND GATE: -Function of NAND gate is to give true output when one of the two
provided input are false. In the remaining output is true case .Following table justifies the
statement :-

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2. NOR GATE: - NOR gate gives the output true when both the two provided input are false. In all the
other cases output remains false. Following table justifies the statement :-

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Result & Conclusion: Universal Gates are verified.

DO’s and DONT’s:

1. Read and understand how to carry out an activity thoroughly before coming to the
laboratory.

2. Shut down the machine once you are done using it.

3. Eatables are not allowed in the laboratory.

4. Do not open the system unit casing.

5. Do not touch, connect or disconnect any plug or cable without your faculty/laboratory
technician’s permission.

Viva Questions:
Q1. What is a logic gate? Q2. What are
basic gates?
Q3. Differentiate between NAND & AND gate.
Q4. Which gates are known as universal Gates? And why?

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PRACTICAL - 2
2.1 Aim: Design and implementation of HALF ADDER using basic logicgates.

Equipment & Components Required:

S.No. Equipments Specification Quantity

1 Digital IC Trainer kit - 1
2 Digital Multimeter 1

S.No. Components Specification Quantity

7400, 7402,
7404, 1 each
1 Digital ICs 7408, 7432,
7486.
- 6
2 Patch cords

Theory:

To design and implement half adder using logic gates.

Procedure:
 Identify the pins.
 Connect the circuit as per circuit diagram.
 Obtain outputs with various input combinations.
 Verify it with the Boolean function using truth table

OUTPUTS
INPUT A INPUT B
S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
CIRCUIT DIAGRAM TRUTH TABLE

Result & Conclusion: All logical circuits have been implemented & verified through truth
table.

2.2 Aim: Design and implementation of FULL ADDER using basic logic gates.

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Equipment & Components Required:

S.No. Equipments Specification Quantity

1 Digital IC Trainer kit - 1
2 Digital Multimeter 1

S.No. Components Specification Quantity

7400, 7402,
7404, 1 each
1 Digital ICs 7408, 7432,
7486.
- 6
2 Patch cords

Procedure:
 Identify the pins.
 Connect the circuit as per circuit diagram.
 Obtain outputs with various input combinations.
 Verify it with the Boolean function using truth table

Theory:

To design and implement FULL adder using logic gates

FULL ADDER:

CIRCUIT DIAGRAM

TRUTH TABLE

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Result & Conclusion: All logical circuits have been implemented & verified through truth
table.

VIVA QUESTIONS
Q.1 What are the applications of half adder?
Q.2 Explain the advantages of half adder?
Q.3 What are the applications of full adder?
Q.4 Elaborate the advantages of full adder over half adder.

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PRACTICAL -3
Aim: Design and implementation of Binary to Gray, Gray to Binary Code conversions.

Equipment & Components Required:

Procedure:
 Collect the components necessary to accomplish this experiment.
 Plug the IC chip into the breadboard.
 Connect the supply voltage and ground lines to the chips. PIN7 = Ground and PIN14=+5v
 Make connections as shown in the respective circuit diagram.
 Connect the inputs of the gate to the input switches of the LED.
 Connect the output of the gate to the output LEDs.
 Once all connections have been done, turn on the power switch of the breadboard
 Operate the switches and fill in the truth table (Write "1" if LED is ON and "0" if
L1is OFF Apply the various combination of inputs according to the truth table and
observe the condition of Output LEDs.
Theory:

a) To design and implement Binary to Gray Code conversions

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Pin diagram of Binary to gray code converter using 7486 IC(Ex-Or Gate)

INPUT OUTPUT
A B C D G4 G3 G 2 G1
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
Truth Table

b) To design and implement Binary to Gray Code conversions

Pin diagram of Gray to Binary code converter using 7486 IC (Ex-Or Gate)

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INPUTS OUTPUTS

A B C D B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
Circuit Diagram for Gray to Binary Code 1 1 1 1 1 0 1 0
Converter 1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
T
TRUTH TABLE

Result & Conclusion: Binary to gray and gray to binary code converter has been designed
using EXOR gate and its truth table verified.

VIVA QUESTION:
Q.1 What is a code converter?
Q.2 Differentiate between translator and code converter.
Q.3 Explain the primary usage of grey code.
Q.4 Illustrate the reasons for using grey code.

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PRACTICAL - 4
Aim: Design and implementation of 3–8-line DECODER.

Equipment’s & Components Required:

S.No. Equipment’s Specification Quantity

1 Digital IC Trainer - 1
kit
2 Digital Multimeter 1

S.No. Components Specification Quanti

ty
7400, 7402,
7404,
1 Digital ICs 1 each
7408, 7432,
7486.
2 Patch cords - 6

Procedure:
 Collect the components necessary to accomplish this experiment.
 Plug the IC chip into the breadboard.
 Connect the supply voltage and ground lines to the chips. PIN7 = Ground
 and PIN14 = +5V.
 Make connections as shown in the respective circuit diagram.
 Connect the inputs of the gate to the input switches of the LED.
 Connect the output of the gate to the output LEDs.
 Once all connections have been done, turn on the power switch of the breadboard
 Operate the switches and fill in the truth table ( Write "1" if LED is ON and "0" if
L1is OFF Apply the various combination of inputs according to the truth table and
observe the condition of Output LEDs.

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Theory:
3 to 8 decoder using logic gates:

Symbol:
Truth table:

Circuit Diagram of 3:8 Decoder

Viva Questions:

Q1. How to use math module for finding square root of a

number? Q2. What is user defined function?
Q3. What is Lambda Function?
Q4. What are higher order functions?
Q5. List some inbuilt higher order functions.

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PRACTICAL – 5
Aim: Design and implementation of 3–8-line DECODER, 4x1 MUX and 8x1
MULTIPLEXERS

Procedure:

• Collect the components necessary to accomplish this experiment.

• Plug the IC chip into the breadboard.

• Connect the supply voltage and ground lines to the chips. PIN7 = Ground

• and PIN14 = +5V.

• Make connections as shown in the respective circuit diagram.

• Connect the inputs of the gate to the input switches of the LED.

• Connect the output of the gate to the output LEDs.

• Once all connections have been done, turn on the power switch of the breadboard

• Operate the switches and fill in the truth table ( Write "1" if LED is ON and "0" if
L1 is OFF Apply the various combination of inputs according to the truth table and
observe the condition of Output LEDs.

Equipment Required:- Digital trainer kit, AND-7411, OR-7432, NOT-7404 Gate IC,
Connecting wires.

Theory:-
4 to 1 MULTIPLEXER: -A multiplexer (MUX) is a device that accepts data from one of
many input sources for transmission over a common shared line. To achieve this MUX has
several data lines and a single output along with data-select inputs, which permit digital data
on any of the inputs to be switched to the output line. The logic symbol for a 1 to 4 data
selector/multiplexer is shown in Figure

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The selection lines decide the number of inputs lines of particular multiplexer. If the number
of n inputs lines is equal to 2m, then m select lines are required to select one of the n input
line. Note that if a binary zero appears on the data-select lines then data on input line D0 will
appear on the output. Thus, data output Y is equal to D0 if and only if S1=0 and S0=0.
Y=D0.S1’.S0’Similarly, the data output is equal to D1, D2 and D3 for y=C1.S1’.S0’
,Y=C2.S0’. S1 and Y=C3.S0.S1 respectively. Thus the total multiplexer logic expression,
formed from ORing terms.
The implementation of this equation is as shown in figure:

8 to 1 MULTIPLEXER: -A multiplexer (MUX) is a device that accepts data from one of

many input sources for transmission over a common shared line. In 8 x 1 Multiplexer, 8
represents number of inputs and 1 represents output line. So three (3) select lines are required
to select one of the inputs.

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Truth Table of 8:1 MUX

Result & Conclusion: 4x1 and 8x1 Mux have been implemented & verified through
truth table .

Viva Questions:
Q1. Explain the need of multiplexer.
Q2. Which is the major functioning responsibility of the multiplexing combinational
circuit? Q3. How many NOT gates are required for the construction of a 4-to-1 multiplexer
Q4. In 1-to-4 multiplexer, how many select lines are required?
Q5.In 1-to-8 multiplexer, how many select lines are required?

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PRACTICAL – 6
Aim:- Verify the excitation table of various FLIP-FLOPS

Procedure:

• Collect the components necessary to accomplish this experiment.

• Plug the IC chip into the breadboard.

• Connect the supply voltage and ground lines to the chips. PIN7 =

Ground and PIN14 = +5V.

• Make connections as shown in the respective circuit diagram.

• Connect the inputs of the gate to the input switches of the LED.

• Connect the output of the gate to the output LEDs.

• Once all connections have been done, turn on the power switch of the breadboard

• Operate the switches and fill in the truth table ( Write "1" if LED is ON and "0" if
L1 is OFF Apply the various combination of inputs according to the truth table and
observe the condition of Output LEDs.

Equipments & Components Required:

Theory:

Flip-flops are synchronous bi-stable devices. The term synchronous means the output
changes state only when the clock input is triggered. That is, changes in the output occur in
synchronization with the clock. A flip-flop circuit has two outputs, one for the normal value

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and one for the complement value of the stored bit. Since memory elements in sequential
circuits are usually flip-flops, it is worth summarizing the behaviour of various flip-flop types
before proceeding further. All flip -flops can be divided into four basic types: SR, JK, D and
T. They differ in the number of inputs and in the response invoked by different value of input
signals. The four types of flip -flops are defined in the Table below.

State Table: -The state table representation of a sequential circuit consists of three sections
labelled present state next state and output. The present state designates the state of flip -flops
before the occurrence of a clock pulse. The next state shows the states of flip-flops after the
clock pulse, and the output section lists the value of the output variables during the present
state.
Flip-Flop:-The basic one bit digital memory circuit is known as flip-flop.It can store either 0
or 1. Flip-flops are classifieds according to the number of inputs.

1. R-S Flip-Flop:- The circuit is similar to SR latch except enable signal is replaced by clock
pulse.

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2. D Flip-Flop:-The modified clocked SR flip-flop is known as D-flip-flop.From the truth

table of SR flip-flop we see that the output of the SR flip-flop is in unpredictable state when
the inputs are same and high. In many practical applications, these input conditions are not
required. These input conditions can be avoided by making then complement of each other.

3. J-K Flip-Flop:- In a RS flip-flop the input R=S=1 leads to an indeterminate output. The
RS flip-flop circuit may be re-joined if both inputs are 1 than also the outputs are complement
of each other.

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4. T Flip-Flop:-T flip-flop is known as toggle flip-flop. The T flip-flop is

modification of theJ-K flip-flop . Both the J K inputs of the J K flip -flop are held
at logic 1 and the clock signalcontinuous to change.

Result & Conclusion: Verified excitation table of various flip flops.

Viva Questions:

Q1. How is a JK Flip Flop made to toggle?

Q2. How many stable states does a Flip Flop has?
Q3. What is the significance of the J and K terminals on the JK flip-
flop?
Q4. The truth table for an S-R flip-flop has how many VALID

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PRACTICAL – 7
Aim: Design and implement 8-bit Input/Output System with four 8-bit internal registers

Procedure:
 Connections are given as per circuit diagram.
 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.

Equipment’s & Components Required:

S.No. Equipments Specification Quantity

1 Logic Simulator - 1

S.No. Component Specification Qty.

1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 15

Theory:
A register is capable of shifting its binary information in one or both directions is
known as shift register. The logical configuration of shift register consist of a D-Flip
flop cascaded with output of one flip flop connected to input of next flip flop. All
flip flops receive commonclock pulses which causes the shift in the output of the
flip- flop. The simplest possible shift register is one that uses only flip flop. The
output of a given flip flop is connected to the input of next flip flop of the register.
Each clock pulse shifts the content of register one bit position to right.

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8-Bit Input/Output System With Four 8-Bit

Internal Register

Result & Conclusion: Verified 8-bit Input/Output System with four 8-bit
internal registerson simulator.

Viva Questions:

Q.1 What are the advantages of using bus

interface?
Q.2 Define an Internal register?
Q.3 How many types of registers are there?

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PRACTICAL – 8

AIM: - Design of an 8- bit ARITHMETIC LOGIC UNIT.

Procedure:

• Connections are given as per circuit diagram.

• Logical inputs are given as per circuit diagram.

• Observe the output and verify the truth table.

Theory:

ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic operations like addition,
subtraction, division, multiplication and logical operations like and, or, xor, nand, nor etc. A
simple block diagram of a 4-bit ALU for operations and, or, xor and add is shown in the
Logic diagram.

LOGIC DIAGRAM:

Design Issues:

The circuit functionality of a 1 bit ALU is shown here, depending upon the control signal S1
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and S0 the circuit operates as follows:

for Control signal S1 = 0 , S0 = 0, the output is A And B, for Control signal S1 = 0 , S0 = 1,

the output is A Or B, for Control signal S1 = 1 , S0 = 0, the output is A Xor B, for Control
signal S1 = 1 , S0 = 1, the output is A Add B.

The truth table for 16-bit ALU with capabilities similar to 74181 is shown

here: Required functionality of ALU (inputs and outputs are active high)

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Viva Questions:
Q1. What are the functions of a an ALU?
Q2. How does an ALU work?
Q3. Describe the components of ALU.
Q4. What are the basic operations of I/O unit?
Q5: What are the functions of a CPU?

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PRACTICAL – 9

Aim:-: Design the data path of a computer from its register transfer language description.

This datapath circuit to be built requires several components that we will design and implement
and test individually. To facilitate successful implementation, verification and documentation of
complex designs, one should proceed in an incremental, modular fashion whereby each
component of a circuit is built and verified independently. The components are then put
together and may form another, larger component at the next level of the design hierarchy.
These combined components may then be combined to from even larger components and so on.
This continues to the top level of the design. This practice applies to the design of hardware,
software or any other system for that matter! Our final goal here is to design and implement the
logic for a hardware datapath that contains a simple arithmetic and logic unit (ALU) that can
perform low level processing.

Step 1 Decoder The register file requires a 2‐line to 4‐line decoder with HI‐true outputs and one
HI‐true enable input as shown in the circuit of Step 4. This is similar to the decoder you
designed in a previous lab. Implement this component using the graphic design editor and test it
in the MAX7000 device.

Step 2 Quad 4:1 MUX The register file also requires a Quad 4:1 multiplexer. A Quad 4:1 MUX
has four 4‐bit data inputs, a 4‐bit data output and two select lines as shown below. Study the
VHDL source code given at the end of this lab that implements a Quad 4:1 multiplexer. Be sure
you understand the logic of the VHDL code. Compile this program, implement and test using
the MAX7000 device. Generate a symbol for this MUX which you will use later.

Step 3 Registers The four registers R0, R1, R2 and R3 in the diagram below are to be
implemented using the VHDL code at the end of this lab. Each register comprises 4 positive
edge‐triggered D flipflops. Each register has a 4‐bit input data and a 4‐bit output data. The clock
input to all flipflops in the register is defined as Clk. Compile this code and make a symbol for
the register.

Step 4 Register File Now we will design the register file using the graphic design editor by
connecting the multiplexer, decoder and four registers as shown below. Compile and test the
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register file circuit in the MAX7000 chip to ensure that all four registers can be loaded using
toggle switches on the Data In lines, and read using LEDs connected at the Data Out lines. Be
sure that you understand the timing of the "load enable" input relative to all the other inputs and
outputs.

Step 5 Datapath
The register file forms the basis of a "datapath" which is a fundamental building block of a
computer. See the diagram below. Data is selected from any register then stored back into any
other register in the register file, all in a single clock cycle ( a lo‐hi‐lo pulse applied to the load
enable LE input). A Quad 2:1 MUX included as shown below allows external data to be
inserted into the datapath. Data can thus be transferred between any two registers of our register
file or any register can be loaded with external data. This datapath can execute the following
operations:
(a) any register can be loaded with external data from switches Rd ← data (4‐bits) (where
d=0,1,2 or 3)
(b) any register can be loaded with the data contained in any one of the other registers,
including itself (register‐to‐register transfer) Rd ← Rs (where d, s = 0, 1, 2 or 3) The
implementation is shown below. The inputs [ D1, D0, S1, S0, DS ] form a 5‐bit
"control" word which specifies the source (S1, S0) and destination (D1, D0) registers of
the register file and an operation (DS) that is to take place. For DS=0, external data from
switches is loaded into the destination register; for DS=1, data is transferred from the
source register to the destination register. Once the control word and data input (if
appropriate) are set on the level switches, execution is achieved by applying a load
enable (LE) input to the register file. This LE input may be considered as the clock to
the entire system. You can view the results of each operation using four LEDs connected
to the output of the register file as shown. Design this data path using the graphic design
editor. VHDL code for the Quad 2:1 MUX design is given at the end of this lab. Test the
circuit for various combinations of the register transfers summarized in the following
table.

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Summary of register transfer operations:

Note: (1) the first four lines of this table allow for initializing the register contents ( DS = 0 ).
(2) this is not a complete table of all possible microoperations that can execute

The VHDL source code for Quad 4:1 MUX

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY quad4to1mux IS
PORT ( a, b, c, d : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
f : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END quad4to1mux ;
ARCHITECTURE Behavior OF quad4to1mux IS
BEGIN
WITH s SELECT
f <= a WHEN "00",
b WHEN "01",
c WHEN "10",
d WHEN OTHERS ;
END Behavior ;

The VHDL source code for 4-bit Register

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY reg4 IS
PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
Clk : IN STD_LOGIC ;
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Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );

END reg4 ;
ARCHITECTURE Behavior OF reg4 IS
BEGIN
PROCESS (Clk)
BEGIN
IF Clk'EVENT AND Clk = '1' THEN Q <= D;
END IF;
END PROCESS ;
END Behavior ;
The VHDL source code for Quad 2:1 MUX
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY quad2to1mux IS
PORT ( a, b : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
s : IN STD_LOGIC ;
f : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END quad2to1mux ;
ARCHITECTURE Behavior OF quad2to1mux IS
BEGIN
f <= a WHEN s='0' ELSE b ;
END Behavior ;

Viva Questions:

1. RTL stands for _______________

2. What do you mean by datapath?
3. How many sources and destination register are required while register transfer operation
4. Why MUX is required while creating datapath

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PRACTICAL – 10

Aim: Design the Control Unit of a computer using either hardwiring or

microprgramming based on its register transfer language description.

BRIEF THEORY
The purpose of this laboratory is to design and implement the control unit to provide control
signals to the 32-bit CPU data-path.

The purpose of this laboratory is to design and implement the control unit to provide control
signals to the 32-bit CPU data-path. Most of the control unit outputs all the control signals for
the Registers, ALU and MUXes in the datapath. It accepts as input the status bits (Zero and
Carry) and the INST for instruction decisions (Note: the diagram shows the entire INST as input
to the control unit. However, if we refer back to the CPU specification document, only
INST[31..28] – opcode e - and INST[27..24] - function code - arerequired). All instructions
require 3 clock cycles to execute. Moreover, in situations when we desire toinitialize or reset the
CPU, an enable/reset input t is needed.
Please note that a control signal required by the data-path, CLR PC is not produced by the
control unit.The clearing of the program counter occurs during initialization. Reset signal for
the CPU and CLR PC are generated by a reset circuit.
When we investigate the internal structure of the control unit, it can be divided it into three parts
(VHDL processes), namely a sequential state generator (for T0, T1 and T2), a memory signal
generator (for wen and en setup and hold times), and a combinational circuit for the decoding
operations. A brief description of these processes is given below.
State Generator
The state generator circuit is the synchronous, sequential component of the control unit. It
generates appropriate state signals based on the clock and the current state of the system. It also
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generates a set of pulse signals T that can be used to indicate the current state of the instruction
being executed. (shown here for three states).

Note: When ENABLE signal is not asserted, the circuit should go to state T0 and remain in
this state until the ENABLE signal is asserted again. At that point, the circuit resumes
normal operation.

Operation Decoder
The operation decoder is responsible for correctly setting the control signals being fed to the
data- path during instruction execution. It requires the current state, status bits (C and Z) and the
INST contents to determine which instruction to execute. Essentially, the operation decoder is
nothing more than an if else type of statement (MUX), which sets the control signals
appropriately. We have determined the correct settings of the control signals for each operation
in the data-path lab. Note that it is wise to use case statements to successfully synthesize the
VHDL for decoding all the CPU instructions.

Memory Signal Generator

To support the load and store instructions, the Write Enable (wen) and Enable (en) signals have
been included in the control unit specification. Assume the signal is active high; the signal must
be asserted correctly during the store and load operations as specified in memory lab manual
and cpu_specification document. The wen and en are sensitive to the Clk, mclk, and INST
given. The process template is given in the code on the next page for setting up "en" and "wen"
in the "Data Memory Instructions" process. Fill in the code with the appropriate values for "en"
and "wen" according to the template given in the specifications to achieve correct setup and
hold times for your CPU's memory operations.

VHDL Implementation
The declaration below is provided as a possible reference:
library ieee;
use ieee.std_logic_1164.ALL;
ENTITY control IS
PORT(
clk, mclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
statusC, statusZ : IN STD_LOGIC;
INST : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
A_Mux, B_Mux : OUT STD_LOGIC;
IM_MUX1, REG_Mux : OUT STD_LOGIC;
IM_MUX2, DATA_Mux : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ALU_op : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
inc_PC, ld_PC : OUT STD_LOGIC;
clr_IR : OUT STD_LOGIC;
ld_IR : OUT STD_LOGIC;
clr_A, clr_B, clr_C, clr_Z : OUT STD_LOGIC;
ld_A, ld_B, ld_C, ld_Z : OUT STD_LOGIC;
T : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
wen, en : OUT STD_LOGIC);
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END control;
ARCHITECTURE description OF control IS TYPE STATETYPE IS (state_0, state_1, state_2,
etc...); SIGNAL present_state: STATETYPE;
BEGIN
-------- OPERATION DECODER ---------
PROCESS (present_state, INST, statusC, statusZ, enable)
BEGIN
-------- YOU FILL IN WHAT GOES IN HERE (DON'T FORGET TO CHECK FOR
ENABLE)
-------- OUTPUT ASSIGNMENTS
END process;
-------- STATE MACHINE ---------
PROCESS (clk, enable)begin
-------- YOU FILL IN WHAT GOES IN HERE
END process;
-------- DATA MEMORY INSTRUCTIONS ---------
PROCESS (mclk, clk, INST)
BEGIN
IF(mclk'EVENT and mclk = '0') THEN
IF(present_state = state_1 AND clk = '0') THEN
--LDA and LDB Signals
--STA and STB Signals
--Default Case Signals
ELSIF(present_state = state_2 AND clk = '1') THEN
--LDA and LDB
--STA and STB
--Default Case ELSIF(present_state = state_1) THEN --or alternatively just an ELSE statement
--fill in
END IF;
END IF;
END process;
END description;

Viva questions:

1. What is Hardwired control unit.

2. What is microprogrammed based control unit.
3. Differentiate between hardwired and microprogrammed based CU.
4. What is the function of state generator?

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PRACTICAL – 11

Aim: Implement a simple instruction set computer with a control unit and a data path.
Theory: -

We will examine the MIPS implementation for a simple subset that shows most aspects of
implementation. The instructions considered are:
• The memory-reference instructions load word (lw) and store word (sw)
• The arithmetic-logical instructions add, sub, and, or, and slt
• The instructions branch equal (beq) and jump (j) to be considered in the end.
This subset does not include all the integer instructions (for example, shift, multiply, and divide
are missing), nor does it include any floating-point instructions. However, the key principles
used in creating a datapath and designing the control will be illustrated. The implementation of
the remaining instructions is similar.
When we look at the instruction cycle of any processor, it should involve the following
operations:
• Fetch instruction from memory
• Decode the instruction
• Fetch the operands
• Execute the instruction
Write the result
We shall look at each of these steps in detail for the subset of instructions For every instruction,
the first two steps of instruction fetch and decode are identical: Send the program counter (PC)
to the program memory that contains the code and fetch the instruction.
Read one or two registers, using the register specifier fields in the instruction. For the load word
instruction, we need to read only one register, but most other instructions require that we read
two registers. Since MIPS uses a fixed length format with the register specifiers in the same place,
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the registers can be read, irrespective of the instruction.

After these two steps, the actions required to complete the instruction depend on the type of
instruction. For each of the three instruction classes, arithmetic/logical, memory-reference and
branches, the actions are mostly the same. Even across different instruction classes there are
some similarities.
A memory-reference instruction will need to access the memory. For a load instruction, a
memory read has to be performed. For a store instruction, a memory write has to be performed.
An arithmetic/logical instruction must write the data from the ALU back into a register. A load
instruction also has to write the data fetched form memory to a register. Lastly, for a branch
instruction, we may need to change the next instruction address based on the comparison. If the
condition of comparison fails, the PC should be incremented by 4 to get the address of the next
instruction. If the condition is true, the new address will have to updated in the PC. However,
wherever we have two possibilities of inputs, we cannot join wires together.
We also need to include the necessary control signals. Figure below shows the datapath, as well
as the control lines for the major functional units. The control unit takes in the instruction as an
input and determines how to set the control lines for the functional units and two of the
multiplexors. The third multiplexor, which determines whether PC + 4 or the branch destination
address is written into the PC, is set based on the zero output of the ALU, which is used to
perform the comparison of a branch on equal instruction. The regularity and simplicity of the
MIPS instruction set means that a simple decoding process can be used to determine how to set
the control lines.

Figure: Datapath, as well as the control lines for the major functional units

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Just to give a brief section on the logic design basics, all of you know that information is
encoded in binary as low voltage = 0, high voltage = 1 and there is one wire per bit. Multi-bit
data are encoded on multi-wire buses. The combinational elements operate on data and the
output is a function of input. In the case of state (sequential) elements, they store information
and the output is a function of both inputs and the stored data, that is, the previous inputs.
Examples of combinational elements are AND-gates, XOR-gates, etc. An example of a
sequential element is a register that stores data in a circuit. It uses a clock signal to determine
when to update the stored value and is edge-triggered.
Now, we shall discuss the implementation of the datapath. The datapath comprises of the
elements that process data and addresses in the CPU – Registers, ALUs, mux’s, memories, etc.
We will build a MIPS datapath incrementally. We shall construct the basic model and keep
refining it.
The portion of the CPU that carries out the instruction fetch operation is given in following figure:

Figure: Schematic high-level diagram of MIPS datapath from an implementational

perspective

As mentioned earlier, The PC is used to address the instruction memory to fetch the instruction.
At the same time, the PC value is also fed to the adder unit and added with 4, so that PC+4,
which is the address of the next instruction in MIPS is written into the PC, thus making it ready
for the next instruction fetch.

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The next step is instruction decoding and operand fetch. In the case of MIPS, decoding is done
and at the same time, the register file is read. The processor’s 32 general-purpose registers are
stored in a structure called a register file. A register file is a collection of registers in which any
register can be read or written by specifying the number of the register in the file.
The R-format instructions have three register operands and we will need to read two data words
from the register file and write one data word into the register file for each instruction. For each
data word to be read from the registers, we need an input to the register file that specifies the
register number to be read and an output from the register file that will carry the value that has
been read from the registers. To write a data word, we will need two inputs- one to specify the
register number to be written and one to supply the data to be written into the register. The 5-bit
register specifiers indicate one of the 32 registers to be used.
The register file always outputs the contents of whatever register numbers are on the Read
register inputs. Writes, however, are controlled by the write control signal, which must be
asserted for a write to occur at the clock edge. Thus, we need a total of four inputs (three for
register numbers and one for data) and two outputs (both for data), as shown in Figure 8.6. The
register number inputs are 5 bits wide to specify one of 32 registers, whereas the data input and
two data output buses are each 32 bits wide.
After the two register contents are read, the next step is to pass on these two data to the ALU
and perform the required operation, as decided by the control unit and the control signals. It
might be an add, subtract or any other type of operation, depending on the opcode. Thus the
ALU takes two 32-bit inputs and produces a 32-bit result, as well as a 1-bit signal if the result is
0. The control signals will be discussed in the next module. For now, we will assume that the
appropriate control signals are somehow generated.
The same arithmetic or logical operation with an immediate operand and a register operand, uses
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the I-type of instruction format. Here, Rs forms one of the source operands and the immediate
component forms the second operand. These two will have to be fed to the ALU. Before that,
the 16-bit immediate operand is sign extended to form a 32-bit operand. This sign extension is
done by the sign extension unit

We shall next consider the MIPS load word and store word instructions, which have the general
form lw $t1,offset_value($t2) or sw $t1,offset_value ($t2). These instructions compute a
memory address by adding the base register, which is $t2, to the 16-bit signed offset field
contained in the instruction. If the instruction is a store, the value to be stored must also be read
from the register file where it resides in $t1. If the instruction is a load, the value read from
memory must be written into the register file in the specified register, which is $t1. Thus, we
will need both the register file and the ALU. In addition, the sign extension unit will sign extend
the 16-bit offset field in the instruction to a 32-bit signed value. The next operation for the load
and store operations is the data memory access. The data memory unit has to be read for a load
instruction and the data memory must be written for store instructions; hence, it has both read
and write control signals, an address input, as well as an input for the data to be written into
memory. Figure 8.7 above illustrates all this.
The branch on equal instruction has three operands, two registers that are compared for equality,
and a 16-bit offset used to compute the branch target address, relative to the branch instruction
address. Its form is beq $t1, $t2, offset. To implement this instruction, we must compute the
branch target address by adding the sign- extended offset field of the instruction to the PC. The
instruction set architecture specifies that the base for the branch address calculation is the
address of the instruction following the branch. Since we have already computed PC + 4, the
address of the next instruction, in the instruction fetch datapath, it is easy to use this value as
the base for
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computing the branch target address. Also, since the word boundaries have the 2 LSBs as zeros
and branch target addresses must start at word boundaries, the offset field is shifted left 2 bits.
In addition to computing the branch target address, we must also determine whether the next
instruction is the instruction that follows sequentially or the instruction at the branch target
address. This depends on the condition being evaluated. When the condition is true (i.e., the
operands are equal), the branch target address becomes the new PC, and we say that the branch
is taken. If the operands are not equal, the incremented PC should replace the current PC (just
as for any other normal instruction); in this case, we say that the branch is not taken.

Thus, the branch datapath must do two operations: compute the branch target address and
compare the register contents. This is illustrated in Figure 8.8. To compute the branch target
address, the branch datapath includes a sign extension unit and an adder. To perform the
compare, we need to use the register file to supply the two register operands. Since the ALU
provides an output signal that indicates whether the result was 0, we can send the two register
operands to the ALU with the control set to do a subtract. If the Zero signal out of the ALU unit
is asserted, we know that the two values are equal. Although the Zero output always signals if
the result is 0, we will be using it only to implement the equal test of branches. Later, we will
show exactly how to
connect the control signals of the ALU for use in the datapath.
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Now, that we have examined the datapath components needed for the individual instruction
classes, we can combine them into a single datapath and add the control to complete the
implementation. Following is the combined datapath:

The simplest datapath might attempt to execute all instructions in one clock cycle. This means
that no datapath resource can be used more than once per instruction, so any element needed
more than once must be duplicated. We therefore need a memory for instructions separate from
one for data. Although some of the functional units will need to be duplicated, many of the
elements can be shared by different instruction flows. To share a datapath element between two
different instruction classes, we may need to allow multiple connections to the input of an
element, using a multiplexor and control signal to select among the multiple inputs. While
adding multiplexors, we should note that though the operations of arithmetic/logical ( R-type)
instructions and the memory related instructions datapath are quite similar, there are certain key
differences.
The R-type instructions use two register operands coming from the register file. The memory
instructions also use the ALU to do the address calculation, but the second input is the sign
extended 16-bit offset field from the instruction.
The value stored into a destination register comes from the ALU for an R-type instruction,
whereas, the data comes from memory for a load.
To create a datapath with a common register file and ALU, we must support two different
sources for the second ALU input, as well as two different sources for the data stored into the
register file. Thus, one multiplexor needs to be placed at the ALU input and another at the data
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the register file, as shown in following figure:

Result:- Implementation of simple instruction set is verified from this output working

Viva Questions:

1. What is instruction set?

2. How many steps are there in instruction cycle?
3. Why PC value is added with 4
4. What do you mean by branch instruction datapath?

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Computer Organization Lab (KCS352)

1. Implementing HALF ADDER, FULL ADDER using basic logic gates

2. Implementing Binary -to -Gray, Gray -to -Binary code conversions.
3. Implementing 3-8 line DECODER.
4. Implementing 4x1 and 8x1 MULTIPLEXERS.
5. Verify the excitation tables of various FLIP-FLOPS.
6. Design of an 8-bit Input/ Output system with four 8-bit Internal Registers.
7. Design of an 8-bit ARITHMETIC LOGIC UNIT.
8. Design the data path of a computer from its register transfer language description.
9. Design the control unit of a computer using either hardwiring or microprogramming based on
its register transfer language description.
10. Implement a simple instruction set computer with a control unit and a data path.

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