DIGITAL DESIGN

INTRODUCTION

A system is a set of related components that work as a whole to achieve a goal. A system contains
inputs, behavior and outputs.

Generally, signals are represented by two methods, i.e., Digital and Analog System. Digital Signal
is limited to only a few possible values, generally represented by Binary logic 0 (0 – 0.8 volts) and
logic 1 (2.0 – 5.0 volts). Whereas Analog Signal varies continuously.

Important characteristics of digital system are as following below:

● Data is represented in a digital system as a vector of binary variables.
● Digital Systems can provide accuracy (dynamic range) limited only by the number of
bits used to represent a variable
● Digital systems are less prone to error than analog systems.
● Data representation in a digital system is suitable for error detection and correction.
● Digital systems are designed in a hierarchical manner using re-usable modules.
Benefits of Digital over Analog System:
There are some reasons why we use Digital representation than Analog System:

● It is economical and easy to design.

● It is very well suited for both numerical and non-numerical information processing.
● It has high noise immunity.
● It is easy to duplicate similar circuits and complex digital ICs are manufactured with the
advent of microelectronics Technology.
● Adjustable precision and easily controllable by Computer.
 NUMBER SYSTEMS
A digital system can understand a positional number system only where there are a few symbols
called digits and these symbols represent different values depending on the position they occupy in
the number.
A value of each digit in a number can be determined using

● The digit
● The position of the digit in the number
● The base of the number system (where base is defined as the total number of digits
available in the number system).
Types of number system:
1. Decimal number system:
This number system is used in our daily life. Every number system has a base value to represent
which number system the given number belongs to. So the base of the decimal numbers is 10.
The numbers start from 0, so the range of numbers in the decimal system is 0 – 9.

2. Binary number system:

This number system is used by computer architecture. Every number system has a base value to
represent which number system the given number belongs to. So the base of the binary numbers is
2.
It has only 2 values of numbers i.e. 0 and 1.

3. Octal number system:

Every number system has a base value to represent which number system the given number belongs
to. So the base of the octal numbers is 8.
The numbers start from 0, so the range of binary numbers is 0-7.

4. Hexa decimal number system:

Every number system has a base value to represent which number system the given number belongs
to. So the base of the hexa decimal numbers is 16.
This number system has a mixture of numbers and characters.
First 10 digits are numbers and the next 6 are characters.
So the range of representing is 0-9 and from 10 to 15 it is from A-F.
 Number system conversion:
1. Decimal to any other number system:
steps to convert:
step 1 : divide the given decimal number by the base number of the number system to which you
are converting.
Step 2: Divide till it is non divisble
step 3: Each time the number is divided write the reminder as the answer from bottom to top.
Step 4: If the floating number is given the numbers after the decimal is multiplied by the base
number to which you are converting to.

a. binary system:
example: Let us say given number (14.25)10
Division result Reminder
14/2 7 0
7/2 3 1
3/2 1 1
1/2 0 1

Multiplication result Binary number

0.25* 2 0.50 0
0.5*2 1.0 1
0.0*2 0 0
so the binary representation of (14.25)10 is (1110.010)2
b. octal system:
example: Let us say given number (24.25)10
Division result Reminder
24/8 3 0
3 3
Multiplication result Binary number
0.25* 8 1.8 1
0.8*8 6.4 6
so the octal representation of (24.25)10 is (30.16)8
c Hexa decimal system:
example: Let us say given number (84)10
Division result Reminder
84/16 5 4
5 5 5
so the octal representation of (84)10 is (54)16
2. Any other number system to decimal:
steps 1: write the given number from one's to highest power of the given number system base value.
Step 2: multiply each digit by the power of base.
Step 3: Add the obtained result.
a. Binary system:
example : convert (1001)2
1*2^3 + 0*2^2 + 0*2^1 + 1*2^0
1*8 + 0*4 + 0*2 + 1*1
8+ 0 + 0 +1 = 9
so the (1001)2 = (9)10
b. Octal system:
example: convert (1010)8
1*8^3 + 0*8^2 + 1*8^1 + 0*8^0
1*24 + 0*16 +1*8 + 0*1
24+ 0 + 1 + 0 = 25
so the (1010)8 = (25)10
c. Hexa decimal system:
example: convert (1011)16
1*16^3 + 0*16^2 + 1*16^1 + 1*16^0
1*48 + 0*32 + 1*16 + 1*1
48 + 0 + 16 +1 = 65
3. Binary to octal and hexa decimal:
steps 1: write the binary representation of number
step 2: to convert into octal from the right side for every 3 bits write its equivalent octal number.
Step 3: to convert into hexadecimal from the right side for every 4 bits write its equivalent
hexadecimal number.
a. Octal system:
example : convert (1001)2
1001: 1
00 + 1001: 1
so (1001)2 = (11)8
b. Hexa decimal system:
example: convert (0010 1010)2
0010 1010: 10 = A
0010 1010: 2
so (0010 1010)2 = (2A)16
4. Octa and Hexa decimal to binary system:
a. Octal system:
example: convert (73)8
7 = 111
3 = 011
so (73)8 = (111011)2
b. Hexa decimal system:
example: convert (B9)16
B = 1011
9 = 1001
so (B9)16 = (1011 1001)2
5. Octal to hexa decimal conversion:
example:convert (10001010)8
10001010 : A
10001010: 8
so (10001010)8 = (8A)16
6. Hexadecimal to octal conversion:
example: convert (C2A)16
C : 1100
2 : 0010
A : 1010
1010: 010 : 2
0010 + 1: 101 : 5
1100 + 00: 000 : 0
110: 6
so (C2A)16 = (6052)8
 COMPLEMENTS

To simplify the addition, subtraction operation and for logical manipulation the digital computers
use the concept of complements.
There are two types of compliments : r’s complement and (r-1)’s complement.
i. (r-1)’s complement or diminished radix:
Given a number N with base r and n digits; the (r-1) complement of that number can be computed
as: (r^n -1)-N.
Example: 9’s complement of (14)10
r = 10; n = 2; N = 14
(10^2 - 1) - 14 = (85)10
ii. r’s complement or radix complement:
Given a number N with radix r and n digits; the r’s complement of that number can be computed as:
((r-1) - N) + 1
Example: 7’s complement of (65)7
r = 7 ; n = 2; N = 65
66 - 65 = 11 + 1 = 12 or 77-65 = 12
Subtraction methods using complements:
i. With end carry:
Example: 2340 - 1120
M = 2340
10’s complement of 1120: N = 8880
M + 10’s complement N = 2340 + 8880 = 12220
∴ The difference is 12220; where 1 is the carry so ignoring carry the M-N = 2340-1120 =
2220
Note: M > N ; the output will have a carry and has to be ignored.
ii. Without end carry:
Example: 1120 - 2340
M = 1120
10’s complement of 2340: N = 7660
M + 10’s complement N = 1120 + 7660 = 8780
∴ The difference is 8780; and no carry is obtained.
Note: M<N; the output will not have a carry.
 SIGNED BINARY NUMBERS

● Generally we have signed and unsigned numbers in our daily arithmetic. The positive numbers can
be prefixed with a plus sign and the negative numbers can be prefixed with a minus sign. But the
computer limitations permit us from using the plus and minus sign as a prefix to numbers to
indicate their sign so we use bits to represent the sign of a number.
● So in computer language we use 0 for positive numbers instead of plus signs and 1 for negative
numbers instead of minus signs.
● Both signed and unsigned numbers have a string of bits, the computer recognizes the left most bit
as a signed bit if it is a signed number or else the leftmost bit is considered as MSB if it is an
unsigned number.
● Example: 1100: 12(unsigned number) ; 11100: -12(signed number)
● In signed bit representation we have three methods of representing : sign magnitude, 1’s
complement, 2’s complement.
Example of bit signed number representation:
i. Signed magnitude: 12 : 01100; -12 : 11100
ii. 1’s complement: 12 : 01100; -12: 10011
iii. 2’complement: 12 : 01100; -12 : 10100
Arithmetic operation:
● If the signs of two numbers are the same then the numbers are added.
● If the signs of two numbers are different then the smallest magnitude number is subtracted from
the largest magnitude number.
● Example:
i. If two numbers have the same sign:
6 : 0000 0110
5: 0000 0101
6 + 5 = 11 = 0000 1011
ii. If two numbers have different sign:
6 : 0000 0110 -6 11111010
-5 : 0000 0101 5 : 0000 0101
6 - 5 = 1 = 0000 0001 5 - 6: -1 : 1111 0001
Note: In the arithmetic operation we may encounter a carry bit which is called overflow bit, this
overflow is acceptable when this operation is done on paper as we have infinite space but in
computers the memory is finite and bits have to accommodate within that space so the overflow is
ignored.
 CODES
A bit is considered to be a binary digit, and is represented as 0 and 1. So with a minimum of n bits
we can form 2^n distinct elements counting from 0 to (2^n - 1).
Codes and its types:
When some particular format of information has been written in another format but holds the same
information then it is called as coded data.
Decimal codes:
Binary codes for decimal digits require a minimum 4 bits.
Numbers in digital computers are represented in binary format or in decimal through binary code.
When specifying a data user generally gives in decimal format but the computer stores the
information in four binary storage elements.

Decimal digit BCD(8 4 2 1) excess -3 2421

0 0000 0011 0000

1 0001 0100 0001

2 0010 0101 0010

3 0011 0110 0011

4 0100 0111 0100

5 0101 1000 1011

6 0110 1001 1100

7 0111 1010 1101

8 1000 1011 1110

9 1001 1100 1111

From the above mentioned codes except BCD all others are self complementing codes ie. if a
number lets say decimal 4 in 2421 code it is 0100 and its 1’s complement can be obtained by
directly converting 1’s to 0’s and 0’s to 1’s.
Note:
The conversion of decimal to binary and conversion of decimal to binary code is different.
The bits obtained from conversion are binary digits and the obtained from code conversion
are the stream of bits following the rules of that particular code. Though both the output has a
combination of 0’s and 1’s.
Example: Binary conversion of decimal 25 is 11001 whereas the binary code of the same
decimal number 25 is 00100101.
Binary codes:
The digital data is represented, stored and transmitted as a group of binary bits. This group is also
called binary code. The binary code is represented by the number as well as the alphanumeric letter.
Advantages of Binary Code
● Binary codes are suitable for computer applications.
● Binary codes are suitable for digital communications.
● Binary codes make the analysis and designing of digital circuits if we use the binary
codes.
● Since only 0 & 1 are being used, implementation becomes easy.

Classification of binary codes

The codes are broadly categorized into the following four categories.
● Weighted Codes
● Non-Weighted Codes
● Binary Coded Decimal Code
● Alphanumeric Codes
● Error Detecting Codes
● Error Correcting Codes
1. Weighted Codes
Each position of the number represents a specific weight. Several systems of the codes are used to
express the decimal digits 0 through 9. In these codes each decimal digit is represented by a group
of four bits.
2. Non-Weighted Codes
In this type of binary code, the positional weights are not assigned. The examples of non-weighted
codes are Excess-3 code and Gray code.
a. Excess-3 code
The Excess-3 code is also called XS-3 code. It is a non-weighted code used to express decimal
numbers. The Excess-3 code words are derived from the 8421 BCD code words adding 3 to the
number.
Example: (0010)2 in excess -3 code written as (0101)2
b. Gray Code
The digital system can accept data in the form of digital signals. In our daily life we encounter only
the analog signals so before feeding any data to a digital system it has to be discretized and digital
systems follow the gray code convention when a digital signal is converted into analog data. One bit
changes when shifting from one number to another number; this makes the gray code more
advantageous over the binary code.
Eg: binary gray
00 00
01 01
10 11
11 10
The normal binary number when changing from one number to another number takes some time for
every bit to change and may get sensitive to noise so this problem is eliminated by gray code
scheme since only one bit changes at a time.
3. Binary Coded Decimal (BCD) code
The decimal digit in binary code using 8421 format is written. We can write 0000 to 1111 binary
digits using 8421 code but in BCD it accepts only numbers from 0000 to 1001 and the rest 1010 to
1111 are invalid. So to make the invalid binary digits into valid we need to add 0110 to each
number.
4. Alphanumeric codes
A binary digit or bit can represent only two symbols as it has only two states '0' or '1'. But this is not
enough for communication between two computers because there we need many more symbols for
communication. These symbols are required to represent 26 alphabets with capital and small letters,
numbers from 0 to 9, punctuation marks and other symbols.
The alphanumeric codes are the codes that represent numbers and alphabetic characters. An
alphanumeric code should at least represent 10 digits and 26 letters of alphabet i.e. total 36 items.
The following three alphanumeric codes are very commonly used for the data representation.
● American Standard Code for Information Interchange (ASCII).
● Extended Binary Coded Decimal Interchange Code (EBCDIC).
● Five bit Baudot Code.
ASCII code is a 7-bit code whereas EBCDIC is an 8-bit code. ASCII code is more commonly used
worldwide while EBCDIC is used primarily in large IBM computers.
5. Error Codes
● Information travels in a physical communication medium and due to some noise there may
be interruption of external unwanted signal into the bit stream that is being sent and may
change the values of bit stream where 1 has to be sent 0 might be received and vice-versa.
● So using error detection codes one can identify if there are any bit-reversal errors.
● There are binary code techniques available to detect and correct data during data
transmission.
travelling from one system to another. That means a 0 bit may change to 1 or a 1 bit may change to
0.
● A simple method to detect the error is using parity check (odd parity and even parity).
● Along with detection we can correct the data by adding a bit to the corrupted signal. Let's
say an even parity check is done and when there has to be even numbers of bits, if odd bits
are transmitted then we can add a bit to the data.
How to Detect and Correct Errors?
To detect and correct the errors, additional bits are added to the data bits at the time of
transmission.
● The additional bits are called parity bits. They allow detection or correction of the
errors.
● The data bits along with the parity bits form a code word.
Parity Checking of Error Detection
It is the simplest technique for detecting and correcting errors. The parity of 8-bits
transmitted word can be either even parity or odd parity.
i. Even parity -- Even parity means the number of 1's in the given word including the parity bit
should be even (2,4,6,....).
ii. Odd parity -- Odd parity means the number of 1's in the given word including the parity bit
should be odd (1,3,5,....).
Use of Parity Bit
The parity bit can be set to 0 and 1 depending on the type of the parity required.
● For even parity, this bit is set to 1 or 0 such that the no. of "1 bits" in the entire word
is even.
● For odd parity, this bit is set to 1 or 0 such that the no. of "1 bits" in the entire word is
odd.
 BINARY LOGIC

● It deals with accepting one or two discrete data with operations assuming the logical
meaning.
● The discrete values are considered to be true or false ie. 1 and 0 respectively.
● It consists of binary variables and logical operations.
● There are three logical operations AND, OR, NOT.
● AND: The operation is specified by a dot(.) operator. If any of the input is false then output
will be false.
● OR: The operation is specified by a plus(+) operator. If any of the input is true then the
output is true.
● NOT: The operation is specified by tilde (~). It inverts the input ie. if input is true then the
output will be false.
● NAND: The operation is specified by ~&. If any of the input is false then output will be
true.
● NOR: The operation is specified by ~|. If any of the input is true then output will be false.
● Exclusive - OR (xor): The operation is specified using cap(^). For an even number of input
bits; if two inputs are the same then output will be false and if two inputs are different then
output will be true. For an odd number of input bits; if inputs have even number of true then
output will be false else true.
● Exclusive - NOR (xnor): The operation is specified using ~). For an even number of input
bits; if two inputs are the same then output will be true and if two inputs are different then
output will be false. For an odd number of input bits; if inputs have even number of true
then output will be false else true.
Boolean laws:
The postulates from basic mathematical systems with some basic assumptions to
reduce rules, theorems and properties for a system.
1. Associative law: (x*y)*z = x*(y*z)
2. Commutative law: x*y = y*x
3. Inverse: Example: x = -x
4. Distributive law: x*(y.z) = (x*y).(x*z); example: a.(b+c) = (a+b).(a+c)

Postulates and theorems of boolean algebra:

1. Duality:
x+0=x x.0 = 0
x + x’ = 1 x.x’ = 0
x+1=1 x.1 = x
x+x=x x.x = x
2. Involution : (x’)’ = x
3. Demorgan’s: (x+y)’ = x’ + y’ ; (xy)’ = x’ + y’
Using these postulates and theorems the boolean equation can be reduced to a smaller
number of literals.
example: x’y’z + x’yz + xy’ = x’z(y’ + y) + xy’ = x’zy + xy’
The complement of a function can be obtained using Demorgan’s theorem. A complement of
function means x = x’ ; x’ = x. The variables hold either 0 or 1 as its value so the
complement of 0 is 1 and the complement of 1 is 0.
example: The complement of F = x’yz’ + x’y’z
F = (x’yz’ + x’y’z)’ = (x’yz’)’ . (x’y’z)’ = (x’’ + y’ + z’’) (x’’ + y’’ + z’)
The complement of F = x’yz’+x’y’z is F’ = (x+y’+z)(x+y+z’)
Minterm(m) and Maxterm(M):
Every binary variable can be expressed in its true or complement form. So for one variable
we can represent it in two ways. Similarly two variables can be represented in 4 ways (m(x
and y) = xy, x’y’, x’y, xy’). So n variables can be represented in 2^n ways. The AND
representation of variables is called minterms. The OR representation of variables is called
maxterms, (M(x or y) = x+y, x+y’, x’+y ,x’+y’).
A boolean expression that expresses all its variables as a sum of minterms or a product of
maxterms is called canonical form.
Don’t care term: X is termed as don’t care where the value is not known. It could either hold
0 or 1.
Example: Represent F = x’y + xyz + zy’ in sum of minterms.
F = x’y(z+z’) + xyz + zy’(x+x’)
F = x’yz + x’yz’ + xyz + xy’z + x’y’z = m3 + m2 + m7 + m6 + m1
F = ∑(m1, m2, m3, m6, m7) = F(x,y,z) = ∑(1,2,3,6,7)
Example: Represent F = (x+y)(y’+z) in the product of maxterms.
F = (x + y + zz’)(xx’ + y’ +z)
F = (x+y+z)(x+y+z’)(x+y’+z)(x’+y’+z)
F(x,y,z) = M0. M1.M2.M6
F(x,y,z) = Π(0,1,2,6)
 LOGIC GATES
● For a digital circuit to be built we require a few logic gates which perform logical
functions.
● Types of logic gates: And, Or, Nand, Nor, Not, Ex-Or, Ex-Nor.
● And: This performs a multiplication operation. F= x.y

FXY
000
001
010
111
● Or: This performs an addition operation. F = x+y

FXY
000
101
110
111
● Not: This performs invert operation. F=x’

FX
10
01

● Nand: This performs And operation and inverts the output. F = (x.y)’

FXY
 100
101
110
011
● Nor: This performs the Or operation and inverts the output. F = (x+y)’

FXY
100
001
010
011
● Ex-Or: This performs exclusive Or addition which means only if any of the input is
high then output will be high. For 3 input Ex-Or if the number of 1’s in input is odd
then output is high if not output is low.

FXY
000
101
110
011

● Ex- Nor: This performs exclusive Nor addition which means if both the inputs are
same then the output will be high. For 3 input Ex-Nor if the number of 1’s in input is
odd then output is high if not output is low.

FXY
100
001
010
111
 SIMPLIFICATION OF BOOLEAN FUNCTIONS
● We have seens postulates and theorems to reduce the number of literals in a boolean
equation. Similarly we have boolean function reduction techniques which use the
“K-map” and “Quine mccluskey” methods.
● Karnaugh Map:
This method is valid only till 5 minterms in a function.
If the number of minterms is more than 5 then the K-Map will no longer work and
Quine mccluskey method comes into picture.
A K-Map can have minterm(1) notation or maxterm(0) notation one at a time.
If minterm notation is used then the binary equivalent of the given decimal or
boolean equation is represented with 1. Each one can be grouped in individually,
pair, quad or octa.
● Example: Simplify the boolean function: F(w,x,y,z): ∑(2,5,6,12)

So from this K-Map we infer: F = w’xy’z+w’x’yz+wx’y’

● Example: Simplify the boolean function: F = A’C+A’B+AB’C+BC
Converting the function into canonical form.
F = A’B’C+A’BC’+A’BC’+A’BC+AB’C+ABC+A’BC
F = 001,010,010,011,101,111,011

F = C+A’B
● Prime implicants: It is a product term obtained by combining the maximum possible
number of adjacent squares in a map.
● Essential prime implicant: If a minterm in a square is covered by only one prime
implicant then it is called essential prime implicant.
 ● Logic gate representation of K-Map: After simplifying the boolean equation the logic
gate representation of the obtained equation is done.
Example: Simplify the boolean function: F = A’C+A’B+AB’C+BC and represent in
logic gates.
Converting the function into canonical form.
F = A’B’C+A’BC’+A’BC’+A’BC+AB’C+ABC+A’BC
F = 001,010,010,011,101,111,011

F = C+A’B

● Nand-Nand and Nor-Nor representation of obtained boolean equations from

K-Map: Digital circuits can be easily constructed using Nand and Nor gates and
thus they are known as universal gates.
a) Nand-Nand implementation of C+A’B

Steps:
1. Simplify the function and express it in terms of SOP form.
2. Draw a Nand to each AND term and replace a Not gate by a Nand gate.
3. Add a Nand gate at the inputs of Or gate and replace the Or gate by Nand gate.
 b) Nor-Nor implementation of C+A’B

Steps:
1. Simplify the function and express it in terms of POS form.
2. Draw a Nor to each Or term and replace the Not gate by Nor gate.
3. Add a Nor gate at the inputs of each And gate and replace the And
gate by Nor gate.
 COMBINATIONAL LOGIC
● A combinational circuit consists of logic gates whose outputs at any time are determined by
the combination of inputs at that instant and does not depend on the previous input to that
logic.
● For n inputs there are 2^n combinations of output so for each input combination there is
only one possible output combination.

Adders:
● The basic operation that a digital system performs is arithmetic operation.
● As the basic arithmetic addition has a carry when two numbers are added the same goes
with digital addition.
● Considering two bit binary addition: Half adder
0 + 0 = sum = 0 ; carry = 0
0 + 1 = sum =1 ; carry = 0
1 + 0 = sum = 1 ; carry = 0
1 + 1 = sum = 0 ; carry = 1
With the help of above obtained sum and carry output drawing its K-Map we arrive
at two boolean equations for sum and carry. Considering inputs A,B and outputs sum
and carry
sum = A’B+AB’
carry = AB
● Considering three bit binary addition: Full adder
0+0+0 = sum = 0 ; carry = 0
0+0+1 = sum = 1 ; carry = 0
0+1+0 = sum = 1 ; carry = 0
0+1+1 = sum = 0 ; carry = 1
1+0+0 = sum = 1 ; carry = 0
1+0+1 = sum = 0 ; carry = 1
1+1+0 = sum = 0 ; carry = 1
1+1+1 = sum = 1 ; carry = 0
With the help of above obtained sum and carry output drawing its K-Map we arrive
at two boolean equations for sum and carry. Considering inputs A,B,C and outputs
sum and carry
sum = (A’B + AB’)’C + (A’B+AB’)C’
carry = AB +BC +CA
Subtracters
● The basic operation that a digital system performs is arithmetic operation.
● As the basic arithmetic subtraction has a borrow when two numbers are subtracted
the same goes with digital subtraction.
● Considering two bit binary subtraction: Half subtractor
0 - 0 = difference = 0 ; borrow = 0
0 - 1 = difference =1 ; borrow = 1
1 - 0 = difference = 1 ; borrow = 0
1 - 1 = difference = 0 ; borrow = 0
With the help of the above obtained difference and borrow output drawing its K-Map
we arrive at two boolean equations for difference and borrow. Consider inputs A,B
and output difference and borrow.
difference = A’B+AB’
borrow = A’B
● Considering three bit binary subtraction: Full subtraction
0-0-0 = difference = 0 ; borrow = 0
0-0-1 = difference = 1 ; borrow = 1
0-1-0 = difference = 1 ; borrow = 1
0-1-1 = difference = 1 ; borrow = 0
1-0-0 = difference = 0 ; borrow = 1
1-0-1 = difference = 0 ; borrow = 0
1-1-0 = difference = 0 ; borrow = 0
1-1-1 = difference = 1 ; borrow = 1
With the help of the above obtained difference and borrow output drawing its K-Map
we arrive at two boolean equations for difference and borrow. Considering inputs
A,B,C and outputs difference and borrow
difference = (A’B + AB’)’C + (A’B+AB’)C’
borrow = A’B +BC +CA’
Binary adder and subtractor
a. Binary adder:
Full adder connected in series performs binary adder operation. For adding n bits we
need an n bit adder.
Consider the example of a 4 bit adder which requires 4 parallel adders each with 2
input and one carry input.

b. Binary subtractor
Full subtractor connected in series performs binary subtractor operation. For
subtracting n bits we need an n bit subtractor.
Consider the example of a 4 bit subtractor which requires 4 parallel subtractors each
with 2 input and one borrow input.

c. Binary adder-subtractor:
This is a special circuit which performs binary addition and subtraction based on the
control signal given as the input.
We give a control signal with input either 1 or 0. If the control signal is 1 then it
performs a subtraction operation which uses the principle of R’s complement and
adds 1 to the number while doing subtraction.
eg: 3-2 : 3+(-2) = 1 ; so we perform 2’s complement on 2 and add it with 3 to obtain
the difference between 3 and 2.
 When we provide a control signal if the input is 1 then it inverts the number that is
being subtracted and adds to another number.

Consider 11 and 01 as two inputs

case1 : K = 0
Y0 Ex-Or K = 0 ^1 = 1
X0+Y0 = 1+1 = sum = 0 carry = 1
Y1 Ex-Or K = 0^0 = 0
X1 + Y1 + carry = 1+0+1 = sum = 0 carry = 1
s1 s0 = 100
case2: K = 1
Y0 Ex-Or K = 1^1 = 0
X0+Y0+carry = 1+0+1 = sum = 0 carry = 1
Y1 Ex-Or K = 0^1 = 1
X1+Y1+carry = 1+1+1 = sum = 1 carry = 1
s1 s0 = 10 (ignoring the carry bit 1 as X>Y)
Carry look ahead adder
While performing the adder operation the circuit takes some delay to propagate the carry
from one level to the next level of addition. This delay can be reduced by improving the
speed of the addition.
In ripple carry adder, the carry bit of each bit position depends on the sum and carry bits of
previous bit position and the carry ripple through the circuit from LSB to MSB. This
increases the propagation of carry with increase in number of bits and limits the operating
frequency.
In carry look ahead adder the carry bits are pre computed using logic gates which generate
carry signals for each bit position based on input signal and carry signal of previous bit
positions.
Only disadvantage of carry look ahead adder is it requires so much logic to design.
Considering three bit binary addition: Full adder

From the above truth table we can conclude that when inputs are complemented and Cin is
1 the carry is propagated and when both inputs are 1 irrespective of Cin the carry is
generated.
 BCD adder
The decimal digit in binary code using 8421 format is written. We can write 0000 to 1111 binary
digits using 8421 code but in BCD it accepts only numbers from 0000 to 1001 and the rest 1010 to
1111 are invalid. So to make the invalid binary digits into valid we need to add 0110 to each
number. The below is the circuit to perform BCD addition.
When two numbers are added and output within the range of 0000-1001 (0-9) then it is said to be
in the BCD valid range; if not then 0110(6) has to be added to the obtained result.
Magnitude comparator
The magnitude comparator is a combinational circuit which compares two numbers if they
are greater (>), lesser(<) or equal(=).
For n bits we have 2^2n entries in the truth table.
If we take a two bit number as an example A1A0, B1B0.
For n bits we have 2^2n combinations ;
A=B : 2^n combination
A>B and A<B : (2^2n - 2^n )/2 combination
 A1 A0 B1 B0 A>B A<B A=B

0 0 0 0 0 0 1

0 0 0 1 0 1 0

0 0 1 0 0 1 0

0 0 1 1 0 1 0

0 1 0 0 1 0 0

0 1 0 1 0 0 1

0 1 1 0 0 1 0

0 1 1 1 0 1 0

1 0 0 0 1 0 0

1 0 0 1 1 0 0

1 0 1 0 0 0 1

1 0 1 1 0 1 0

1 1 0 0 1 0 0

1 1 0 1 1 0 0

1 1 1 0 1 0 0

1 1 1 1 0 0 1

A>B

A>B : A1B1’+A0B1’B0’+A1A0B0’
A<B

A<B : A1’B1+A0’B1B0+A1’A0’B0
A=B

A=B: (A0 EXOR B0) (A1 EXOR B1)

Example: Design a 2 bit comparator using 1 bit comparator

Multiplex and demultiplex
Multiplexer transmits large amounts of data over smaller channels. A digital
multiplexer is a circuit which has multiple input lines with one output line.
Based on the active select line the input is transmitted to output. For the 2^n
input line the circuit has n selection lines and one output line.
4 to 1 mux:

X Y Z

0 0 I0

0 1 I1

1 0 I2

1 1 I3

EXAMPLE FOR SOLVING MUX WITH SELECTION LINE B AND

C:

A B C X

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1
Realizing 4:1 Mux using 2:1 Mux

Demultiplexer receives a signal on one line and transmits that signal into
multiple output lines. A digital demultiplexer is a circuit which has multiple
output lines with one input line. Based on the active select line the input is
transmitted to output. The circuit has n selection lines with one input line and
2^n output lines.
 1 to 4 demux:

B C I3 I2 I1 I0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

Realising 1:4 Demux using 1:2 Demux

Implementing basic gates using mux:

1. NOT using MUX

2. AND using MUX

3. OR using MUX

4. NAND using MUX

5. NOR using MUX

6. XOR using MUX

7. XNOR using MUX

Decoder and encoder

Encoders are the combinational circuits that convert one form of code to another form. In
digital circuits the encoder converts 2^n inputs into n outputs. For a particular decimal input
its corresponding binary output will be high. If the enable pin is high then the input is
encoded and output is obtained.

Truth table of 2 to 1 encoder: at enable high

Y1 Y0 Z

0 1 0

1 0 1
 Z = Y0’Y1+Y1’Y0

Realizing 8:3 Encoder using 4:2 Encoder

 Decoders are the combinational circuits that convert back the encoded data into original code
format. In digital circuits the decoder converts n inputs into 2^n outputs. For a particular binary
input its corresponding decimal output will be high. If the enable pin is high then the input is
decoded and output is obtained.
Truth table of 2 to 4 decoder:

Y0 Y1 A B C D
A: A: Y0Y1
0 0 0 0 0 1
B:B: Y0Y1’
0 1 0 0 1 0
C:C: Y0’Y1
1 0 0 1 0 0

1 1 1 0 0 0 D:D: Y0’Y1’

A: Y0Y1

Y1’ Y1

Y0’ 0 0

Y0 0 1

B: Y0Y1’

Y1’ Y1

Y0’ 0 1

Y0 0 0

Y1’ Y1

Y0’ 0 0

Y0 1 0

Y1’ Y1

Y0’ 1 0

Y0 0 0
Realizing 3:8 Decoder using 2:4 Decoder

Priority encoder
 When there is more than one input high in the input logic then the normal
encoders produce invalid output. To overcome this we are going with a
priority encoder circuit which has an additional output pin called valid pin(v).
Based on the priority of the input its particular binary equivalent output will
be high.
4 to 2 priority encoder:

A B C D X Y V

0 0 0 0 X X 0

1 X X X 0 0 1

0 1 X X 0 1 1

0 0 1 X 1 0 1

0 0 0 1 1 1 1

X in input is don’t care term which can have either 0 or 1.

X:

X: A+B’C
Y:

Y: A+B
V: A+B+C+D
Parity
Parity checker detects the error in the data transmitted and with the help of a parity
generator the error is corrected. We have two types of parity generator ie. even and odd.
For an even parity checker if the number of 1’s in input is even then the signal does not
have any error and the generator generates 0 if not the generator generates 1 to make the
sequence as even.

For an odd parity checker if the number of 1’s in input is odd then the signal does not have
any error and the generator generates 0 if not the generator generates 1 to make the
sequence as odd.

X Y EVEN PARITY
GENERATOR

0 0 0

0 1 1

1 0 1

1 1 0

Y’ Y

X’ 0 1

X 1 0

Z = XY’+X’Y

X Y ODD PARITY
GENERATOR

0 0 1

0 1 0

1 0 0

1 1 1
 Y’ Y

X’ 1 0

X 0 1

Z = X’Y’+XY

Tri State Buffers

Tri state Buffer with Active HIGH Control

C X Carry

0 0 z

0 1 z

1 0 0

1 1 1

Tri state Buffer with Active LOW Control

C X Carry
 0 0 0

0 1 1

1 0 z

1 1 z

SEQUENTIAL LOGIC
● As we have read, the combinational circuit consists of logic gates whose outputs at any time
are determined by the combination of inputs at that instant and does not depend on the
previous input to that logic. The sequential circuit has an additional memory element with
logic gates . The output of sequential logic depends on the present and the past inputs.

Types of sequential circuits

● Synchronous circuits:
Synchronous sequential circuits use a clock signal to operate the circuit
synchronously. Based on the current state and inputs to the logic the next state is
determined.

● Asynchronous circuits:
Asynchronous circuits operate without a clock signal. They use feedback paths to
propagate the signals through the circuit.
 Synchronous circuits Asynchronous circuits

They use a common clock to They use a feedback path to propagate

synchronize operation. the data.

They rely on the regularity of clock They rely on the propagation delays of
signals. logic gates and feedback paths.

They are less complex so have less They are more complex than
chance of race around condition.. synchronous circuits and may have race
around conditions.

Easy to design. Complex to design.

Note: Synchronous circuits are used in most of the digital circuits like
microprocessing, DSP and memory systems. They are preferred over asynchronous circuits
because they are easier to design and analyse, and they are less susceptible to timing
problems like race around conditions.
Types of clock trigger
● Edge trigger:
The signal is obtained when the clock triggers when logic changes from low to high
or from high to low.
i. Positive edge trigger:
The output of the circuit changes when the clock triggers from high to low signal.
ii. Negative edge trigger:
The output of the circuit changes when the clock triggers from low to high signal.
● Level trigger:
The signal is obtained when the clock triggers when logic is high or low.
i. Positive level trigger:
The output of the circuit changes when the clock is at logic high.
ii. Negative level trigger:
The output of the circuit changes when the clock is at logic low.
Latches:
Latch is a single bit storage element which internally has logic gates.
There are 4 types of latches:
1. SR latch:
The SR latch has two inputs S(set), R(Reset). The output of latch depends on the
state of these inputs. When S is high and R is low then the latch is set and output is
high. When R is high and S is low then the latch is reset and output is low. When
both inputs are high or low the output is undefined.

En S R Q Q(t+1)

0 X X X 0

1 0 0 X Invalid

1 0 1 X 0(reset)

1 1 0 0 1(set)

1 1 1 X Memory
2. D latch:
This is a basic memory element in a digital circuit and has only one input. The
output is obtained when the enable is high and holds the data when the enable is low.

En D Q(t+1)

0 X Memory

1 1 1

1 0 0

3. JK latch:
The SR latch is modified into JK latch to overcome the problem of undefined state
when both inputs are high or low.

En J K Q Q(t+1)
 0 X X X Memory

1 0 0 X Memory

1 0 1 X 0 (reset)

1 1 0 X 1 (set)

1 1 1 0 1 (toggle)
1 0

4. T latch:
Toggle latch changes to the opposite state regardless of the present state .To
overcome the race around condition seen in JK latch is overcome by T latch.

En T Q Q(t+1)

0 X X Memory

1 0 X Memory

1 1 0 1 (Toggle)
1 0
Master slave:
The master slave flip flop is made using two JK latches one with positive
clock and other with negative clock.
The master slave circuit was developed to overcome the issues of timing
which produces glitches. When one circuit is working the other circuit is
made off so that the output is not affected by the next input reducing the
problem of glitches.

Flip flops:
Flip Flop is a one bit storage element but output changes with respect to input only when the
clock triggers. They have two inputs: clock input and data input.
The clock input determines the state of the output and the data input determines the new
state of the flip flop.
Flip flop is made by combining two latches, one with a positive clock (master) and other
with negative clock(negative).
There are 4 types of flip flops:
1. SR flip flop:

S R Q Q’

0 0 0 0(no change)

0 0 1 1(no change)

0 1 0 0(reset)

0 1 1 0(reset)

1 0 0 1(set)

1 0 1 1(set)

1 1 0 x(undefined)

1 1 1 x(undefined)

Characteristic equation: Q(t+1) = S+RQ(t)

2. D flip flop:
 Irrespective of the present state the output will have input as its output.

D Q Q’

0 0 0

0 1 0

1 0 1

1 1 1

Characteristic equation: Q(t+1) = D

3. JK flip flop:

J K Q Q’

0 0 0 0(no change)

0 0 1 1(no change)

0 1 0 0(reset)

0 1 1 0(reset)

1 0 0 1(set)

1 0 1 1(set)

1 1 0 1(toggles)
 1 1 1 0(toggles)
characteristic equation Q(t+1) = JQ’+K’Q
4. T flip flop:

T Q Q’

0 0 0(no change)

0 1 1(no change)

1 0 1(toggles)

1 1 0(toggles)

Characteristic equation Q(t+1) = T Ex-or Q(t)

Excitation table:

Q Q’ S R J K D T

0 0 0 X 0 X 0 0

0 1 1 0 1 X 1 1

1 0 0 1 X 1 0 1

1 1 X 0 X 0 1 0

Conversion of one flip flop to another flip flop:

Steps to convert:
1. write the truth table of required flip flop
2. From the obtained truth table write the excitation table of available flip flop.
3. Write the K-Map of the required flip flop.
4. Draw the Flip flop with available input.
Example:
1. Draw the JK flip flop with SR flip flop.
step 1: write the truth table of JK flip flop

J K Q Q’

0 0 0 0(no change)

0 0 1 1(no change)

0 1 0 0(reset)

0 1 1 0(reset)

1 0 0 1(set)

1 0 1 1(set)

1 1 0 1(toggles)

1 1 1 0(toggles)

step 2: Write the excitation table of SR flip flop

Q Q’ S R

0 0 0 X

1 1 X 0

0 0 0 X

1 0 0 1

0 1 1 0

1 1 X 0

0 1 1 0

1 0 0 1

Step 3: Write the K-Map

S:
 S = JQ’
R:

R = KQ
Step 4:

Race around condition and toggling:

Race around condition: The output of JK latch goes to an unpredictable state when both
the inputs are 1 1(the output toggles). This toggling of output is called race around condition
as the previous state of the circuit is unknown and the next state cannot be predicted. The
toggling of output in one pulse is uncontrollable and this hazard has to be overcome.
The race around condition can be overcome by reducing the enabling and increasing the
propagation delay but practically not possible.
So the practically possible way to overcome race around condition is by using edge
triggered latch(flip flop) or master slave circuit.

Toggling: Based on the present state my output will toggle till next clock pulse.
Timing diagram:
1. SR latch:

2. D latch:

3. JK latch:
 4. T latch:

Toggle mode of all flip flops:

1. SR flip flop: Connect S with Q’ and R with Q/
2. D flip flop: Connect Q’ to D.
3. JK flip flop: Connect J and K with 1.
4. T flip flop: Connect T with 1.
Latch using mux:
1. D-latch using Mux

2. T latch using Mux

3. JK latch using Mux

4. SR latch using Mux

NOTE:
Difference between combinational and sequential circuit:

COMBINATIONAL LOGIC SEQUENTIAL LOGIC

The output is dependent only on present The output is dependent on present input
input. and previous output.

It does not have a memory element. It has a memory element.

 It does not require a clock to trigger the It requires a clock to trigger the input.
input.

There will be no feedback from the output Involves some kind of feedback.
to input.

Easier to design & faster in operation. Involves lots of complexity in the design
and slower in operation.

REGISTERS AND COUNTERS

Registers:
● A register is a group of binary cells which hold binary information.
● Flip-flop is a 1 bit memory cell which can be used for storing the digital data.
● A register requires n flip flops to store n bits.
● We have Shift registers which can shift the data through the flip flops. The shift can be right
shift or left shift.

Types of shift registers

1. Serial in serial out:
 When data is passed through a shift register for every clock pulse the data shifts
either left or right direction under control. For n bits n flip flops are used and require
2^n-1 clock cycles.

Consider 4 bit 0101 to be stored in register :

clock A B C D

1 0 0 0 0

1 1 0 0 0

1 0 1 0 0

1 1 0 1 0

1 0 1 0 1

2. Serial in parallel out:

When data is passed through a shift register for every clock pulse the data shifts
either left or right direction under control. For n bits n flip flops are used and require
n clock cycles.

Consider 4 bit 0101 to be stored in register:

For 0101 to be passed till 4th flop it requires 4 clock pulses to load all the 4 bits.

3. Parallel in parallel out:

When data is passed through a shift register for every clock pulse the data shifts
either left or right direction under control. For n bits n flip flops are used and require
1 clock cycles.

Consider 4 bit 0101 to be stored in register:

For 0101 to be passed it requires 1 clock pulses to load all the 4 bits, as we get
 output at each flop.

4. Parallel in serial out:

When data is passed through a shift register for every clock pulse the data shifts
either left or right direction under control. For n bits n flip flops are used and require
N clock cycles.
We use a mux to select if the data to be passed or not. The registers either loads or
shifts.

If the select line is 0 then data is loaded and if the select line is 1 then the data shifts.

Consider 4 bit 0101 to be stored in register:

At x = 0101 is loaded. The input 0101 is given to each mux.

Counters:

It is a circuit which stores the number of times a particular event has occurred. The counters are
used for counting in digital circuits.
JK, D and T flip flops can only be used to design a counter, SR flop cannot be used as it goes to
undefined state.

For n bits n flip flops , 2^n states and n clock pulses are required.

Counters can be classified based on:

1. Clock: Synchronous and asynchronous
2. Clock trigger: Positive edge or negative edge
3. Count to: Binary or decade
4. Count direction: Up, down, up-down, random
5. Flip flops used: JK, T or D.

Types of counter:

1. Synchronous counter:

All flops are triggered by the same clock. It can operate at high frequency compared
to ripple counters.

Procedure to write the synchronous counter:

1. Write the present state and next state.
2. Write the excitation of the present state and next state of the given flip flop.
3. Write the K-Map with respect to the present state and design the counter.

Example 1: Design Mod - 4 counter using D flip flop:

Present Present Next state Next state D1 D0

State state

Q1 Q0 Q(T+1)1 Q(T+1)0

0 0 0 1 0 1

0 1 1 0 1 0

1 0 1 1 1 1

1 1 0 0 0 0

D1:

Q1’ Q1

Q0’ 0 1

Q0 1 0

D1: Q0Q1’+Q1Q0’

D0:

Q1’ Q1
 Q0’ 1 0

Q0 1 0

D0: Q1’

Example 2: Design mod 5 counter with T flip flop. (0-2-1-4-3-0)

Prese Prese Prese Next Next Next T2 T1 T0

nt nt nt state state state
state State state

Q2 Q1 Q0 Q(T+ Q(T+ Q(T+

1)2 1)1 1)0

0 0 0 0 1 0 0 1 0

0 0 1 1 0 0 1 0 1

0 1 0 0 0 1 0 1 1

0 1 1 0 0 0 0 1 1

1 0 0 0 1 1 1 1 1

T2:

Q1’Q2’ Q1’Q2 Q1Q2 Q1Q2’

Q0’ 0 1 0 0

Q0 1 0 0 0

T2: Q0Q1’Q2’+Q0’Q1’Q2 = Q1’(Q0Q2’+Q0’Q2)

T1:

Q1’Q2’ Q1’Q2 Q1Q2 Q1Q2’

Q0’ 1 0 1 1
 Q0 1 0 0 0

T1: Q0’Q1+Q1’Q2’

T0:

Q1’Q2’ Q1’Q2 Q1Q2 Q1Q2’

Q0’ 0 1 1 1

Q0 1 0 0 0

T0: Q0’Q1+Q0’Q2+Q0Q1’Q2’

2. Asynchronous counter(ripple counter):

The counter does not have a common clock. The output of a flop is given as a clock
to the next flop.

Rules to draw asynchronous counter:

1. The main block is given with input LSB .
2. All the flops should be in toggle mode.

Two types of ripple counter:

For up counting with a positive clock pulse connect Q’ to the next flip flop
clock, and for negative clock pulse connect Q to the next flip flop clock.

For the down counter with negative clock pulse connect Q’ to next flop
clock, and for positive clock pulse connect Q to next flop.

1. Up counter
Example Mod - 8 up counter:
Q2 Q1 Q0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Example Mod 5 up counter

Q2 Q1 Q0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0
 Note:
1. For the counters which do not count till the 2^n states for n bits we have an
additional input reset/clear. When reset or clear is given then the counter stops
counting when the required bit sequence is reached.
2. At (n+1)th pulse the set should be 1, and at nth pulse the clear should be 0. (Either
set or clear input is given).

2. Down counter

Example Mod 5 down counter

Q2 Q1 Q0

0 0 0

1 0 0

0 1 1

0 1 0

0 0 1

0 0 0

Note:
3. For the counters which do not count till the 2^n states for n bits we have an
additional input reset/clear. When reset or clear is given then the counter stops
counting when the required bit sequence is reached.
4. At (n+1)th pulse the set should be 1, and at nth pulse the clear should be 0. (Either
set or clear input is given).

3. Up-Down counter:

We provide a select signal for selecting the operation either up or down.

Example Mod-8 up down counter - 3 bit:

Special counters:

1. Ring counter/Bi-directional shift register:

It is a special type of serial in serial out shift register. The last flip flop output
is taken as input for the first flip flop with another input called preset for the
first flop.

For n bit Number of states(n) is equal to the number of flip flops(n) used.
Note: When preset is set to 0 then output is 1 and when the clear is set to 1
output is 1.
Consider Mod-4 counter: At 4th pulse the counter has reached its original
state so it is Mod-4 counter.

clk d3 d2 d1 d0

0 1 0 0 0

1 0 1 0 0

1 0 0 1 0

1 0 0 0 1

1 1 0 0 0
 2. Johnson counter/twist-pair ring counter:
It is a special type of serial in serial out shift register. The last flip flop output
is taken as input for the first flip flop.

For n bit , 2n Number of states and n flip flops used.

Consider the Mod-8 counter: The number of states is 8 because for the
initial state to come back it took 8 pulses so it is called as MOD-8 counter.

clk d3 d2 d1 d0

0 0 0 0 0

1 1 0 0 0

1 1 1 0 0

1 1 1 1 0

1 1 1 1 1

1 0 1 1 1

1 0 0 1 1

1 0 0 0 1

1 0 0 0 0

NOTE:

Asynchronous counter Synchronous counter

Output of each flop is used as a clock to the It has a common clock to all the registers.
next flop.

Delay of each flop is propagated to the next Delay is independent of previous flops.
 flop.

It is not suitable for high speed applications It is used in high speed applications.
due to timing criticality.

The number of states for n bits is 2^n states. The number of states for n bits is 2^n states.

FINITE STATE MACHINE

A FSM consists of a set of states, a set of inputs and outputs with a set of state transition functions.
The output signals of an FSM can be a function of either the current state or the combination of the
current state and input signals, depending on the type of FSM.
The most common use of an FSM in daily life would be vending machines or traffic light systems
etc.
The sequential state machines are called finite state machines(if they have finite states).

Types of FSM
1. Mealy FSM
If output depends on both present input and present state.

Steps to design Mealy FSM:

1. Define the requirement
2. Define state diagram
3. Assign binary codes to the states
4. Define state transition table
5. Implement state transition table using logic gates or flip flops

Example:
State diagram:

Assigning binary codes to states:

A=0
B=1

Define state transition table:

Current state Input Next state Output

 0 0 1 0

0 1 0 0

1 0 0 1

1 1 1 0

Implement state transition table using gates or flip flops:

Current Input Next Output T

state(Qt) state(Qt+1)

0 0 1 0 1

0 1 0 0 0

1 0 0 1 1

1 1 1 0 0

K-Map for T:

Q(t+1)’ Q(t+1)

Q(t)’ 0 1

Q(t) 1 0

T: Q(t)Q(t+1)’+Q(t)’Q(t+1) = Q(t) Ex-or Q(t+1)

2. Moore FSM

Outputs are only dependent on the current inputs.

 Steps to design Moore FSM:
1. Define the requirement
2. Define state diagram
3. Assign binary codes to the states
4. Define state transition table
5. Implement state transition table using logic gates or flip flops

Example:
State diagram:

Assigning BInary codes to states:

A=0
B=1

State transition table:

Current state Input Next state Output

0 0 0 0

0 1 1 0

1 0 0 1

1 1 1 1
 Implement state transition table using gates or flip flops:

Current Input Next Output D

state(Qt) state(Qt+1)

0 0 0 0 0

0 1 1 0 1

1 0 0 1 0

1 1 1 1 1

K-Map for D:

Q(t+1)’ Q(t+1)

Q(t)’ 0 1

Q(t) 0 1

D: Q(t+1)

Note:

Mealy Moore

Output depends on both current input and Output depends on only present input.
previous state.

Requires less number of states Requires one state more than mealy.

Can generate more complex circuits Cannot generate complex circuits

As output signals can be generated more It is slower compared to mealy

frequently it is faster.

Applications: Vending machine, traffic control Applications: Vending machine, traffic control
signals, war games signals, war games
 ROM - Read Only Memory & RAM - Random Access Memory

* ROM - Read Only Memory

● It is a combination of decoders and an OR gate.

● It is a permanent binary information storage element.
● They have internal fuses which can be programmed for specific configuration.
● It has n input lines and m output lines.
● Each bit combination of inputs is called an address(n variables) and the output combination
is called a word.
● The number of bits per word is equal to the number of output lines m.
● Number of addresses possible with n variables is 2^n.

● Let's take an example of 8x3 which means 8 words of 3 bits each can be stored in the
memory with 3 variables as input.
Types of ROMs:
1. Mask programming: This is a customized ROM where the vendor provides the
truth table to the manufacturer based on the customer requirement. The information
once stored cannot be erased.
2. Programmable ROM: This ROM used internal fuses to maintain connectivity for a
functionality to pass with some pattern which uses input data given by the vendor.
The information once written in this ROM cannot be erased. If it needs to be erased
then the unit has to be erased to change the bit pattern.

3. Erasable PROM: Once a bit pattern is fixed with the help of fuses it can be erased
with the help of Ultraviolet rays on the ROM and again programmed based on the
requirement.
4. Electrically Erasable PROM: Once a bit pattern is fixed with the help of fuses it
can be erased with the help of electrical signals on the ROM and again programmed
based on the requirement.
PLA - Programmable Logic Array:
They are Programmable AND and OR gate.

##image##
Size of PLA: n*l*m ; n = no of inputs, l = no of product terms, m = number of outputs
 We can reduce the size of PLA using K-MAP for the given function and use the function
which has less number of minterms.
##example##
PAL - Programmable Array Logic:
They are fixed OR and Programmable AND gates.
##image##
Size of PAL: n*m*I ; n = no of inputs, I = no of inputs to OR, m = no of outputs
##example##
PROM - Programmable ROM:
They are fixed AND and programmable OR gate.
##image##
Size of PROM: 2^n * m; n = no. of inputs , m = no of outputs
##example##

* RAM - Random Access Memory

● We know that for an information to be stored there must be a set of circuits that gets
the data, stores and transmits again when required.
● We have seen ROM which is a permanent storage similarly we have a RAM which is
a temporary storage ie. after storing data if not saved upon refreshing the data will be
erased.
● RAM is considered to have multiple memory units where each memory unit stores
binary data in form of words and bits.
● A word is a group of 1’s and 0’s. It is an entity of bits used to move data in and out.
A group of 8 bits is called byte.
● Most computers use 8 bit length words. In a 32 bit word length we have four 8 bits.
● The communication between memory and outer environment is achieved through
input lines, output lines, control lines and address selection lines.
● Consider an example of memory with capacity 1K words of 16 bits each. Since 1K =
1024 = 2^10 and 16 bits constitute two 8 bits. It means that the memory can
accommodate 2048 = 2K bytes.
● Based on the control line’s input the operation that the memory should perform is
decided.

Memory line read/(write)’ memory operation

0 X none

1 0 write to selected word

1 1 read from selected word

● There are two types of RAM ie. Static RAM and Dynamic RAM.
● Static RAM is a collection of flip flops and data can be erased as soon as the system is
turned off. They are easy to use and have shorter read and write cycles.

● Dynamic RAM uses a capacitor to store information and is stored in the form of an
electrical signal. The capacitors inside the RAM are obtained through MOSFET. As
capacitors charge and discharge the capacitors must be charged frequently by
refreshing dynamic memory. It has reduced power consumption and large storage on a
single chip.