International Journal of Power Electronics and Drive Systems (IJPEDS)

Vol. 13, No. 2, June 2022, pp. 783~791

ISSN: 2088-8694, DOI: 10.11591/ijpeds.v13.i2.pp783-791  783

Development of performance characterization in VSI-fed

induction motor drives using random PWM

Mohan Das Raman1, Chandirasekaran Easwaran2, Vinod Kumar Srinivasan1,

Bharatiraja Chockalingam3
1
Department of Electrical and Electronics Engineering, New Horizon College of Engineering, Bengaluru, India
2
Department of Electrical and Electronics Engineering, Coimbatore Institute of Technology, Coimbatore, India
3
Department of Electrical and Electronics Engineering, SRM Institute of Science and Technology, Chennai, India

Article Info ABSTRACT

Article history: Any industrial or power sector application requires a pulse width modulation
(PWM) inverter. Industrial drives, in particular, are highly concerned with
Received Sep 30, 2021 industrial standards. To satisfy the voltage source inverter (VSI) drives
Revised Mar 1, 2022 objects, a variety of PWM approaches are used, including inverter DC input
Accepted Mar 23, 2022 voltage utilizations, suppression of higher and lower order of harmonics, as
well as spreading harmonics acoustic noise reduction, among others PWMs.
One of the better approaches for minimizing noise on voltage source three-
Keywords: phase inverter fed drives is random pulse width modulation (RPWM).
Despite the fact that these described RPWM approaches are superior in
Analysis multicarrier RPWM terms of harmonic spreading and mitigation, these methods are unable to
Harmonics achieve the target DC-link utilizations. As a result, the focus of this paper is
Mitigation acoustic noise on combining multicarrier RPWM principles with space vector PWM
reduction (SVPWM) to produce multi-carrier random SVPWM (MCRSVPWM). The
Space vector PWM suggested PWM generates random unsystematic triangle carrier (5 kHz,
2.5 kHz, 1.25 kHz, 1 kHz) based pulses, whereas the traditional random
PWM techniques are uses a fixed frequency triangular carrier to generate
random pulse positions. Asynchronous induction motor driving simulation is
carried out using MATLAB/Simulink. The proposed MCRSVPWM is put to
the test with a 2-kW six-switch VSI-fed induction motor drive system.
This is an open access article under the CC BY-SA license.

Corresponding Author:
Raman Mohan Das
Department of Electrical and Electronics Engineering, New Horizon College of Engineering
Outer Ring Rd., Kaverappa Layout, Bengaluru, India
Email: [email protected]

1. INTRODUCTION
Voltage source inverter (VSI) based on pulse width modulation (PWM) are an unavoidable element
of industrial drive systems. Volatge harmonics rejection, DC-link volatge usage, common-mode voltage
(CMV) elimination, bearing current mitigations, and acoustic-noise eliminations, are all benefits of these
VSIs. To address the above needs, various types of PWM schemes have been developed in VSI [1]-[3].
Nonetheless, certain PWM techniques fail to reduce acoustic noise, which is a critical consideration for VSI-
based motors [4]-[6]. Another standard for any PWM is the utilisation of the DC-link to meet the drive needs.
As a result, the power electronics researcher created real-time pulse width modulation random carrier PWM.
Unlike sine PWM (SPWM), this PWM compares sinusoidal signals with random carriers to arrive at the final
result. pulse [5]. In various attempts to minimise AC drives, PWM and external noise reduction filters have
been suggested [7]-[12]. The RPWM is accomplished by altering the carrier wave's slope at random. Random
carrier frequency PWM (RCFPWM) [13], random switching PWM (RSPWM) [14], and random pulse-

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784  ISSN: 2088-8694

position PWM (RPPPWM) [15] are the three main kinds of RPWM. The researcher changes the angle of the
PWM carrier otherwise the volatge reference signal angle in RCFPWM to modify the carrier. RPWM can be
incorporated using space vector PWM (SVPWM). The random signal is employed in RSPWM as a substitute
of the carrier wave modification to provide the switching pulse width. Lai and Chen [16] used a digital
logical circuit with gates to build the RPPPWM. To reduce electromagnetic interference (EMI) in electric
motor systems, Jiang and Wang [17] presented a chaotic pulse generation approach. Here motor current
spectrum uses discrete components, it includes the circuit to choose their own needed carrier frequency [18],
[19]. New-fangled constent carrier frequency quasi-random PWM approach is presented to eliminate
harmoincs by improving the drive without stimulating mechanical resonance [12]. More diverse states are
necessary to generate a random bit number, which needs a higher number of successive digital states.
However, as the number of digital circuits increases, so does the cost and difficulty of putting them together.
As a result, the researcher advised that to boost randomization, a direct response shift register using Linux
from scratch (LFS) register is used [19]. The size of the linear-feedback shift register (LFSR) and the clock
frequency existent influence the quantity of repetition. The sinusoidal reference is related to the engaging
carrier triangle cycle to attain the pulses [20], [21]. To meet out these demand from the PWM, the paper
proposed a hybrid PWM combining conventional RPWM with ramdom carrier and SVPWM [22] few work
is persented in PWMs gerneration spreading harmonics reduction to improve the the system's harmonic
effects. Nevertheless, those methods ignore the acoustic noise effects and maximum possbile DC-link volatge
utilizations [23]-[26]. random space vector pulse width modulation for noise reduction in VSI-fed induction
motor cloud system model incoprated [27]. Random space vector PWM techniquies used for noise reduction
in induction motor [28]. Hence the acoustic noise effects and maximum possbile DC-link volatge unitizations
can be easly addressed.
The field programmable gate array (FPGA) used to buid the 8-bit and 16-bit pseudo-random bit
sequence (PRBS) to generate the discontinous random binary bits. The space vectior PWM refence signal is
associated with random carrier generator and PRBS binary selector block are organized by the same FPGA.
A three-phase VSI linked 2.5 kW 3-phase induction motor drive is simulated using the MATLAB/Simulink
software package (2016.b). Different rectangular phase shift with PWM (RPPWM), including the suggested
multi-carrier random SVPWM (MCRSVPWM), are studied in the inverter. The suggested approach uses
switching frequencies of 1.25 kHz, 1 kHz, 5 kHz and, 2.5 kHz for random carriers. Test the experimental
validity of the proposed MCRSVPWM is validated using lab scale setup of a 2-kW power capacity 3–phase
VSI fed induction motor drive.

2. START OF THE ART OF RPWM

The main difference among traditional and random PWM (RPWM) is pulse signal width is no
longer constrained to the operating frequency. The modulated signal and the switching frequency (carrier
frequency) regulate relay [7]. The structure of three phase induction motor is shown in Figure 1 (see
Appendix). The Figure 1 (a) shows the 3-phase induction motor drive VSI. The Figure 1 (b) shows the
conventional RPWM PRBS, and Figure 1 (c) shows the RPWM pattern generation. The randomization is
achieved here using the PRBS binary digital assignment method. In the common PWM generation processes,
the carrier wave generation is flows the fixed frequency carrier, whereas random PWM the carrier is handled
by a multiplexer and a shift register. The triangle carrier 'Cr' (in fixed frequency) is providing via multiplexer
(MUX) in the 'Cr' and 'Cr*-' sequences, as shown in Figure 1 (c). The 'Cr*' is the inverse phase of the 'Cr'
obtained using the 'NOT' gate. The constant frequency carriers 'Cr*' and opposed phase carriers 'Cr' are
specified by the designated signal (S) of the multiplexer, and the 'Cr' and 'Cr*' are chosen at random. The
MUX receives their chosen signal via a PRBS shift register. The exclusive OR (XOR) gate is values of
specific bits.

3. PROPOSED MCRSVPWM
RCPWM is essentially the same as regular SPWM, except with different carrier frequencies. To
generate randomization on the resultant carrier, two necessary triangular carriers with 180° phase-shift is
utilized. To begin, the proposed MCRSVPWM generated with the mixer of conventional random PWM and
space vector PWM. Pulse width modulation scheme is shown in Figure 2. Figure 2 (a) shown a depicts the
MCRSVPWM structure. The randomization carrier is generated using four carrier signals with various
frequencies of 1.25 kHz, 1 kHz, 5 kHz and, 2.5 kHz. Four multiplexers (MUX) are used to combine these
random carrier signals, and the MUX output is then supplied to a 411 multiplexer. The PRBS generators with
16-bit and 8-bit to produce random manner arrangements '0' and '1', that modify the random mix of four
carrier frequency signals. In the logic that one section significance in a series is not reliant on any extra

Int J Pow Elec & Dri Syst, Vol. 13, No. 2, June 2022: 783-791
Int J Pow Elec & Dri Syst ISSN: 2088-8694  785

sequence; hence the output is received in random manner. The multiplexers as well as random binary
sequence are used to choose each carrier signal. The output of the 1 st bit (bit 0) and 3rd bit D flip flop of the
shift register (three-bit) are used to create PRBS in the example below. The same clock signal triggers all
three D- flip-flops in the 3-bit shift register. The LFSR input is created by XORing the shift register's bit 0
and bit 2. The data shifting function is the only usage for the remaining D-flip-flop outputs. The pattern or
sequence of bits created is the consequence of the combined effect of XOR's output and the inputs chosen by
XOR.
With the support of a random frequency carrier signal and shift register the constant frequency clock
(fc) is created. A pseudo-random carrier approach is used to generate a random choice of triangle carrier-
waves with frequency (discrete in nature). Figure 2 shows the PWM scheme, Figure 2 (a) depicts the 8-bit
and 16-bit PRBS generation and Figure 2 (b) shows the space vector diagram. The output from the random
bits generator's PRBS bits can be found in (1) and (2).

OPRBS −8bit = B4 ⊕ B5 ⊕ B6 ⊕ B8 (1)

OPRBS −16bit = B11 ⊕ B13 ⊕ B14 ⊕ B16 (2)

Where Bxx is the n-bit shift register's xth output bit and XOR. At what time of outputs is 8-bit and 16-bit
PRBS generators are become zero, then the carrier with a frequency of 2kHz is chosen. The frequency carrier
wave 3kHz is picked, once the 16-bit PRBS output 8-bit PRBS generator output are zero and unity
respectively. The 3.5 kHz wave is picked, once the 16-bit PRBS generator output and the 8-bit PRBS
generators are turn out to be one and zero.

Triangle
Generator
2 kHz
3x1 Space Vector Diagram
Mux

VL2
3 kHz VL3
[110]
3x1
[010]
Mux
2 kHz
4x1 VL2
Sum VL4 [100]
3 kHz 3x1
Mux
[011]

Shift Register 16 bit PRBS VL5 VL6

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
[001] [101]
3x1
Mux
Gate Pulses S1 to S6

Shift Register 8 bit

PRBS
8 7 6 5 4 3 2 1

Multicarrier generation

(a)

β
VL2 [110]
VL3 [010]

S2
S1
S3 V*Ts

θ VL2 [100]
Vz Va Ta α
S4 [000] S5
[111]

S5
VL5 [001] VL6 [101]
(b)

Figure 2. Pulse width modulation scheme (a) proposed MCRSVPWM scheme and (b) space vector diagram

Development of performance characterization in VSI-fed induction … (Mohan Das Raman)

786  ISSN: 2088-8694

Figure 2 (a) depicts the planned MCBRCPWM scheme. The multi-frequency carrier random signal
is sent to the SVPWM reference signal generation block once after the random signal has been created. In the
Figure 2 (b) the planned SVPWM is notified in this case for adjusting random signals. Motor quantities (such
as voltages, currents, magnetic flux, and so on) can be sent into the SVPWM reference generator, which
calculates the phase angle and magnitude of the space vector diagram (SVD) [22]. Every SVD sector remains
an equilateral triangle with height; the height of a sector equals h (=3/2). There are two sorts of voltage
vectors: i) large vectors (LV) and ii) zero vectors (ZV). The active vectors V1 to V6 are (1-11), (-1-11),
(-111), (-11-1), (11-1), (1-1-1), whereas the zero vectors V0 and V7 are (000) and (111) respectively. For
example, Figure 2 (b) indicates that V* is located in sector-1, which is bordered by vector V1. TS is the
switching sampling period (=1/fS). From time t0, V* travels to t1 as well as the association with the time-
integral is specified as (3) and (4).
𝑡1
∫𝑡 V* =T𝑎 𝑉1 +T𝑏 𝑉1 (3)
0

𝑇𝑠 = 𝑇𝑎 + 𝑇𝑏 + 𝑇0 (4)

Thus, the time expended by the zero vectors V0 can be written as (5).

𝑇0 = 𝑇𝑠 − 𝑇𝑎 − 𝑇𝑏 (5)

Here, Ta and Tb is pulse width of the on-time pulse SVPWM.

4. SIMULATIONS
A three-phase VSI linked 2.5 kW 3-phase asynchronous induction motor drive is simulated using
the MATLAB/Simulink software package (2016.b). Different RPPWM, including the suggested
MCRSVPWM, are studied in the inverter. The suggested approach uses switching frequencies of 1.25 kHz,
1 kHz, 5 kHz and, 2.5 kHz for random carriers. Throughout the simulation, the VSI's DC-link voltage has
been maintained at 400 V, and the inverter has been operated in the modulation index range of 0.1 to 0.9 Ma.
The Figure 3 shows inverter line-voltage and corresponding voltage THD of MCRSVPWM for inverter
modulation indices Figure 3 (a) show the measured line voltage Ma=0.7. Figure 3 (c) show the measured
inverter line voltage at Ma=0.9. The inverter delivers the maximum allowable DC-link utilization during the
circumstance. The voltage and its related harmonics spectra with M a=0.7 are shown in Figure 3 (b), The
voltage and its related harmonics spectra with Ma=0.9 is shown in Figure 3 (d). The basic voltage was
archived linearly by altering modulation index, and the harmonics spectra (percentage voltage total harmonic
distortion (VTHD)) was validated as 47.790% and 52.890% respectively, which is smaller than all previous
reported RPWM. As a result, when the inverter operates at a lower modulation, the Ma (low speed) operating
zone decreases the VTHD and increases the current total harmonic distortion (ITHD). Table 2 displays all of
the associated results for each operating zone. It is clear from the data that the inverter not only reduces THD
but also maintains DC-link utilization. The voltage and current spectra HSF noise is calculated by using [8]
as (6) and (7).

1 𝑁
HSF=√ ∑𝑗>1(𝐻𝑗 − 𝐻0 )2 (6)
𝑁

1 𝑁
Ho= ∑𝑗>1(𝐻𝑗 ) (7)
𝑁

Here, Hj= harmonics amplitude and ho=harmonic orders average value.

The white noise is zero when harmonic spread factor (HSF) is near zero. However, bringing the
HSF to zero is only partially doable. On the other hand, dealing with HSF should be small for better
harmonic spread. As a result, the proposed PWM coin the lower HSF using a simple technique. Table 1
compares the simulated values of several PWM systems, including the proposed MCRSVPWM. The inverter
operation voltage and current, as well as voltage THD and HSF, are all highlighted in the table. When
compared to the other five situations, the proposed MCRSVPWM shows its superiority in terms of inverter
operating range. When Ma = 0.8, RPWM and SPWM produce roughly 42.12% HSF reduction, chaotic PWM
achieves 36.04% reduction, AMTCPWM achieves 14.03% reduction, and RCPWM achieves 21.05%
reduction.

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Int J Pow Elec & Dri Syst ISSN: 2088-8694  787

VAB

msec
Harmonics Frequency
(a) (b)
VAB

msec
(c) (d)

Figure 3. Inverter line-voltage and corresponding voltage THD of MCRSVPWM for inverter modulation
indices: (a) inverter line -voltage Ma=0.7, (b) harmonics spectra for Ma=0.7, (c) inverter line-voltage Ma=0.9
and (d) harmonics spectra for Ma=0.9

Table 1. Harmonics acoustic noise results MCRSVPWM with other methods

Ma SPWM RPWM CPWM RCRPWM MRCRPWM MCRSVPWM
0.2 8.310 8.110 6.090 6.267 4.128 4.032
0.3 7.562 7.420 6.020 6.127 4.01/ 3.894
0.5 6.893 6.560 5.000 5.195 3.912 3.656
0.7 5.695 5.120 4.210 4.565 3.430 3.290
0.8 5.571 5.070 3.955 4.251 3.235 3.005
0.9 5.161 4.980 3.255 3.561 3.022 2.862

The Figure 4 shows the Acoustic noise results of MCRSVPWM, Figure 4 (a) shows acoustic noise
results of MCRSVPWM with modulation index of 0.2, Figure 4 (b) shows for Ma=0.5, Figure 4 (c) shows
for Ma=0.7 and Figure 4 (d) shows Ma=0.9. While experiences the proposed RSVPWM with different motor
speed, at low range speed the RSVPWM shown better response and disappearing the discrete frequency-
component like RSWM. The other surrounded frequencies the discrete components are still present. When
the motor operated at high and medium speed range, the proposed PWM is completely eliminated the
discrete frequency-components. The suggested PWM eliminates all discrete components voltage as well as
current spectrum frequency, which is not certainly abolished by a simple filter. The HSF for all recorded
RPWM is compared to the proposed MCRSVPWM in Table 2. The MCRSVPWM has less HSF thought out
the inverter operation, as can be seen in the table. The reason behind this is that spreading the carrier
frequency reduces the dominating frequency component significantly, allowing the non-fundamental power
to be spread out over a much larger frequency range, which helps to reduce acoustic noise.

Table 2. Line voltage and harmonics simulation results MCRSVPWM with other methods
SPWM RPWM CPWM RC-RPWM MRCR-PWM MCRSVPWM
Ma
V1 %VTHD V1 %VTHD V1 %VTHD V1 %VTHD V1 %VTHD V1 %VTHD
0.2 55 54.82 43 49.82 56 51.84 56 54.42 58 47.49 59 46.87
0.3 81 53.21 62 47.21 83 52.54 83 53.01 89 45.67 90 44.51
0.5 139 46.06 112 51.06 142 50.35 142 45.52 146 49..25 149 47..98
0.7 194 54.41 156 54.41 189 56.21 197 54.41 204 52.06 207 51.04
0.9 248 59.45 215 56.454 253 56.18 257 58.43 263 53.54 267 52.89

Development of performance characterization in VSI-fed induction … (Mohan Das Raman)

788  ISSN: 2088-8694

(a) (b)

(c) (d)

Figure 4. Acoustic noise results of MCRSVPWM with different modulation indies: (a) 0.2, (b) 0.5,
(c) 0.7 and (d) 0.9

5. EXPERIMENTAL VALIDATION
A fed VSI fed induction motor is used to test the experimental validity of the suggested RPWM.
Figure 5 depicts the lab scale setup of a 2-kW power capacity 3–phase voltage source fed drive (induction
motor) as well as the design flow of the MCRSVPWM FPGA implementation. The experiment uses a
SCH2080KE MOSFET based VSI stack module. To achieve a maximum RMS AC voltage output of 400 V,
the VSI input DC-link capacitor 3400microF is used. The input DC link voltage bus is maintains 550 V. The
switching frequency of the inverter is retained at 5kHz. The suggested approach uses switching frequencies
of 1.25 kHz, 1 kHz, 5 kHz and, 2.5 kHz with random carriers. The random carriers are generated via PRPS
bit generator via FPGA (Spartan-6). Using the MATLAB Xilinx system generation implementation, the
random carrier and SVPWM are created, and the bit file is generated by FPGA-controller. The multi-carrier
5 kHz, 2.5 kHz, 1.25 kHz, 1 kHz signals are created and stored with an FPGA look-up-table [22]. The
various switching/carrier frequencies are combined using PRBS to generate binary in random manner and
then fed into the SVPWM block for the final pulse generation. For an inverter leg, the dead-time is set to
6 micro-seconds. The VSI drive is put through its paces with various frequency combinations in order to
change the mixer's carrier frequency sequence. The SVPWM allows the inverter operating modulation indies
from 0 to 0.9.

Oscilloscope Three phase reference

Vref, α calculation
MATLAB/Simulink Design

FPGA Board Multicarrier

MSO Random Sampling and & Holding
( spartan-6)
Generation
3 phase IPM Sector Angle Calculation

Timing calculation

Switching Pattern
gerneration
Implementation
FPGA Design

Design Implementation

Bit file Design Translation

Fluke Pins paling and route

Induction Motor

Download The Target FPGA

Figure 5. Experimental setup and implementation and design of MCRSVPWM implementation in FPGA

Int J Pow Elec & Dri Syst, Vol. 13, No. 2, June 2022: 783-791
Int J Pow Elec & Dri Syst ISSN: 2088-8694  789

To begin with, the VSI is evaluated with different frequencies as fc1=5 kHz, fc1=2.5 kHz,
fc1=1.25 kHz, fc1=1 kHz without floating combinations. The inverter voltage (VLL) of VAB and
corresponding percentage voltage THD of 0.9 Ma are shown in Figures 6 (a) and 6 (b). The inverter voltage
(VLL), VAB, increased to 263.5V, and the VTHD was found to be 51.70%. The analysis confirmed that
while the induction motor is working at intermediate speed range (at Ma=0.6), the line voltage VAB as well
as voltage THD are 123.5 V and 53.80% respectively, under modulation. As a result of these findings, it is
clear that the suggested MCRSVPWM maintains harmonics and inverter DC-link voltage at full inverter
range of operations. The experimentation results confirmed the MATLAB simulation results.

%VTHD = 51.7
Vab
300V/Div
Fundamental Voltage

Vbc
Lower Order harmonics
300V/Div

Vca
300V/Div

Harmonics order
msec
(a) (b)

Figure 6. Proposed MCRSVPWM results (experimental): (a) VLL for Ma = 0.9 and
(b) VLL voltage for Ma = 0.9

6. CONCLUSION
The multi random carrier space vector PWM for 3-phase voltage source inverter fed induction motor
drive is suggested in this paper to minimize the spreading harmonics acoustic noise. The proposed
MCRSVPWM is proposed by using random-binary bits. The recommended PWM is associated with
SVPWM, hence the with reduction of harmonics motor acoustic-noise in addition to the inverter DC–link
utilization. Including the proposed MCRSVPWM other RPWM and SVPWM is simulated and compared.
The Experimentations is built and validated through FPGA. The results are justifying the proposed RPWM
performances associations with SVPWM by reducing harmonics acoustic noise with better DC–link
utilization. This method can be recommended for the AC drives applications.

APPPENDIX

3 -Phase VSI

VDC/2
C1
S1 S3 S5 Induction Motor

A
B
C
VDC/2 S4 S5 S2
C2

DC-Link
(a)

Figure 1. Structure of three phase induction motor drive: (a) 3-phase induction motor drive VSI

Development of performance characterization in VSI-fed induction … (Mohan Das Raman)

790  ISSN: 2088-8694

Fixed Frequency Triangle Wave

Pseudo Random
Cr Frequency Carrier
2x1 R
Multiplier
Cr*
PRBS Random
bits
1
P 0

Shift Register
b1 b2 b3 b4 b5 b6 b7 b8
x(4)
x(5)
x(6) x(8)

(b) (c)

Figure 1. Structure of three phase induction motor drive: (b) conventional RPWM PRBS and (c) RPWM
pattern generation (continue)

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BIOGRAPHIES OF AUTHORS

Mohan Das Raman received B.E. Degree (2002) in Electrical and Electronics
Engineering from CSI College of Engineering, Ketti and ME Power Electronics (2007) from
Karunya University. He received Ph.D. in Anna University-Chennai (2020). He is currently
working as Associate Professor in the Department of Electrical and Electronics Engineering, New
Horizon College of Engineering, Bengaluru, Karnataka. His research interests are in PWM
Techniques, power electronics, renewable energy sources. He can be contacted at email:
[email protected]

Chandirasekaran Easwaran received B.E. Degree in Electrical and Electronics

Engineering from PSG College of Technology and ME (Applied Electronics) from Coimbatore
Institute of Technology. He obtained his Ph.D. in Electrical Engineering from Anna University-
Chennai. He is currently working as Professor in the Department of Electrical and Electronics
Engineering, Coimbatore Institute of Technology, Coimbatore, Tamil Nadu, India. His research
interests are in PWM Techniques, power electronics, renewable energy sources. He can be
contacted at email: [email protected].

Vinod Kumar Srinivasan received B.E Degree (2009) B.E-Electrical & Electronics
Engineering from Jayaram college of Engineering & Technology, Trichirapalli and M.E Power
system Engineering from Anna University, Coimbatore- 2015.He is working as Senior Assistant
Professor/EEE New Horizon College of Engineering Bengaluru, Karnataka. His Research areas
are in Power Systems, Industrial Automation. He can be contacted at email:
[email protected].

Bharatiraja Chockalingam is currently working as a Professor at Department of

Electrical and Electronics Engineering, SRM Institute of Science and Technology, Kattankulathur
Campus, Chennai, India. # Award recipient, Bhaskara Advanced Solar Energy (BASE)
Fellowship, Department of Science and Technology (DST), Govt. of India-Indo-U.S. Science and
Technology Forum – 2017 and, Young Scientists Fellowship Scheme (YSFS), Tamil Nadu State
Council for Science and Technology – 2018. His research interest includes power electronics
converter topologies, and controls for PV and EV applications. He can be contacted at email:
[email protected].

Development of performance characterization in VSI-fed induction … (Mohan Das Raman)