Received 11 November 2023, accepted 8 December 2023, date of publication 13 December 2023,

date of current version 20 December 2023.

Digital Object Identifier 10.1109/ACCESS.2023.3342328

Design of High Speed BCD Adder Using CMOS

Technology
ABDELSALAM AL SHARE1 , FADI NESSIR ZGHOUL 1 , OSAMA AL-KHALEEL 2 ,
MOHAMMAD AL-KHALEEL 3,4 , AND CHRIS PAPACHRISTOU5 , (Life Fellow, IEEE)
1 Electrical
Engineering Department, Jordan University of Science and Technology, Irbid 22110, Jordan
2 Computer Engineering Department, Jordan University of Science and Technology, Irbid 22110, Jordan
3 Mathematics Department, Khalifa University of Science and Technology, Abu Dhabi, United Arab Emirates
4 Mathematics Department, Yarmouk University, Irbid 21163, Jordan
5 ECSE Department, Case Western Reserve University, Cleveland, OH 44106, USA

Corresponding authors: Fadi Nessir Zghoul ([email protected]) and Mohammad Al-Khaleel ([email protected])

ABSTRACT Decimal arithmetic gains its importance in different applications in the fields of finance
and scientific applications. The approach of running decimal arithmetic over binary hardware requires
conversions from decimal to binary and from binary to decimal. These conversions produce inexact results
that impose financial losses for companies. Therefore, the need for decimal hardware is of high importance.
This work proposes decimal addition circuits and presents their realization in complementary metal-oxide
semiconductor (CMOS) technology. LTSPICE SPICE simulator software is used to simulate and verify the
functionality of the proposed circuits. The circuits are simulated using 45nm, 65nm, and 180nm technologies
and compared against existing works in the literature. Due to the lack of existing work in literature and for
purpose of comparison, this work also designed five different BCD adders using different existing binary
adders in literature. The experimental results show that proposed decimal adder achieves better performance
comparing to the other works. For example, for 3-digit operands, the proposed adder shows a power delay
product (PDP), in femtojoule (fJ), of 13.88 fJ comparing to 25.38 fJ , 16.01 fJ , 15.24 fJ , 27.49 fJ , and 27.77
fJ PDP for other works.

INDEX TERMS Addition circuits, BCD adders, CMOS, decimal arithmetic, decimal hardware, LTSPICE,
PDP.

I. INTRODUCTION Therefore, to create fewer rounding mistakes, it is preferable

Decimal numbers are widely utilized in the financial and the to directly do the calculation in decimal rather than in binary
scientific applications. For example, commercial databases [6], [7]. As a consequence, the need for embedding decimal
include a greater amount of decimal data than binary hardware components within processors becomes attractive
data. In order to achieve the precision required by these and justified [1], [6], and [8].
applications, which in some cases needs more than 32 digits, New innovations in technologies and new financial and
decimal arithmetic conventions are used to perform the business applications arise starting year 2000. Usually, the
calculations with enough word length [1]. Performing the numbers in the database of these applications are in decimal
calculations over binary units requires conversions between format.
decimal and binary, which introduces an unacceptable IBM is considered the first processor company to include
amount of latency [2], [3]. Additionally, these conversions dedicated decimal arithmetic units in their processors [1].
may result in producing inexact results especially when Examples where IBM uses decimal arithmetic unit are found
converting fractional quantities between decimal and binary in IBM eServer z900 [9], IBM POWER6, and IBM z10 [10].
systems [4], [5]. Hence, the precision is dramatically affected. Mathematical tools and solutions which have been con-
sistently playing a prominent role in a variety of science
The associate editor coordinating the review of this manuscript and and engineering fields to address technical issues (see,
approving it for publication was Marcelo Antonio Pavanello . e.g., [11], [12]) do not offer effective solutions for such
2023 The Authors. This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.
141628 For more information, see https://creativecommons.org/licenses/by-nc-nd/4.0/ VOLUME 11, 2023
A. Al Share et al.: Design of High Speed BCD Adder Using CMOS Technology

applications. In addition, software solutions are not favored the emergence of energy-efficient, compact, and portable
for such applications since they are generally slower than electronic systems [20]. Additionally, pioneering methodolo-
their hardware counterparts for large scale applications [13]. gies have paved the way for the creation of efficient and
As a result, experiments have been conducted in recent years symmetrical CMOS logic circuits, unlocking fresh opportu-
to improve decimal arithmetic in electronic devices. nities for design innovation [21]. In tandem, these endeavors
Different addition techniques have been devised since the have made significant contributions to comprehending and
adder is utilized in arithmetic tasks, whether in decimal or analyzing the performance of CMOS circuits [22]. In essence,
binary units. This study compares and implements the Binary CMOS circuits, fortified by inventive calibration techniques,
Coded Decimal (BCD) delay drop, as well as looks at the state-of-the-art power supply algorithms, inventive design
power reduction of five proposed decimal additions. approaches, and advanced analytical methods, persist as cen-
In computers, BCD is often used to encode decimal tral components in modern electronics, catalyzing innovation
values. BCD is a number representation system with a and empowering the development of progressively intricate
range from 0 to 9, where each decimal digit is represented electronic systems.
separately by 4-bit. For example, the decimal number 546 in The main contribution of this work is the design of two-
BCD is (0101 0100 0110)BCD [14], [15], [16]. stage, correction-free, fast, and low-power one-digit decimal
One significant advantage that BCD representation has addition CMOS circuit. This one-digit addition circuit is
over binary representation is the ease with which a decimal utilized in designing higher digits decimal addition circuits
number can be converted from its text representation to which is used in decimal arithmetic units that support
its BCD representation. Since many frequently used values decimal-based applications. In addition, for comparison
between 0 and 1 cannot be precisely represented by fixed and purposes, this work build five different decimal adders based
floating point binary representations, this capability is helpful on existing binary adders. The proposed decimal adder and
when working with fractional numbers. the other five decimal adders are used to build 2-digit, 3-digit,
A BCD adder adds two decimal digits with a carry-in and 4-digit decimal adders that are realized and simulated
input and generates the decimal sum and the carry-out output. using different CMOS technology libraries.
Typically, it consists of two 4-bit binary adders that are All of the one-digit decimal addition circuits are imple-
integrated with correction and carry generation circuits. The mented using CMOS technology, which has many advantages
two decimal operands and the carry-in are added using the over other technologies. For example, power dissipation is
first 4-bit binary adder. If the resulting sum is greater than 9 very low in digital CMOS circuits, since they dissipate power
(invalid decimal digit) then a correction is mandatory. The during switching time only. Moreover, in comparison to other
correction is done by the second binary adder, which adds types of transistors, CMOS devices can be scaled down more
6 to the result and passes any resulting carry to the output easily. Additionally, recent advances in CMOS technologies
[17], [18]. have improved the intrinsic speed of CMOS devices, which
In the field of contemporary electronics, the utilization made it faster than other type of devices. In general, CMOS
of CMOS (Complementary Metal-Oxide-Semiconductor) technology is preferred in digital circuit design over other
circuits has become remarkably prevalent due to their type of technologies due to its low fabrication cost. CMOS
exceptional qualities. These circuits have discovered diverse technology has been used in designing different type of BCD
applications across various domains, owing to their dis- adders in the literature [23], [24], [25].
tinctive advantages. A particularly noteworthy attribute is The rest of the paper is structured in the following manner.
the capacity of CMOS transistors to achieve minimal time Section II presents the background and the literature review.
delay, a feature of immense significance when aiming for Section III contains detailed information about the proposed
precision in electronic system design. Furthermore, they are BCD adder circuits. Section IV presents simulation results
acknowledged for their effectiveness in conserving power, and comparisons. Finally, the conclusions are provided in
a pivotal aspect in the creation of energy-efficient designs. Section V.
These attributes assume heightened significance during the
development of electronic systems, directly influencing both II. BACKGROUND AND RELATED WORK
speed and energy efficiency. The integration of CMOS BCD addition of n-digit operands is usually performed by
technology has ushered in substantial progress in the realm cascading n 1-digit BCD adders in a ripple carry structure as
of electronics, enabling the realization of high-performance, illustrated by Figure 1, where, Xi and Yi ; i = 0, 1, 2, · · · , n −
energy-efficient components such as microprocessors and 1 are the decimal digits of the two operands. In this case, if the
memory modules. It is worth noting that numerous studies delay for the 1-digit BCD adder is assumed to be T , then the
in the existing body of research have played a pivotal role delay for the n-digit BCD adder is linearly increasing with n
in advancing the precision of CMOS circuits [19], further and it can be estimated to be nT for large n.
solidifying their prominence in contemporary electronics. Performing a 1-digit BCD addition is achieved by adding
Moreover, dedicated efforts have been invested in the evolu- the BCD codes of the two decimal digits in binary and if
tion of power supply technologies, consequently facilitating the result is greater than 9 or if a carryout is generated,

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adders. Some of the proposed BCD adders in the literature

are used for two-operand operation while the others are
multi-operand BCD adders. Generally, one decimal digit
operands or multi decimal digits operands are addressed. For
example, the work in [26] present two techniques to design
high speed and economical decimal adders at the gate level.
FIGURE 1. A block diagram for n-digit BCD adder. Another example, where also gate level implementation is
used to design decimal addition/subtraction unit, is proposed
in [27].
It can be easily figured out that most of the imple-
mentations of the BCD adders presented in the literature
are high-level implementations where ASICs or FPGAs
environment is used. In fact, only few low-level imple-
mentations at the transistor level are found. As discussed,
one way to build a BCD adder is to use two-level binary
addition with a correction circuit. Therefore, it is worth
to address the low-level implementation of existing binary
adder and use them to design BCD adders for comparison
purposes. Therefore, in addition to the existing low-level
implementations of BCD adders, this work uses different
transistor level binary adder to design BCD adders that are
FIGURE 2. A conventional 1-digit BCD adder.
used for comparison purpose with the proposed CMOS BCD
adder.

a correction is done by adding (0110)2 to the result in order

to guarantee a result in the range of [0 − 9] [17], [18]. A. LOW-LEVEL BCD ADDERS
For example, to perform 5 + 3, we perform the binary With the advances in technology, the need for high perfor-
operation (0101)2 + (0011)2 . In this case the result, which mance circuits with low power dissipation and small size
is (1000)2 , is not greater than 9 and no correction is needed. is growing. In fact, customized circuits with compact size
On the other hand, to perform 6 + 7, the binary operation are essential in many applications. To reduce the time delay
(0110)2 + (0111)2 is performed. In this case the result, which in CMOS BCD adders, the CMOS threshold voltage is
is (1101)2 , is greater than 9 and a correction is required. reduced, which increases the leakage currents. Unfortunately,
Therefore, (0110)2 is added to (1101)2 to get (0011)2 which is the increase in the leakage current leads to high power
(3)10 = (0011)BCD . In fact, this is the correct result. The last dissipation. To solve this dilemma, a Dual threshold voltage
scenario is when a carryout is generated after adding the BCD (DVT) scheme is used in [28] and [29]. The threshold voltage
codes of the two decimal digits in binary. This can happen if for the transistors in the critical path is reduced to assure a
the input decimal digits are, for example, 8 and 9. Here, the balanced trade off between the power dissipation and the time
operation (1000)2 + (1001)2 is performed and the result is delay. Other techniques, such as power gating strategies and
(0001)2 . A carryout is generated in this case. It is clear that multiple channel length, are also used to lower the leakage
the result is wrong despite the fact the it is not greater than 9. current. The most effective power sleeping strategy is using
This is detected by the generated carryout and a correction is sleep MOSFETs. The sleep MOSFETs are two transistors.
needed. Hence, (0110)2 is added to (0001)2 to get the correct The first transistor is connected in series with the pull-up part
results (0111)2 which is (7)10 = (0111)BCD . Any generated of the logic gate circuit and the second transistor is connected
carry is considered a carryout from the 1-digit BCD addition in series with the pull-down part of the logic gate circuit.
operation and must be rippled to next stage, if any. Both of these MOSFET transistors either prevent a direct
Based on the previous discussion, a 1-digit BCD adder connection to ground or a direct connection to the power
is conventionally designed using two-stage binary addition. supply [28], [29]. In the multiple channel length techniques,
In the first stage, the initial binary addition of the BCD the transistors in the critical path are designed with small
codes of the two decimal digits is preformed. Whereas, the channel length in order to maximize their speed. On the other
second stage is required for correction whenever a correction hand, the other transistors are designed with larger channel
is detected by a dedicated logic. A 1-digit BCD is illustrated length to minimize the leakage current [29].
by Figure 2 where it is clear that the correction is done once More work is done to reduce the static power in BCD
the result from the first binary adder is greater than 9 or a adders. In [30], the power consumption is decreased by
carryout is generated from the first binary adder. designing a 32-bit adder with 14 transmission gate transistors
There are many works in the literature that address the instead of 28 transistors in the traditional 32-bit BCD adder.
BCD addition operations and the implementation of BCD On the other hand, the authors employ efficient power

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in (1)-(5).

C1 = G0 (P0 + C0 ), (1)
C2 = G1 (P1 + G0 ) + C0 (P1 + P0 ), (2)
C3 = G2 (P2 + G1 ) + (P2 + P1 ).(G0 (P0 + C0 )), (3)

Gout = G3 (P3 + G2 ) + (P3 + P2 ).(G1 (P1 + G0 )), (4)

FIGURE 3. AND logic and XOR logic used in modified 4-bit CLA.

Pout = (P3 + P2 )(P1 + P0 ), (5)

where, Pi = Ai + Bi and Gi = Ai Bi .
gating and multi-channel techniques to curtail the leakage Figure 6 shows the circuits for the carry signals of this
supremacy dissipated during standby mode in all deep CLA.
submicron CMOS devices.
5) A HIGH-SPEED 4-BIT CLA ARCHITECTURE
B. LOW-LEVEL BINARY ADDERS A new 4-bit CLA architecture is presented in [34]. In this
One approach that is used to speed up binary adders is the design, inputs (Ai , Bi , and C0 ) are directly supplied into the
carry look ahead addition (CLA). This type of adders reduces complex CLA circuits and the carry signals are generated.
the carry delay by reducing the number of gates through None of the Gi and Pi signals are used in this design. The
which the carry propagates [31]. Two signals, Propagate (P) circuits for the carry signals of this CLA are presented in
and Generate (G), are invented exclusively for the aim of Figure 7.
reducing the time required to generate the carry bits.
III. THE PROPOSED BCD ADDER
In the sequel, we present, discuss, and realize a CMOS based
1) CONVENTIONAL 4-BIT CLA ADDERS fast BCD digit adder which we use to build higher order BCD
The theory behind the conventional CLA is addressed by adders. The adder achieves high speed since being correction-
many works in literature such as [32], [33], [34], [35], [36], free. It is developed as a two-level netlist: netlist1 and netlist2
[37], [38], and [39]. In general, in a 4-bit conventional as illustrated by Figure 8. To do so, we first note that we let
CLA adder, the Propagate (P) and Generate (G) signals are the BCD adder have two decimal inputs A = A3 A2 A1 A0 and
computed and used in generating the sum and the carry B = B3 B2 B1 B0 , where A, B ∈ {0, 9} and Cin be the decimal
signals. The CMOS realization for these signal is found in carry input. Additionally, we let the output decimal sum be
many works in the literature. S ∈ {0, 9} and the output decimal carry be Cout . Then, the A
and B terms are expressed in the Boolean functions in (6) and
(7) in terms of two integers I = B3 B2 B1 and J = A3 A2 A1 as
2) MODIFIED 4-BIT CLA ARCHITECTURE
follows:
New implementations, as illustrated by Figure 3, for the XOR
and AND gates are presented in [40]. These XOR and AND A = (2 × J ) + A0 , (6)
gates are used to generate the Pi and Gi signals in the modified B = (2 × I ) + B0 . (7)
CLA presented in [41]. The only difference between this
modified CLA and the conventional CLA is the way the Pi Since A and B are two decimal digits, we have 0 ≤ J ≤ 4 and
and Gi signals are generated. 0 ≤ I ≤ 4.
As a result, the BCD adder output can be written as follows:
3) COMPACT 4-BIT CLA ARCHITECTURE {Cout , Sum} = A + B + Cin
The work in [42] presents the compact 4-bit CLA shown in = (2 × J + A0 ) + (2 × I + B0 ) + Cin
Figure 4. This CLA generates the Pi signal in a similar way it
is generated in the conventional CLA. However, the Gi signal = 2 × (J + I ) + (A0 + B0 + Cin )
is not required in this design and the carry-generation depends = 2 × K + (A0 + B0 + Cin ), (8)
only on the Pi signal.
where K = (J + I ) = (K3 K2 K1 K0 )BCD and 2 × K =
(K3 K2 K1 K0 0)BCD is generated using Netlist1 of Figure 8.
4) NOVEL 4-BIT CLA ARCHITECTURE K3 represents the decimal carry output and its value is either
A novel CLA is presented in [43] where the generation of 1 or 0. (K2 K1 K0 0)BCD is an even decimal digits which means
the Pi signal is completely changed and a NOR gate is used that the least significant bit (LSB) of 2 × K is always 0.
instead of the XOR gate in the conventional CLA. In addition, Therefore, only K3 , K2 , K1 , and K0 are forwarded to Netlist2
an inverted version of the Gi signal is utilized. The new logic of Figure 8 in order to add the term (A0 + B0 + Cin ) to 2 × K
based on this modification is given by the Boolean functions to get the final result.

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FIGURE 4. Compact 4-bit CLA circuits.

FIGURE 5. NAND logic and NOR logic used in Novel 4-bit CLA.

FIGURE 7. Carry signals in high-speed 4-bit CLA circuits.

FIGURE 6. Novel 4-bit CLA architecture.

For instance, if the two inputs A and B are (0101)BCD =

5 and (1000)BCD = 8, respectively, then one shall have
the values J = (010)2 = 2, I = (100)2 = 4, K =
K3 K1 K2 K0 = (J + I ) = (2 + 4) = (6)10 . This means FIGURE 8. The proposed BCD adder block diagram.
that 2 × K = (12)10 = (10010)BCD . The decimal carry
K3 is 1, and the even decimal digit (K2 K1 K0 0)BCD =
(2)10 = (0010)BCD . The values of K3 , K2 , K1 , and K0 have Cin to obtain optimized NAND-NAND implementation for
been computed for all possible combinations of A, B, and Netlist1. Hence, the Boolean logic that implements Netlist1

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is given by (9). where

Y0 : = Cin A¯0 B¯0 , Y1 := C¯in A0 B¯0 ,

K0 = X0 · X1 · X2 · X3 · X4 · X5 · X6 · X7 , (9a)
Y2 : = C¯in A¯0 B0 , Y3 := Cin A0 B0 ,
K1 = X0 · X8 · X9 · X10 · X11 · X12 · X13 · X7 , (9b)
Y4 : = K2 K0 Cin B0 , Y5 := K¯2 K¯0 Cin A0 ,
¯ ¯
K2 = X14 · X15 · X16 · X17 · X18 , (9c) Y6 : = K¯2 K¯0 A0 B0 , Y7 := K0 A¯0 B¯0 ,
K3 = X19 · X20 · X21 · (X22 · X23 ) · X24 · X7 , (9d) Y8 : = K0 C¯in B¯0 , Y9 := K0 C¯in A¯0 ,
Y10 = K¯1 K0 Cin B0 , Y11 := K¯1 K0 Cin A0 ,
where
Y12 : = K¯1 K0 A0 B0 , Y13 := K1 C¯in B¯0 ,
Y14 : = K1 C¯in A¯0 , Y15 := K1 A¯0 B¯0 ,
X0 : = A¯3 A¯2 A¯1 B2 B1 , X1 := A1 B¯3 B¯2 B¯1 ,
Y16 : = K1 K¯0 , Y17 := K1 K0 Cin B0 ,
X2 : = A¯3 A¯1 B¯2 B1 , X3 := A¯2 A1 B2 B¯1 ,
Y18 : = K1 K0 Cin A0 , Y19 := K1 K0 A0 B0 ,
X4 : = A2 A1 B2 B1 , X5 := A2 A¯1 B3 ,
Y20 : = K2 C¯in B¯0 , Y21 := K2 C¯in A¯0 ,
X6 : = A3 B2 B¯1 , X7 := A3 B3 ,
Y22 : = K2 A¯0 B¯0 , Y23 := K2 Cin B0 ,
X8 : = A2 B¯3 B¯2 B¯1 , X9 := A¯3 A¯2 B2 B¯1 ,
Y24 : = K2 Cin A0 , Y25 := K2 A0 B0 ,
X10 = A2 A¯1 B¯2 B1 , X11 := A¯2 A1 B¯2 B1 ,
Y26 : = K3 .
X12 : = A2 A1 B3 , X13 := A3 B2 B1 ,
X14 : = A¯3 A¯2 A¯1 B3 , X15 := A3 B¯3 B¯2 B¯1 , The proposed BCD adder can be expanded to handle as
X16 : = A2 A¯1 B2 B¯1 , X17 := A2 A1 B¯2 B1 , many decimal digits as needed, as discussed in Section II,
and then used in decimal arithmetic units in fully or partially
X18 : = A¯2 A1 B2 B1 , X19 := A2 A1 B2 ,
decimal processors. One of the processors that are furnished
X20 : = A2 A¯1 B3 , X21 := A2 B2 B1 , with decimal arithmetic unit is the IBM z196 10-Core chip
X22 : = A3 B2 B¯1 , X23 := A1 B3 , [44], which is an evolution of the z10 core design.
X24 : = A3 B1 .
IV. RESULTS AND COMPARISONS
For this research, LTSPICE program aided design tools are
The CMOS realization of Netlist1 is presented in Figure 9.
used as the standard circuit design and simulator tool. The
The inputs to Netlist2 are K , A0 , B0 and Cin , which are
circuits of the proposed decimal adder are implemented using
added to produce the final result which consists of the final
dynamic logic gates using 45nm BSIM4 model for 1-digit,
decimal carry output Cout and the final decimal digit result
2-digit, 3-digit, and 4-digit decimal operands. The transient
S = (S3 S2 S1 S0 )BCD . K must be aligned properly in this
analysis is performed at a frequency of 100MHz. The inverter
addition process such that 2 × K is evntually added.
has a width of 270nm for the p-MOS and 135nm for the n-
For instance, if the values of K3 , K2 , K1 and K0 are 1, 0,
MOS. For all simulations, the supply voltage is set to 1V .
0 and 1, respectively, then this means that the value of 2 × K
In order to determine the critical path delay in each design,
to be added to the value of (A0 + B0 + Cin ) is (12)10 =
the delay of all paths from inputs to the most significant bit
(1 0010)BCD . If we assume the values of A0 , B0 , and Cin are 1,
(MSB) of the sum output and the delay of all paths from input
1 and 0, respectively, then this means that the value of A+B =
to the final decimal carry out are investigated.
2 × K + (A0 + B0 + Cin ) is (14)10 = (1 0100)BCD . Cout , S3 ,
Beside the existing low-level decimal adder works pre-
S2 , S1 , and S0 are computed to be 1, 0, 1, 0 and 0, respectively.
sented in literature, which are found to be few as mentioned
On this basis, Cout , S3 , S2 , S1 , and S0 are computed for
in Section II, this work builds five different decimal adders
all possible combinations of K , A0 , B0 and Cin in order
for comparison purposes with the proposed decimal adders.
to obtain an optimized NAND-NAND implementation for
These five adders are designed following the 1-digit BCD
Netlist2. This NAND-NAND implementation of Netlist2 is
adder architecture presented in Figure 2, where low-level
presented by (10) and is realized using CMOS technology by
binary adder implementations from [34], [41], [42], and [43]
the circuits presented in Figure 10.
are used in addition to the conventional low-level binary adder
which is presented in different works in literature. For clarity
S0 = Y0 · Y1 · Y2 · Y3 , (10a) and simplicity, this work refers to these five BCD adders
S1 = Y4 · Y5 · Y6 · Y7 · Y8 · Y9 , (10b) using the symbols presented in Table 1.
Similarly, 1-digit, 2-digit, 3-digit, and 4-digit decimal
S2 = Y10 · Y11 · Y12 · Y13 · Y14 · Y15 · Y16 , (10c) adder versions are built out of these five adders and the
S3 = Y17 · Y18 · Y19 · Y20 · Y21 · Y22 , (10d) critical path delay is determined using the same way used to
determined the critical path delay for the proposed decimal
Cout = Y23 · Y24 · Y25 · Y26 , (10e) adder.

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FIGURE 9. Netlist1 of the proposed BCD adder design.

The delay of all paths from inputs to the most significant bit
(MSB) of the sum output and the delay of all paths from input FIGURE 10. Netlist2 of the proposed BCD adder.

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TABLE 1. Symbols used to refer to the five BCD adders that are built by
this work for comparison purposes with the proposed BCD adder.

to the final decimal carry out are reported in Tables 2, 3, 4,

and 5 for 4-digit, 3-digit, 2-digit, and 1-digit decimal adders,
respectively. For example, for 3-digit decimal adder, the delay
of all paths for each input to S11 and the delay of all paths
from each input to the final carry out Cout are investigated
FIGURE 11. Propagation delay from inputs to Cout of different BCD
and reported in Table 3 for the proposed adder and for the adders for different digit-length.
other five adders. In this case, the maximum delay from the
inputs to S11 is found to be 620.20 ps, 584.52 ps, 588.63 ps,
628.94 ps, 785.62 ps, and 371.75 ps for the 3-digit ADDa , 3-
digit ADDb , 3-digit ADDc , 3-digit ADDd , 3-digit ADDe , and
the proposed 3-digit BCD adder, respectively.
It can be seen from Tables 2, 3, 4, and 5 that the proposed
decimal adder achieves higher speed than all of the other
decimal adders especially with larger operands. For instance,
for 1-digit operands, the proposed decimal adder has minor
improvement in speed over the other five decimal adders.
However, much improvement is shown when it comes to 2-
digit operands and a speed up of almost 1.62, 1.50, 1.52,
1.61, and 1.97 is achieved by the proposed decimal adder
over ADDa , ADDb , ADDc , ADDd , and ADDe , respectively.
Moreover, from Table 2, one can find that for 4-digit operands
the proposed decimal adder is 1.50, 1.62, 1.62, 1.74, and FIGURE 12. Average power consumption of different BCD adders for
2.19 times faster than ADDa , ADDb , ADDc , ADDd , and different digit-length.
ADDe , respectively.
Furthermore, the proposed decimal adder is compared
against ADDa , ADDb , ADDc , ADDd , and ADDe in terms of
Average Power Consumption (APC), Power Delay Product
(PDP), and transistors count (TC). These comparisons are
listed in Tables 6, 7, 8, and 9 for 1-digit, 2-digit, 3-digit,
and 4-digit decimal adders, respectively. To highlight the
significance of these results, they are illustrated in Figures
11, 12, and 13.
It is clear that the proposed adder outperforms all other
adders in terms of power-delay product specifically for
operands size of 2-digit and above. The penalty is more
transistor count for all cases and more power dissipation in
some cases. For example, for 3-digit operands, the proposed
adder shows a PDP of 13.88 comparing to 25.38, 16.01, FIGURE 13. PDP of different BCD adders for different digit-length.
15.24, 27.49, and 27.77 PDP for ADDa , ADDb , ADDc ,
ADDd , and ADDe , respectively. In this case, the proposed
adder consumes 8.7% and 14.5% less power than ADDa and Additionally, the proposed adder is compared against some
ADDd respectively. On the other hand, it consumes 26.6%, existing decimal adders from the literature. These works are
30.6%, and 5.3% more power than ADDb , ADDc , and ADDe , implemented using 45nm, 65nm, and 180nm technologies.
respectively. In fact, it achieves 40.0%, 36.4%, 36.8% 40.8%, Therefore, for fair comparison with these works, the proposed
and 52.6% reduction in delay with an extra 22.1%, 47.6%, decimal adder has been implemented and simulated targeting
43.4%, 4.6%, and 15.3% transistors count comparing to the 65nm, and 180nm technologies. The results are reported
ADDa , ADDb , ADDc , ADDd , and ADDe , respectively. in Table 10.

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TABLE 2. Delay for all possible critical paths in the proposed 4-digit BCD adder.

TABLE 3. Delay for all possible critical paths in the proposed 3-digit BCD adder.

TABLE 4. Delay for all possible critical paths in the proposed 2-digit BCD adder.

From Table 10, the proposed 4-digit decimal adder 180nm technology, the proposed decimal adder is compared
achieves 23.1 PDP comparing to 50.3 and 1815.6 PDP for the with the work presented in [30] for 1-digit, 2-digit, and 4-digit
4-digit (CMOS) and (DTMOS) decimal adders of [45]. The operand size. The proposed 4-digit decimal adder achieves
works in [30] and [46] do not report any information about the almost 68% power saving comparing to the 4-digit decimal
delay and the PDP of their design. Therefore, the proposed adder in [30] that is based on power gating technique.
decimal adder is compared with these works in terms of The total transistor area (TTA) for each circuit is calculated
power only. The proposed 1-digit decimal adder achieves using (11) where Nn and Np are the n-MOST and p-MOST
much power saving comparing to both decimal adder designs transistors count, respectively. Therfore, the total number of
presented in [46]. For example, there is 99% saving in power transistors N = Nn + Np . Ln and Lp are the transistor length
comparing to the (RPS) decimal adder presented in [46]. For for the n-MOST and p-MOST transistors, respectively. Wn

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A. Al Share et al.: Design of High Speed BCD Adder Using CMOS Technology

TABLE 5. Delay for all possible critical paths in the proposed 1-digit BCD adder.

TABLE 6. Comparisons results for 1-digit BCD adder. TABLE 9. Comparisons results for 4-digit BCD adder.

TABLE 7. Comparisons results for 2-digit BCD adder.

TABLE 10. Comparisons of the proposed decimal adder with works from
the literature.

TABLE 8. Comparisons results for 3-digit BCD adder.

and Wp are the transistor width for the n-MOST and p-MOST
transistors, respectively. This work sets Wn = 3Ln , Wp = 6Lp is used. Therefore, as an examples, the total transistor area
and Ln = Lp = L. In CMOS technology, Nn = Np = N /2. for the proposed 3-digit BCD adder is calculated to be
12.848625 µm2 , 26.807625 µm2 , and 205.578 µm2 for
TTA = Np × Lp × Wp + Nn × Ln × Wn . the 45nm process, the 65nm process, and 180nm process;
= Np × Lp × 6Lp + Nn × Ln × 3Ln . respectively.
= N /2 × (6Lp2 + 3Ln2 ).
V. CONCLUSION
= 9NL 2 /2. (11)
A high performance 1-digit BCD adder is proposed. The
In this work, L is set to be 45nm, 65nm, 180nm for the 45nm adder is designed using two level netlist such that correction
process, the 65nm process, and 180nm process; respectively. is interleaved within the design. The Boolean equations for
The transistor count N is the same no matter what process each netlist are derived and realized in CMOS technology

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targeting 45nm technology. The 1-digit BCD adder is used [18] S. A. Kumar and M. Kavitha, ‘‘Design of efficient BCD adders correction
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[40] M. Hasan, M. J. Hossein, M. Hossain, H. U. Zaman, and S. Islam, ‘‘Design OSAMA AL-KHALEEL received the B.Sc. degree
of a scalable low-power 1-bit hybrid full adder for fast computation,’’ in electrical engineering from the Jordan Univer-
IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 67, no. 8, pp. 1464–1468, sity of Science and Technology, Irbid, Jordan,
Aug. 2020. in 1999, and the M.Sc. and Ph.D. degrees in
[41] M. Hasan, M. S. Islam, and M. R. Ahmed, ‘‘Performance improvement of computer engineering from Case Western Reserve
4-bit static CMOS carry look-ahead adder using modified circuits for carry University, Cleveland, OH, USA, in 2003 and
propagate and generate terms,’’ Sci. J. Circuits, Syst. Signal Process., vol. 8, 2006, respectively. He is currently an Asso-
no. 2, p. 76, 2019.
ciate Professor of computer engineering with
[42] G. A. Ruiz and M. Granda, ‘‘An area-efficient static CMOS carry-select
the Department of Computer Engineering, Jordan
adder based on a compact carry look-ahead unit,’’ Microelectron. J.,
University of Science and Technology. His current
vol. 35, no. 12, pp. 939–944, Dec. 2004.
[43] J. Miao and S. Li, ‘‘A novel implementation of 4-bit carry look-ahead research interests include embedded systems design, reconfigurable comput-
adder,’’ in Proc. Int. Conf. Electron Devices Solid-State Circuits (EDSSC), ing, computer arithmetic, and logic design.
Oct. 2017, pp. 1–2.
[44] IBM z196 (IBM 2817) Technical Specs | Top Gun Technology.
Accessed: Nov. 9, 2023. [Online]. Available: https://www.topgun-
tech.com/products/ibm-zsystems/ibm-z196-ibm-2817
[45] P. Chaudhari, A. Khadke, M. More, and P. D. S. Patil, ‘‘Ultra low power,
low voltage 16 bit BCD adder using DTMOS,’’ Int. Res. J. Eng. Technol.,
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[46] C. M. Kumar, M. Srinivasulu, S. A. Basha, K. Suvarna, and H. Devanna,
‘‘Design of low power 4-bit BCD adder using reversible gates,’’ Int. J. Ind.
Electron. Elect. Eng., vol. 2, pp. 14–16, Sep. 2014. MOHAMMAD AL-KHALEEL received the M.Sc.
and Ph.D. degrees in applied mathematics (numer-
ical analysis and scientific computing) from
McGill University, Montreal, QC, Canada, in
2003 and 2007, respectively. In 2007, he became
an Assistant Professor of mathematics with the
ABDELSALAM AL SHARE received the B.Sc.
Department of Mathematics, Yarmouk University,
degree from Yarmouk University, Jordan, in 2018,
Jordan, and afterwards was promoted to an
and the M.Sc. degree in electrical engineering
Associate Professor. He is currently an Associate
from the Jordan University of Science and Tech-
Professor with the Department of Mathematics,
nology, Jordan, in 2023. He did practical training
Khalifa University of Science and Technology, United Arab Emirates.
for three months with Irbid Electricity Company,
His research interests include multidisciplinary nature but the bulk of it
from June 2017 to September 2017. He was
has revolved around developing and implementing efficient and parallel
an Electrical Engineer with Jordan Petroleum
numerical methods as well as analytical methods for solving differential
Refinery, from September 2018 to February 2019.
equations (ordinary, partial, and fractional) that appear in many applications
He is currently with the Ministry of Education,
in different fields, including seismic waves, nanofluid and microfluid dynam-
Jordan. His current research interests include electrical circuits design,
ics, circuit simulations, other areas of mathematics, including topics in metric
electrical distribution systems, and electronic circuit design.
fixed point theory, fractional calculus, numerical parameter optimization,
inverse and control problems, and the mathematical background of computer
arithmetic circuits.

FADI NESSIR ZGHOUL received the M.Sc.

and Ph.D. degrees in electrical engineering from
the University of Idaho, Moscow, ID, USA, in
2003 and 2007, respectively. In 2007, he joined
The Hashemite University, Jordan, as an Assistant
Professor. After that, he joined Yarmouk Uni-
versity, Irbid, Jordan, in 2008, as an Assistant
Professor. In 2009, he was appointed as the Dean CHRIS PAPACHRISTOU (Life Fellow, IEEE)
Assistant of the Hijjawi Faculty for Engineering received the Ph.D. degree in electrical engineering
Technology, Yarmouk University. Since 2010, and computer science from Johns Hopkins Uni-
he has been an Associate Professor with the Jordan University of Science versity, Baltimore, MD, USA. He is currently a
and Technology, Irbid. In 2014, he was appointed as the Dean Assistant of Professor of electrical and computer engineering
the Faculty of Engineering, Jordan University of Science and Technology. with Case Western Reserve University, Cleveland,
In 2019, he spent one academic year with The University of Texas at Austin, USA. His research interests include of embedded
Austin, as a Visiting Scholar, sponsored by Fulbright. His current research systems, fault tolerant and secure system design,
interests include mixed signal circuit design, power management systems, VLSI CAD, and reconfigurable computing.
and improving simulation techniques for nonlinear circuits.

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