REDUCE VERIFICATION COMPLEXITY

IN LOW/MULTI-POWER DESIGNS

MAT THEW HOGAN, MENTOR GRAPHICS

W H I T E P A P E R

D E S I G N - T O - S I L I C O N

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Reduce Verification Complexity in Low/Multi-Power Designs

BACKGROUND
The increasing demand for highly reliable products covers many industries, all process nodes, and almost all design
implementations. To satisfy this demand, reliability requirements are growing in all market segments. Ensuring
these requirements are met requires design verification that goes beyond traditional design rule checking (DRC),
layout vs. schematic (LVS) comparison, and electrical rule checking (ERC). Small and large process nodes alike are
affected by these requirements, while both system-on-chip (SoC) and full custom designs also need
comprehensive reliability coverage.

In particular, today’s competitive products demand power-efficient design practices. What does power-efficient
design entail? Designers are using ever-lower voltages wherever practical in a design, reserving higher voltages for
those portions of the design that truly require the additional power. While power-efficient designs may contain
several different voltages, there are often tens, or even hundreds, of power domains—discrete portions of the
design that can be turned on and off to minimize power usage. Accurate and efficient low-power and multiple-
power domain verification requires both knowledge of the overall system’s power intent and careful tracking of
signals crossing these power domains. The ability to evaluate the interactions of different power states at the
transistor level, where bulk connections, floating wells, and other physical implementation details can be verified, is
critical to avoid latch-up conditions and ensure high reliability compliance.

Power-efficient reliability requirements apply to both low power/low voltage and high power/high voltage designs.
If there’s a memory cell, high-voltage gate, or other element with signals that are not directly compatible with the
rest of the design, the designer must make sure there is adequate isolation and protection to ensure a design is
created that is reliable under all operating conditions. Level shifters are often used between different voltages to
ensure smooth transitions (Figure 1), while retention cells are often employed to preserve a circuit’s input values
when its domain is switched off.

Figure 1: On the left, a level

shifter is used to provide a safe
transition between differing
voltages, while on the right, a
retention cell is used to preserve
input values.

Designs that incorporate multiple power domain checks are particularly susceptible to subtle design errors that are
difficult to identify using SPICE simulations or traditional physical verification techniques. These subtle errors often
don’t result in immediate part failure, but performance degradation over time. Figure 2 shows a transistor
connected to different VCCs. If the VCCs are the same voltage, but in different domains, they may be switching on
and off at different times, leading to reliability issues. This type of error is going to be very difficult to catch in a
SPICE simulation. If VCC2 has a greater voltage than VCC1, the device is at risk for gate oxide breakdown, a long-
term reliability issue.

Place and route (P&R) tools most commonly deal with gate-level blocks. Because verification in that environment
does not go down to the transistor or well level to validate transistor biasing, problems like the one shown in Figure
2 will not be identified during the P&R process.

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Transistor-level power intent verification is a critical

need, especially in designs that make extensive use of IP.
SOCs can contain any number of IPs from different
providers, many of which may use different power
designs or contain their own internal global signals, and
each IP must be hooked up correctly within the design.
Without an understanding of the power intent of each
IP, it’s very difficult to proactively prevent reliability
issues (such as power domain crossing errors) from
occurring when the IP is placed into a larger design. In
Figure 3, the voltages internal to the IP block look Figure 2: A transistor connected to two different VCCs is
consistent, but it’s been hooked up incorrectly in the susceptible to long-term performance degradation and
larger implementation. Also, as stated before, even if the reliability issues.
voltages are equal, if they are in different power
domains, they may be switching on and off at different
times, leading to additional reliability issues.

Figure 3: IPs pose two levels of

reliability cerification
challenges—internal verification,
and verification in the context of
a larger implementation.

Another factor in these designs is the use of thinner oxides that allow designers to use lower voltage, and
subsequently, less power. These desirable effects are offset by the sensitivity of these circuits to electrical overstress
(EOS) issues. In addition, some power domain design errors lead to eventual oxide breakdown, which results in
device failures that occur over time. In particular, PMOS devices can be susceptible to negative-bias temperature
instability (NBTI), which leads to the threshold voltage of the PMOS transistor increasing over time. This, in turn,
leads to reduced switching time for logic gates, and induces hot carrier injection (HCI), which then gradually alters
the threshold voltage of NMOS devices. Soft breakdown (SBD) also contributes as a time-dependent failure
mechanism, contributing to the degradation effects of gate oxide breakdown. [3] [4] [5] [6]

A transistor-level power-aware checking tool must also be able to statically propagate voltage values from the
various supplies to every node in the circuit to facilitate a variety of reliability checks. Power-aware checking
requires the ability to use the design’s netlist to recognize specific circuit topologies (such as level shifters, charge
pumps, I/O drivers, and other structures), and then relate those to the corresponding physical implementation that
makes up the layout, to verify that these specific elements have been included and implemented correctly. Unlike
the foundry DRC decks, the definition of these checks may not all come from the foundry—some can be tailored
to the specific design styles and practices of the designer’s company—so flexibility and customizability are
essential features. Thin oxide gates and high-power applications require tight controls for voltage and power
domains. Many of these issues are difficult to identify in the simulation space or with traditional physical verification
techniques.

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TRANSISTOR-LEVEL POWER INTENT VERIFICATION

WITH CALIBRE PERC
While typical hardware description language (HDL) design and checking tools can verify digital designs at the
module level, accurate reliability verification must happen at the transistor level. Calibre® PERC™ provides a new
approach to reliability verification for low-power and multi-power designs, by leveraging the information contained
in the unified power format (UPF) and applying it to transistor-level designs. The UPF provides a way to annotate a
design with the power and power control intent of that design (including such elements as supply nets, supply
sets, power states, power switches, level shifters, isolation, and retention) that is independent of any HDL. UPFs are
typically used at all levels of the design flow for P&R designs.

A UPF specification at the register transfer logic (RTL) level defines the power architecture of a given design, and
drives synthesis and P&R to achieve correct implementation. The UPF enables a consistent description of the power
intent of a design, and provides power state tables that describe each power mode of the design. In automated
reliability verification, using the same UPF specification for transistor level physical verification ensures the original
power intent is preserved with the final implementation.

UPF specifications can be leveraged as an integral part of Calibre PERC’s understanding of power intent. Along with
the design layout data and verification rule deck, Calibre PERC examines the UPF definitions of supply networks
(consisting of power switches, supply ports, and supply nets) and checks each supply port’s supply states and its
connected supply net. Most importantly, it analyzes the power state tables defined in terms of these states to
ensure it captures the legal combinations of supply voltages in the entire design. With integrated support for UPF,
Calibre PERC can assign voltages based on a design’s power intent, greatly improving verification coverage and
robustness [2].

In both custom/analog (which is typically not implemented in HDL designs) and P&R design flows, understanding
how signals cross multiple power domains in the design is paramount to ensuring robust reliability. With its
comprehensive view of the design, Calibre PERC is able to leverage design flows with or without the UPF to
understand the power intent down to the transistor level, then apply reliability verification at the transistor level.
Multiple power and voltage domains can be automatically traced to provide a complete picture of how the design
will interact. Designers can validate design intent for any number of design scenarios, such as ensuring low-power
rules are being honored, or that routing has been correctly implemented in the design. Specifically for low-power
designs, Calibre PERC can ensure that level shifters are in place, that the correct voltages are tied to the devices,
and that the correct protection circuitry is in place for transitions from one domain to another.

This transistor-level power intent verification simplifies multiple-power and low-power verification by enabling a
consistent description of the power intent throughout the design flow. Support for the UPF power state table
allows verification of each power mode within the design, enabling a repeatable, comprehensive, and efficient
design reliability verification methodology using industry standards at the transistor level.

Calibre PERC can also examine all thin oxide transistors of the circuit to catch any occurrence of a voltage across the
device terminals that would lead to gradual oxide breakdown and device failure. A list of thin oxide transistors is
identified by the Calibre PERC rule deck from the complete transistor list that is automatically detected by Calibre
PERC during voltage propagation [1].

Some of the more obvious reliability checks are available from foundries in Calibre PERC rule decks, but specific
methodology rule checks and internal best practices should be provided to augment these rules for complete
coverage. The functionality provided by Calibre PERC rule decks may be easily enhanced to provide verification
beyond standard foundry rule decks to include custom reliability verification requirements. Users can insert
reliability verification into their existing design flows with Calibre PERC as part of an integrated Calibre platform for
cell, block, and full-chip verification. Combining rules expressed in the proprietary SVRF and the Tcl-based TVF

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language across all applications provides users with flexibility to meet the specific and evolving needs of their
design teams, while ensuring compatibility with all foundries.

Debugging is a key component of any verification flow. One common

problem for designers trying to debug power violations at the transistor
level with existing tools is a lack of knowledge of the power intent of the
circuit where the violation is found. Without a clear understanding of how
the circuit works, debugging often becomes a task bogged down with the
elimination of false errors caused by level shifters and other protection
mechanisms that have not been accounted for. Calibre PERC eliminates
these false errors by using a circuit recognition technique to identify
particular topologies used to provide these power domain transitions. For
example, Figure 4 shows a typical level shift circuit [7]. Simply checking for
transistors connected to multiple domains results in a large number of false
errors at the boundary between power domains, where level shifter
Figure 4: Unless level shifters are structures intentionally include transistors exposed to both low and high
recognized by the verification tool, they voltages (i.e., systematic violations would be reported on {M2, M3}
can create false errors that slow down the transistors). However, if these structures are identified by Calibre PERC as
debugging process [7]. level shifters, these false errors can be quickly waived [7].

Additional sources of false errors are the isolation cells

used between OFF and Always-ON domains. The circuit
recognition functionality within Calibre PERC uses the
SPICE syntax as an easy way to define these types of
complex circuit structures (Figure 5). Whenever such
violations are detected, these false errors can be quickly
waived internally by the tool, using topological
recognition [7].

Calibre PERC readily integrates into your design flow,

while Calibre RVE™ provides a results viewing and Figure 5: Isolation cells between to-voltage domains are
debugging environment that can highlight Calibre PERC another example of false positives that can occur without
results and geometries, and access connectivity knowledge of the function of circuit structures [7].
information, to make debugging reliability checks easy,
quick, and thorough (Figure 6).

Figure 6: Calibre PERC results can

be easily and efficiently reviewed
and debugged in Calibre RVE.

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Accurate and repeatable reliability verification is now a critical capability, both for advanced nodes and for
increasingly complex products being produced at established nodes. Calibre PERC is the only comprehensive
solution capable of providing transistor-level power intent verification without the need for SPICE simulation on
both the schematic and layout side of your design. As part of the Calibre platform, it integrates easily into existing
signoff flows, with comprehensive debugging support provided by Calibre RVE. Calibre PERC provides an easy-to-
use, automated verification solution for low-power and multiple-power domain designs, ultimately reducing cost
and time to market, while providing the diagnostic insight to help you improve yield and device reliability.

To learn more about Calibre PERC’s full range of capabilities, visit our website at:

http://mentor.com/perc

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REFERENCES
[1] Lescot, J., Bligny, V., Medhat, D., “Static Low Power Verification at Transistor Level for SoC Design,” Proc. ACM/IEEE
International Symposium on Low Power Electronics and Design (2012), 129-134.
Doi: 10.1145/2333660.2333694
[2] Hogan, M., “Robust Reliability Verification Beyond Traditional Tools and Techniques,” SemiWiki.com (May 2013).
URL: http://www.semiwiki.com/forum/content/2451-robust-reliability-verification.html
[3] Hamed Abrishami, et al., “NBTI-Aware Flip-Flop Characterization and Design,” GLSVLSI’08, May 4–6, 2008
[4] B.C. Paul, K. Kang, H. Kuflouglu, M. A. Alam and K. Roy, “Impact of NBTI on the temporal performance
degradation of digital circuits,” Electron Device Letter, vol. 26, no. 8, pp. 560-562, Aug. 2005.
[5] Hong Luo, et al., “Modeling of PMOS NBTI Effect Considering Temperature Variation,” 8th International
Symposium on Quality Electronic Design (ISQED’07)
[6] Jin Qin, et al., “SRAM Stability Analysis Considering Gate Oxide SBD, NBTI and HCI,, 2007 IIRW FINAL REPORT
[7] Medhat, D., “Power-Aware Verification in Low-Power ICs,” Chip Design (Fall 2012). URL: http://chipdesignmag.
com/display.php?articleId=5163

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