Static CMOS

Designing Combinational Logic Circuits

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Combinational vs. Sequential Logic

In Out
Combinational Combinational
In Logic Out Logic
Circuit Circuit

State

Combinational Sequential

Output = f(In ) Output = f (In, Previous In )

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Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.

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Static Complementary CMOS
VDD

In1
PMOS only
In2 PUN
InN
F(In1,In2,…InN)
In1
In2 PDN
NMOS only
InN

PUN and PDN are dual logic networks

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NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

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PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

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Threshold Drops
VDD VDD
PUN
S D
VDD

D 0  VDD S 0  VDD - VTn

VGS
CL CL

PDN VDD  0 VDD  |VTp|

VGS
D CL S CL
VDD

S D

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Complementary CMOS Logic Style

8
Example Gate: NAND

9
Example Gate: NOR

10
Complex CMOS Gate

B
A
C

D
OUT = D + A • (B + C)
A
D
B C

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 Constructing a Complex Gate
VDD VDD

C
SN1 F SN4 A
F
SN2 B
A A
D D SN3

B C B C D

(a) pull-down network (b) Deriving the pull-up network A

hierarchically by identifying
D
sub-nets
B C

(c) complete gate

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CMOS Properties
 Full rail-to-rail swing; high noise margins
 Logic levels not dependent upon the relative
device sizes; ratioless
 Always a path to Vdd or Gnd in steady state;
low output impedance
 Extremely high input resistance; nearly zero
steady-state input current
 No direct path steady state between power
and ground; no static power dissipation
 Propagation delay function of load
capacitance and resistance of transistors
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Ratioed Logic

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Ratioed Logic

VDD VDD VDD

Resistive Depletion PMOS

Load RL Load VT < 0 Load
VSS
F F F
In1 In1 In1
In2 PDN In2 PDN In2 PDN
In3 In3 In3

VSS VSS VSS

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

Goal: to reduce the number of devices over complementary CMOS

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Ratioed Logic
VDD

Resistive
Load RL

In1
In2 PDN
In3

VSS

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Active Loads
VDD VDD

Depletion PMOS
Load VT < 0 Load
VSS
F F
In1 In1
In2 PDN In2 PDN
In3 In3

VSS VSS

depletion load NMOS pseudo-NMOS

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Pseudo-NMOS

VDD

F
CL
A B C D

VOH = VDD (similar to complementary CMOS)

 V2  k 2
OL p
k  V – V V – -------------  = ------  V – V 
n DD Tn OL 2  2 DD Tp


kp
V = V –V  1– 1 – ------ (assuming that V = V = V )
OL DD T k T Tn Tp
n

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

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