INDEX

Exp. Date Page Marks Signature

Experiment Title
No No

To simulate and synthesis Logic

1 Gates, Adders and Subtractor using
VIVADO

To simulate and synthesis

ENCODER, DECODER,
2 MULTIPLEXER, DEMULTIPLEXER,
MAGNITUDE COMPARATOR using
VIVADO

To simulate and synthesis multiplier

3 using VIVADO.

To simulate and synthesis SR, JK, T,

4 D - FLIPFLOP, COUNTER DESIGN
using VIVADO

To simulate and synthesis finite state

5 machine using VIVADO

To Simulate and Synthesis Inverter

6 using CADENCE
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SIMULATE AND SYNTHESIS LOGIC GATES,

ADDERS AND SUBTRACTOR USING
VIVADO

AIM:
To simulate and synthesis Logic Gates, Adders and Subtractor using VIVADO

APPARATUS REQUIRED: VIVADO 2023.2

PROCEDURE:
STEP:1 Start the Vivado, Select and Name the New project.
STEP:2 Select the device family, device, package and speed.
STEP:3 Select new source in the New Project and select Verilog Module as the Source
type.
STEP:4 Type the File Name and Click Next and then finish button. Type the code and
save it.
STEP:5 Select the Behavioural Simulation in the Source Window and click the check
syntax.
STEP:6 Click the simulation to simulate the program and give the inputs and verify the
outputs as per the truth table.

LOGIC-GATES:

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PROGRAM:
module fs(a,b,c0,c1,c2,c3,c4,c5,c6);
input a,b;
output co,c1,c2,c3,c4,c5,c6;
or g1 (co,a,b);
and g2 (c1,a,b);
xor g3 (c2,a,b);
nand g4 (c3,a,b);
nor g5 (c4,a,b);
not g6(c5,a);
xnor g7 (c6,a,b);
endmodule

OUTPUT:

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HALF ADDER:

PROGRAM:
module ha (a,b,s,c);
input a,b;
output s,c;
xor g1(s,a,b); O and g2 (c,a,b);
endmodule

OUTPUT:

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HALFSUBTRACTOR:

PROGRAM:
module hs (a, b, diff, borr);
input a,b;
output diff, borr;
xor gl (diff,a,borr);
and g2 (borr, -a,b);
endmodule

OUTPUT:

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FULLADDER:

PROGRAM:
module fa (a,b,c,sum, carry);
input a,b,c;
output sum, carry;
wire w1,w2,w3;
xor gl(wl,a,b);
xor g2 (w2,a,b);
xor g3 (sum, w1,c);
and (w3,c,w1);

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or g5 (carry, w3,w2);
endmodule

OUTPUT:

FULLSUBTRACTOR:

PROGRAM:
module fs(a,b,c,diff,borrow);
input a,b,c;
output diff, borrow;
wire w1,w2,w3;
xor gl (wl,a,b);
and g2 (w2,~a,b);
xor g3 (diff,wl,c);

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and (w3,c,~wl);
or g5 (borrow,w3,w2);
endmodule

OUTPUT:

8-BIT-RIPPLE-CARRY-ADDER:

PROGRAM:
module FA(a, b, c, sum, carry);
input a, b, c;
output sum, carry;
assign sum=a ^ b ^ c;
assign carry=a & b|b & c|a & c;
endmodule

module RCA(a, b, c, sum, carry);

input [7:0] a, b;

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input c;
output [7:0] sum;
output carry;
wire [6:0] w;
FA f1(a[0], b[0], c, sum[0], w[0]);
FA f2(a[1], b[1], w[0], sum[1], w[1]);
FA f3(a[2], b[2], w[1], sum[2], w[2]);
FA f4(a[3], b[3], w[2], sum[3], w[3]);
FA f5(a[4], b[4], w[3], sum[4], w[4]);
FA f6(a[5], b[5], w[4], sum[5], w[5]);
FA f7(a[6], b[6], w[5], sum[6], w[6]);
FA f8(a[7], b[7], w[6], sum[7], carry);
endmodule

OUTPUT:

RESULT:

The simulate and synthesis Logic Gates, Adders and Subtractor using VIVADO is su

https://github.com/Udayabharathim/VLSI-LAB-EXP-1/edit/main/README.md 8/8
5/12/24, 10:22 AM VLSI-LAB-EXP-2/README.md at main · Udayabharathim/VLSI-LAB-EXP-2

SIMULATE AND SYNTHESIS ENCODER,

DECODER, MULTIPLEXER,
DEMULTIPLEXER, MAGNITUDE
COMPARATOR USING VIVADO.

AIM:
To simulate and synthesis ENCODER, DECODER, MULTIPLEXER, DEMULTIPLEXER,
MAGNITUDE COMPARATOR using VIVADO.

APPARATUS REQUIRED:
VIVADO 2023.2

PROCEDURE:
STEP:1 Start the Vivado, Select and Name the New project.
STEP:2 Select the device family, device, package and speed.
STEP:3 Select new source in the New Project and select Verilog Module as the
Source type.
STEP:4 Type the File Name and Click Next and then finish button. Type the code
and save it.
STEP:5 Select the Behavioural Simulation in the Source Window and click the check
syntax.
STEP:6 Click the simulation to simulate the program and give the inputs and verify
the outputs as per the truth table.

ENCODER 8:3:

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PROGRAM:
module encoder83df(i, a, b, c);
input [7:0]i;
output a,b,c;
assign a=i[4] | i[5] | i[6] | i[7];
assign b=i[2] | i[3] | i[6] | i[7];
assign c=i[1] | i[3] | i[5] | i[7];
endmodule

OUTPUT:

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DECODER3:8:

PROGRAM:
module decoder_3_8(s,y);
input [2:0]s;
output [7:0]y;
assign y[0]=~s[2]&~s[1]&~s[0];
assign y[1]=~s[2]&~s[1]&s[0];
assign y[2]=~s[2]&s[1]&~s[0];
assign y[3]=~s[2]&s[1]&s[0];
assign y[4]=s[2]&~s[1]&~s[0];
assign y[5]=s[2]&~s[1]&s[0];
assign y[6]=s[2]&s[1]&~s[0];

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assign y[7]=s[2]&s[1]&s[0];
endmodule

OUTPUT:

MULTIPLEXER 8:1:

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PROGRAM:
module Mux 8 1 (s0,s1,s2, i,y);
input [7:0]i;
input 50, s1,s2;
output y;
wire [7:0]w;
assign w[0]=(~s2) & (~sl) & (~50)&i[0];
assign w[1]=(~32)&(~51) & (50) &i [1];
assign w[2]=(~52) & (sl) & (~50)&i [2];
assign w[3]=(~52) & (51) & (50) &i [3];
assign w[4]=(s2) & (sl) & (~50)&i [4];
assign w[5]=(s2) & (sl) & (s0) &i [5];
assign w[6]=(52) & (51)&(~50)&i [6];
assign w[7]=(s2) & (51) & (s0)&i [7];
assign y=w[0][w[1] w[2] w[3] w[4] w[5] w[6] w[7];
endmodule

OUTPUT:

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DEMULTIPLEXER 1:8:

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PROGRAM:
module fa (a,b,c,sum, carry);
input a,b,c;
output sum, carry;
wire w1,w2,w3;
xor gl(wl,a,b);
xor g2 (w2,a,b);
xor g3 (sum, w1,c);
and (w3,c,w1);
or g5 (carry, w3,w2);
endmodule

OUTPUT:

COMPARATOR:

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PROGRAM:
module comparator(a,b,l,g,e);
input [3:0]a,b;
output reg l,g,e;
always@(*)
begin
if(a>b)
begin
l=1'b0;
g=1'b1;
e=1'b0;
end
else if(a<b)
begin
l=1'b1;
g=1'b0;
e=1'b0;
end
else
begin
l=1'b0;
g=1'b0;
e=1'b1;
end
end
endmodule

OUTPUT:

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RESULT:
The simulate and sythesis ENCODER, DECODER, MULTIPLEXER, DEMULTIPLEXER,
MAGNITUDE COMPARATOR using VIVADO is successfully verified.

https://github.com/Udayabharathim/VLSI-LAB-EXP-2/blob/main/README.md 9/9
5/12/24, 10:24 AM Udayabharathim/VLSI-LAB-EXP-3

SIMULATION AND IMPLEMENTATION

OF MULTIPLIER

AIM:
To simulate and synthesis multiplier using VIVADO.

APPARATUS REQUIRED:
VIVADO 2023.2

PROCEDURE:
STEP:1 Start the Vivado, Select and Name the New project.
STEP:2 Select the device family, device, package and speed.
STEP:3 Select new source in the New Project and select Verilog Module as the
Source type.
STEP:4 Type the File Name and Click Next and then finish button. Type the code
and save it.
STEP:5 Select the Behavioural Simulation in the Source Window and click the check
syntax.
STEP:6 Click the simulation to simulate the program and give the inputs and verify
the outputs as per the truth table.

2- BIT MULTIPLIER

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PROGRAM:
module ha(a,b,s,carry);
input a,b;
output s,carry;
assign carry=a&b;
endmodule
module multiplier_2(a,b,c);
input [1:0]a,b;
output [3:0]c;
wire w;
assign c[0]=a[0]&b[0];
ha h1(a[0]&b[1],a[1]&b[0],c[1],w);
ha h2(a[1]&b[1],w,c[2],c[3]);
endmodule

OUTPUT:

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4- BIT MULTIPLIER:

PROGRAM:

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module ha(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule

module fa(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(a&c);
endmodule

module multi_4(a,b,p);
input[3:0]a,b;
output [7:0]p;
wire [17:1]w;
assign p[0]=a[0]&b[0];
ha h1(a[1]&b[0],a[0]&b[1],p[1],w[1]);
fa f1(w[1],a[2]&b[0],a[1]&b[1],w[2],w[3]);
fa f2(w[3],a[3]&b[0],a[2]&b[1],w[4],w[5]);
ha h2(a[3]&b[1],w[5],w[6],w[7]);
ha h3(a[0]&b[2],w[2],p[2],w[8]);
fa f3(w[8],a[1]&b[2],w[4],w[9],w[10]);
fa f4(w[10],a[2]&b[2],w[6],w[11],w[12]);
fa f5(w[12],w[7],a[3]&b[2],w[13],w[14]);
ha h4(a[0]&b[3],w[9],p[3],w[15]);
fa f6(w[15],a[1]&b[3],w[11],p[4],w[16]);
fa f7(w[16],a[2]&b[3],w[13],p[5],w[17]);
fa f8(w[17],w[14],a[3]&b[3],p[6],p[7]);
endmodule

OUTPUT:

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RESULT:

The simulate and synthesis multiplier using VIVADO is successfully verified.

https://github.com/Udayabharathim/VLSI-LAB-EXP-3?tab=readme-ov-file 5/5
5/12/24, 10:25 AM Udayabharathim/VLSI-LAB-EXP-4

SIMULATE AND SYNTHESIS SR, JK, T, D

- FLIPFLOP, COUNTER DESIGN USING
VIVADO.

AIM:
To simulate and synthesis SR, JK, T, D - FLIPFLOP, COUNTER DESIGN using VIVADO.

APPARATUS REQUIRED:
VIVADO 2023.2

PROCEDURE:
STEP:1 Start the Vivado, Select and Name the New project.
STEP:2 Select the device family, device, package and speed.
STEP:3 Select new source in the New Project and select Verilog Module as the
Source type.
STEP:4 Type the File Name and Click Next and then finish button. Type the code
and save it.
STEP:5 Select the Behavioural Simulation in the Source Window and click the check
syntax.
STEP:6 Click the simulation to simulate the program and give the inputs and verify
the outputs as per the truth table.

SR FLIPFLOP:

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PROGRAM:
module sr_ff(clk,q,rst,s,r);
input s,r,clk,rst;
output reg q;
always@(posedge clk)
begin
if(rst==1)
q=1'b0;
else
begin
case({s,r})
2'b00:q=q;
2'b01:q=1'b0;
2'b10:q=1'b1;
2'b11:q=1'bx;
endcase
end
end
endmodule

OUTPUT:

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JK FLIPFLOP:

PROGRAM:
module jk_ff(clk,q,rst,j,k);
input j,k,clk,rst;
output reg q;
always@(posedge clk)

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begin
if(rst==1)
q=1'b0;
else
begin
case({j,k})
2'b00:q=q;
2'b01:q=1'b0;
2'b10:q=1'b1;
2'b11:q=~q;
endcase
end
end
endmodule

OUTPUT:

T FLIPFLOP

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PROGRAM:
module t_ff(clk,q,rst,t);
input t,clk,rst;
output reg q;
always@(posedge clk)
begin
if(rst==1)
q=1'b0;
else
if(t==0)
q=q;
else
q=~q;
end
endmodule

OUTPUT

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D FLIPFLOP:

PROGRAM:
module d_ff(clk,q,rst,d);
input d,clk,rst;
output reg q;
always@(posedge clk)
begin

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if(rst==1)
q=1'b0;
else
q=d;
end
endmodule

OUTPUT:

MOD 10 COUNTER

PROGRAM
module mod_10(clk,rst,out);
input clk,rst;
output reg[3:0]out;
always@(posedge clk)

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begin
if(rst==1|out==9)
out=4'b0;
else
out=out+1;
end
endmodule

OUTPUT

UP-DOWN-COUNTER

PROGRAM

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module updown_counter(clk,rst,ud,out); input clk,rst,ud; output reg[3:0]out;

always@(posedge clk) begin if(rst==1) out=4'b0; else if (ud==1) out=out+1; else
if(ud==0) out=out-1; end endmodule

OUTPUT

RESULT:

The simulate and synthesis SR, JK, T, D - FLIPFLOP, COUNTER DESIGN using VIVA

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5/11/24, 9:23 PM VLSI-LAB-EXP-5/README.md at main · Udayabharathim/VLSI-LAB-EXP-5

SIMULATION AND IMPLEMENTATION OF

FINITE STATE MACHINE

AIM:
To simulate and synthesis finite state machine using Xilinx ISE.

APPARATUS REQUIRED: VIVADO 2023.2

PROCEDURE:
STEP:1 Start the Xilinx navigator, Select and Name the New project.
STEP:2 Select the device family, device, package and speed.
STEP:3 Select new source in the New Project and select Verilog Module as the Source
type.
STEP:4 Type the File Name and Click Next and then finish button. Type the code and
save it.
STEP:5 Select the Behavioral Simulation in the Source Window and click the check
syntax.
STEP:6 Click the simulation to simulate the program and give the inputs and verify the
outputs as per the truth table.
STEP:7 Select the Implementation in the Sources Window and select the required file in
the Processes Window.
STEP:8 Select Check Syntax from the Synthesize XST Process. Double Click in the
Floorplan Area/IO/Logic-Post Synthesis process in the User Constraints process group.
UCF(User constraint File) is obtained.
STEP:9 In the Design Object List Window, enter the pin location for each pin in the Loc
column Select save from the File menu.
STEP:10 Double click on the Implement Design and double click on the Generate
Programming File to create a bitstream of the design.(.v) file is converted into .bit file
here.
STEP:11 On the board, by giving required input, the LEDs starts to glow light,
indicating the output.
STEP:12 Load the Bit file into the SPARTAN 6 FPGA

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Logic Diagram :

VERILOG CODE:
module fsm(clk,rst,x,z);
input clk,rst,x;
output z;
reg [2:1] ps,ns;
parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;
always@(x,posedge clk)
case(ps)
s0:if(x)
ns=s1;
else
ns=s0;
s1:if(x)
ns=s1;
else
ns=s2;
s2:if(x)
ns=s3;
else
ns=s0;
s3:if(x)

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ns=s1;
else
ns=s0;
endcase
always@(posedge clk)
if(rst)
ps<=s0;
else
ps=ns;
assign z=(ps==s3);
endmodule

OUTPUT:

RESULT:
The simulate and synthesis of finite state machine using VIVADO is successfully
verified.

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5/11/24, 10:12 PM VLSI-LAB-EXP-6/README.md at main · Udayabharathim/VLSI-LAB-EXP-6

SIMULATE AND SYNTHESIS INVERTER USING CADENCE

AIM:
To Simulate and Synthesis Inverter using CADENCE

APPARATUS REQUIRED: CADENCE VIRTUOSO

PROCEDURE:
STEP:1 Cadence Virtuoso open procedere
STEP:2 Open MobaXterm
STEP:3 Click on Session (Top left Cornet)
STEP:4 Choose SSH
STEP:5 In Remote Host enter then on Password" Student @Cadence. Saves the.in"
STEP:6 Type Exdg-open Hiphen, alles open Space New window will be opened (all is
small)
STEP:7 Create a new folder
STEP:8 Right click on folder window open
STEP:9 Terminal Command window will be opened
STEP:10 In Command window type the following.
->pwod
->tcsh
->Spate →SEU Source / Cadence / Install /cshrc
->Welcome to Cadence tools suite"
->Virtuoso.
STEP:11 Analog design window will be opened
STEP:12 Analog design using Virtuoso
STEP:13 In Virtuoso 6.1.8-646
STEP:14 File New library library nanae"
STEP:15 Choose Attach to an existing technology library
STEP:16 Choose the folder where you. need to work
->ok gpak 180 Apply
STEP:17 File cell veew choose library Type coll name
STEP:18 Schematic windere will be opened

https://github.com/Udayabharathim/VLSI-LAB-EXP-6/blob/main/README.md 1/5
5/11/24, 10:12 PM VLSI-LAB-EXP-6/README.md at main · Udayabharathim/VLSI-LAB-EXP-6

INVERTER:

OUTPUT:

https://github.com/Udayabharathim/VLSI-LAB-EXP-6/blob/main/README.md 2/5
5/11/24, 10:12 PM VLSI-LAB-EXP-6/README.md at main · Udayabharathim/VLSI-LAB-EXP-6

NAND:

OUTPUT:

https://github.com/Udayabharathim/VLSI-LAB-EXP-6/blob/main/README.md 3/5
5/11/24, 10:12 PM VLSI-LAB-EXP-6/README.md at main · Udayabharathim/VLSI-LAB-EXP-6

NOR:

OUTPUT:

https://github.com/Udayabharathim/VLSI-LAB-EXP-6/blob/main/README.md 4/5
5/11/24, 10:12 PM VLSI-LAB-EXP-6/README.md at main · Udayabharathim/VLSI-LAB-EXP-6

RESULT:

The Simulate and Synthesis Inverter using CADENCE is successfully verified.

https://github.com/Udayabharathim/VLSI-LAB-EXP-6/blob/main/README.md 5/5