SystemVerilog-2009 Enhancements:

Priority/Unique/Unique0
Clifford E. Cummings
Sunburst Design, Inc.
14355 SW Allen Blvd., Suite #100
Beaverton, OR 97005
1-503-641-8446
[email protected]

ABSTRACT potential for enhanced error trapping capabilities. The error

SystemVerilog-2009 enhanced the case / if modifiers, trapping is still insufficient for most design teams but
priority & unique, with new scheduling semantics to help recommendations are included at the end of this paper to describe
how EDA tool vendors can remedy the insufficiencies that still
correctly identify more bugs during simulation. SystemVerilog-
exist through tool command lines options (see section 9).
2009 also added a new unique0 keyword to emulate the
parallel_case capability of synthesis tools. This paper will
detail how these two enhancements will help to accurately
2. FULL_CASE BASICS
When an engineer declares that a case statement is a
identify more bugs in a design and provide better synthesis results
for a certain class of designs. full_case case statement, the engineer is asserting that all
possible matching conditions have been listed as case items and
that any unlisted possibility is not reachable by the actual logic;
General Terms therefore, the other conditions are don't-care conditions.
Verilog, SystemVerilog, full_case, parallel_case, priority, unique,
unique0, simulation, synthesis. An easy way to understand full_case is to compare a case
statement to a Karnaugh map (K-map) as taught in undergraduate
engineering classes.
Keywords
SystemVerilog, full_case, parallel_case, priority, unique, unique0. In the K-map for any given output variable, the engineer notes
when the output is a 1 and when it is a 0. If there are input
conditions that cannot be reached, those K-map squares are filled
1. INTRODUCTION with X's to indicate don't-care conditions. The synthesis tool can
The SystemVerilog priority and unique keywords,
then optionally incorporate the X's to build simpler product terms
described in this paper, actually pre-date the SystemVerilog
for the K-map. The simpler product terms translate into smaller
language and were part of the Superlog language, most of which
and faster logic.
was donated to Accellera and became the foundation for the early
Accellera SystemVerilog 3.0 Standard[7]. These keywords It should be noted that the full_case directive is disabled if
offered a simulation-aware replacement for the existing comment- the case statement includes a case-default statement.
style synthesis directives full_case and parallel_case.
It should also be noted that one typically will get the same
Although the new SystemVerilog keywords made it possible to synthesis results if the full_case directive is replaced with a
detect illegal simulation conditions that would cause a mismatch case-default where every signal assigned in the body of the
between pre- and port-synthesis simulations, over the past eight case statement is assigned the value of X in the case-
years it was discovered through usage of these constructs in default.
SystemVerilog designs that their defined semantics still lacked
minor features and important error-trapping capabilities. The biggest problem with the full_case directive is that it is a
potential command to the synthesis tool but it is a comment to the
The SystemVerilog-2009 Standard[6] has taken important steps to simulator, so if the full_case directive causes the synthesis
close the shortfalls in both features and error detection. This paper
tool to take actions to optimize the design, those same
describes existing priority and unique semantics and then
optimizations will not be executed by the simulator, which makes
introduces the new unique0 keyword semantics and the
it possible to have a mismatch between pre- and post-synthesis
simulations. This can be the source of design problems in the final
synthesized design[1].

3. PARALLEL_CASE BASICS
When an engineer declares that a case statement is a
parallel_case case statement, the engineer is asserting that
it is only possible to match the case expression to one and only
one (or none) of the case items. The engineer has declared that the
case expression shall only uniquely match up to only one of the that is tested during simulation, and (2) if during simulation a
case items. priority case command is executed but the case expression
does not match any of the case items, the simulator will report a
This declaration is intended to inform the synthesis tool that no
warning or violation (see sections 7 and 8).
priority encoders are required to build the logic in the case
statement and that each tested case item in the case statement When an engineer adds the priority keyword to a case
can be treated as if it were a unique if statement. The resultant statement, the engineer has assumed that it is only possible to
logic would be both smaller and faster than if the case items had match the defined case items in the case statement and therefore
been assembled into a set of priority logic. it is safe to treat all other potential matching patterns as don't-
cares. If during simulation, none of the listed case items matches
Like the full_case directive, the biggest problem with the
the case expression, then the engineer's initial assumption was
parallel_case directive is that it is a potential command to wrong and it should be flagged as some form of violation for the
the synthesis tool but it is a comment to the simulator, so if the engineer to fix, because the synthesis tool has been directed to
parallel_case directive causes the synthesis tool to take treat the unspecified pattern as a don't-care. From a designer's
actions to optimize the design, those same optimizations will not perspective, the best simulation behavior under these
be executed by the simulator, which again makes it possible to circumstances would be to abort the simulation with a violation
have a mismatch between pre- and post-synthesis simulations. message (see sections 8 and 9). This would help eliminate
This again can be the source of design problems in the final incorrect design assumptions that could cause the design to have a
synthesized design. fatal design flaw.

4. PRIORITY KEYWORD If the priority case statement contains a case-default

The priority keyword was added to the SystemVerilog statement, the priority testing will be disabled because every
language to be a simulation-aware replacement for the execution of the case statement must match something, even if it
full_case comment-style directive[5]. is just the default statement.

Apology - on behalf of most of the SystemVerilog Standards 4.2 Priority If

Group, I apologize for the choice of the priority keyword. The ability to add the priority keyword to an if statement is
Most on the SV Standards Group believe it is a terrible keyword new to SystemVerilog-2005 and allows an engineer to specify
that does not describe the actual behavior imposed by this if-else-if statements where all conditions that would be
keyword. A case statement is already a priority statement. covered by an else statement are treated as don't-care conditions
Within both Verilog and SystemVerilog, if the case expression by a synthesis tool.
matches a case item, the case item expression is executed and
there is an implied break that causes the case statement to skip Just as a case-default disables the effects of a priority
testing all of the trailing case items, which raises the question, case, an else-statement attached to the end of a priority-
how does a priority keyword change the implementation of if-else-if statement will disable the effects of the priority
the design if a case statement already behaves like a priority keyword.
expression? The priority keyword does not add priority
As with the priority case statement, the priority if
semantics to a case statement because, by its nature, a case
statement requires that one of the tested conditions be matched
statement already has priority semantics. So what does the
during simulation, otherwise the simulator is required to report a
priority keyword really do?
violation message.
From a synthesis perspective, the priority keyword really has
the same semantics as the old full_case directive. Most of the 5. UNIQUE KEYWORD
SystemVerilog Standards Group believes that it would have been The unique keyword was added to the SystemVerilog language
better to replace the priority keyword with either a full_case to be a simulation-aware replacement for the combined
or all_cases keyword. The latter two would have provided a better full_case parallel_case comment-style directives.
description of the intended behavior. Unfortunately, we On behalf of most of the SystemVerilog Standards Group, unlike
discovered this confusion and potential solution too late. the priority keyword, we are quite proud of the unique
Perhaps the SystemVerilog Standards Group should consider keyword. Most of us believe that the unique keyword is a far
adding one of the keywords, full_case or all_cases as a synonym superior description of the intended check over the older and
for the priority keyword. equivalent full_case and parallel_case comment-style
synthesis commands.
4.1 Priority Case The unique keyword directs the compiler and/or simulator to
As mentioned above, a priority case construct informs the
ensure that whenever the corresponding case-statement or if-
synthesis tool that all possible cases have been defined and that
statement is executed, that one of the tested items is matched and
any unlisted case items can be used as don't-cares during
that it is possible to match one and only one of the tested
synthesis optimization.
alternatives, that the testing uniquely matches one of the tested
The advantages that the priority case statement has over the items and can uniquely match only one of the alternatives.
full_case statement are: (1) the full_case is just a
Uniqueness testing can also be treated like a onehot test, meaning
comment to the simulator, while priority case is an assertion that only one of the tested alternatives can match, but also that
one of the tested alternatives MUST match. So the unique module dec2_4a (
testing also encompasses the priority testing requirement, output logic [3:0] y,
which is why an engineer will never use both unique and input logic [1:0] a,
priority on the same if or case statement (unlike the input logic en);
common grouping of full_case parallel_case).
always_comb begin
y = '0;
5.1 Unique Case case ({en,a})
As mentioned above, a unique case construct informs the 3'b100 : y[a]='1;
synthesis tool that all possible cases have been defined, that any 3'b101 : y[a]='1;
unlisted case items can be used as don't-cares during synthesis 3'b110 : y[a]='1;
optimization and that the case expression shall only match one of 3'b111 : y[a]='1;
the case items so it is not necessary for the synthesis tool to build endcase
any priority logic dependencies between the case items. end
endmodule
The advantages that the unique case statement has over the
Example 1 - Efficient 2-to-4 decoder model (no priority or
full_case parallel_case directive are: (1) the
unique keywords used)
full_case parallel_case directive is just a comment to
the simulator, while unique case is an assertion that is tested
during simulation, (2) if during simulation a unique case
This case statement is not "full" because it does not list any of
command is executed but the case expression does not match any
the cases when enable is 0. This style is a recommended coding
of the case items, the simulator will report a warning or violation
style because all of the default cases have been covered by the
and (3) if during simulation it is determined that more than one of
initial assignment at the top of the procedure (guarantees removal
the case items of a unique case could be executed, the
of latches) and then all of the exception conditions are noted in
simulator will report a uniqueness violation.
the case statement.
5.2 Unique If Sample synthesized logic for example Example 1 is shown in
The ability to add the unique keyword to an if statement is Figure 1.
new to SystemVerilog-2005 and allows an engineer to specify
if-else-if statements where all conditions that would be
covered by an else statement are treated as don't-care conditions
by a synthesis tool. It also asserts that it is not possible during
simulation to match more than one of the if-tested conditions,
which informs a synthesis tool that no large and slow priority
encoders are required to build the if-specified logic equations.
Just as a case-default disables the effects of the full_case
testing, an else-statement attached to the end of a unique-if-
else-if statement will disable the priority-case effects
(fullness testing) of the unique keyword but still retain the
uniqueness testing.

6. UNIQUE0 KEYWORD (*NEW*)

Since the introduction of the priority and unique keywords,
it has been observed that there are some designs that would
benefit from the uniqueness testing without the requirement to Figure 1 - 2-to-4 Decoder with enable - correct synthesis result
match one of the case items or if-else-if tested items. For
this reason, the unique0 keyword was added to the SystemVerilog added the unique keyword, which allowed the
SystemVerilog-2009 Standard[6]. simulator to give run-time warnings if (a) the case expression
could match more than one of the case items, or (b) if the case
The unique0 keyword is a simulation equivalent to the older expression did not match any of the case items.
parallel_case comment-style synthesis directive.
The unique keyword informs the synthesis tool that (a) the case
6.1 Unique0 Case (*New*) items are unique so do not build priority logic base on case-item
To understand the motivation for the unique0 keyword, order, and (b) all possible case conditions are listed (this is a full
case) so the output for any unspecified case item combination can
consider the example of an efficient 2-to-4 decoder in Example 1.
be treated as a don't-care. The latter condition overrides any pre-
At the top of the always_comb procedure, the y-output is
default assignment that might have been specified at the top of the
initialized to 0, and then only if the enable is set to 1 will one of
procedure.
the four outputs be reset to 0 inside of the case statement.
Now consider the 2-to-4 decoder of example Example 2. The the full_case simulation testing and synthesis optimization,
code is identical to example Example 1 except the unique an engineer had to add an empty case-default (remember, the
keyword has been added to the case statement. case-default cancels the priority case testing).
module dec2_4b ( module dec2_4c (
output logic [3:0] y, output logic [3:0] y,
input logic [1:0] a, input logic [1:0] a,
input logic en); input logic en);

always_comb begin always_comb begin

y = '0; y = '0;
unique case ({en,a}) unique case ({en,a})
3'b100 : y[a]='1; 3'b100 : y[a]='1;
3'b101 : y[a]='1; 3'b101 : y[a]='1;
3'b110 : y[a]='1; 3'b110 : y[a]='1;
3'b111 : y[a]='1; 3'b111 : y[a]='1;
endcase default: ; // empty default
end endcase
endmodule end
Example 2 - Flawed 2-to-4 decoder model with unique case endmodule
statement Example 3 - SystemVerilog-2005 empty-default work-around
to replicate parallel_case functionality
Upon examination, it can be seen that the case statement only
defines four out of eight possible case conditions. The four Although this is a reasonable work-around, it is a rather awkward
conditions defined are the four conditions when the en input is looking piece of code that often requires explanation.
set to 1. The unique keyword informs the synthesis tool that the
To avoid the awkward, empty-default of Example 3,
four conditions when en is 0 are don't-care conditions (overriding
SystemVerilog-2009 added the ability to use a unique0
the pre-default at the top of the always_comb procedure). The
directive that would allow uniqueness testing while avoiding the
synthesis tool therefore concludes that since the output is a don’t-
full_case testing without the addition of the awkward empty
care whenever the en input is low, that the en input is a don't-
default statement.
care and the en input is optimized out of the design as shown in
Figure 2. Example 4 shows the preferred use of the unique0 case
statement. This example code synthesizes to the correct 2-to-4
decoder implementation, just like the implementation shown in
Figure 1.
module dec2_4d (
output logic [3:0] y,
input logic [1:0] a,
input logic en);

always_comb begin
y = '0;
unique0 case ({en,a})
3'b100 : y[a]='1;
3'b101 : y[a]='1;
3'b110 : y[a]='1;
3'b111 : y[a]='1;
endcase
end
endmodule
Example 4 - SystemVerilog-2009 unique0 case decoder to
Figure 2 - 2-to-4 Decoder with dangling enable - WRONG replicate parallel_case functionality
synthesis result
One of the nice features of the unique0 keyword is that it forces
Since unique is a recognized simulation keyword with the simulator to ensure that either none or only one of the case
simulation semantics, the simulation should report a violation items can be reached during execution of any case statement.
whenever the always_comb procedure is executed when en =
0. When one compares making a pre-default assignment prior to a
case statement, to adding a case-default, I have found that
For the 2-to-4 decoder model, it is desirable to add uniqueness making the pre-default assignment is both more effective at
testing without adding the full_case testing and optimization. removing latches and typically yields equal or better synthesis
Prior the to addition of the unique0 keyword, in order to cancel
results. Why does a pre-default remove latches better than a priority/unique cannot be reliably used because it is too
case-default? easy for design errors to go unnoticed. Engineers have requested a
more strongly tested version of the same constructs; hence, the
Consider the 2-to-4 decoder with case-default in Example 5.
SystemVerilog-2009 violation enhancement of the next section.
module dec2_4e (
output logic [3:0] y, 8. SYSTEMVERILOG-2009 VIOLATIONS
input logic [1:0] a, (*NEW*)
input logic en);
In SystemVerilog-2009, a new type of violation checking replaces
the SystemVerilog-2005 warning checks for unique and
always_comb begin
unique case ({en,a}) priority constructs, as well as the new unique0 construct.
3'b100 : y[a]='1; Strictly speaking, the violation checking is not a stronger check; it
3'b101 : y[a]='1; is just a different check, but with user encouragement, we might
3'b110 : y[a]='1; convince EDA vendors to turn the violation into a stronger check
3'b111 : y[a]='1; (see section 9).
default: y = '0; Clause 12.4.2.1 of the new SystemVerilog-2009 standard states:
endcase
end A unique, unique0, or priority violation check is
endmodule evaluated at the time the statement is executed, but violation
Example 5 - ERROR - 2-to-4 decoder with case-default - reporting is deferred until the Observed region of the current
infers latches time step.
In this decoder example, the combination of unique case with
case-default appears to have all possible cases covered, but Since all module RTL code is executed in the Active Region set
the common mistake is that the explicit case items only set one of that includes the Active events region where all of the properly
the four outputs, which means that the other three outputs must coded[2] always_comb procedures are executed, the
remain unchanged (they must be latched). combinational logic will iterate and settle out within the Active
region before any violations can be reported in the Observed
It is very easy to make a latch-inference coding mistake using a region (see Figure 3).
case-default when multiple outputs are assigned in the same
case statement. If the same case-default is repositioned to
be a pre-default assignment at the top of the always_comb
block, then all latches will be removed. As long as all outputs are
assigned to anything (even X's) at the top of the procedure, no
latch inference will occur. This technique is simple, effective and
synthesis efficient.

6.2 Unique0 If (*New*)

The SystemVerilog-2009 Standard also allows the unique0
keyword to be added to an if-else-if statement.
Just like a unique0 case , the unique0 if imposes
uniqueness testing but does not require any of the tested if
conditions to be matched during simulation. In synthesis, no
priority encoder will be built from the conditions tested in the if-
else-if statement.

7. SYSTEMVERILOG-2005 WARNINGS
SystemVerilog-2005 requires a simulator to report warnings if a Figure 3 - SystemVerilog-2009 Event Scheduling - Violation
priority or unique test-expression does not match any of the checks in Observed Region
listed case items or if-tests.
Consider the fully coded 2-to-1 mux example based on the
SystemVerilog-2005 similarly requires a simulator to report example code in clause 12.5.3.1 of the IEEE SystemVerilog-2009
warnings if a unique case test-expression would match more Standard.
than one of the listed case items during simulation, or if more than The descriptions in 12.5.3 mentions several cases in which a
one of the unique if-test conditions would match during violation report shall be generated by unique-case, unique0-
simulation. case, or priority-case statements. These violation checks
The priority testing is essentially a strict must-match test shall be immune to false violation reports due to zero-delay
while the unique testing is essentially a strict onehot test. glitches in the active region set (see 4.4.1).

Unfortunately, because these are warnings and not fatal errors,

they are easy to miss, and many engineers have told me that
The mechanics of handling zero-delay glitches shall be identical (3) When process b1 completes, process a1 would then trigger
to those used when processing zero-delay glitches for unique- and invert the value of not_a.
if, unique0-if, and priority-if constructs (see 12.4.2.1).
(4) When not_a is inverted, it will again trigger process b1
The following is an example of a unique-case that is immune while still in the Active events region.
to zero-delay glitches in the active region set:
(4a) In process b1, the unique case will determine that there is
module sv_logic1 ( no overlap in the case items, so the scheduled violation in the
output logic z, Observed region will be flushed. From this example, it can
input logic a, b, c); be seen that although there was a momentary glitch where
the unique case would have reported a violation, the
logic not_a; logic settled to a valid state to satisfy the unique case
assumption and no violation will be reported.
always_comb begin: a1
not_a = ~a; A note about violations and combinational logic. The violation
end enhancement works with 0-delay combinational RTL code, which
is sufficient for most RTL coders. If the separate assignments had
always_comb begin: b1 unit delays between updates, there could be multiple
unique case (1'b1) combinational settling violations during simulation. One the
a : z = b; design is synthesized and rendered into a gate-level
not_a : z = c; representation, the unique/unique0/priority keywords
endcase will have been removed so even gate-level models with delays
end will not be subject to these RTL-related violations.
endmodule
Example 6 - 2-to-1 mux implemented with two concurrent
always_comb blocks
9. FATAL ON VIOLATION
Although the introduction of violations is a good first step, most
engineers want a simulation to abort on an error. Although not
required by the IEEE Std 1800-2009, it would be most useful if
EDA vendors would provide a command line switch to enable
aborting on a violation of the unique/unique0/priority
constructs. The command line switch would be optional and could
be easily turned off to disable aborting on violations.
The only reason to add the unique/unique0/priority
keywords to an RTL design is to inform the synthesis tool of a
design assumption that would allow optimization of the RTL
design during synthesis. If the assumption is incorrect, the
engineer would like to be notified by having a simulation abort,
forcing the engineer to examine the circumstances that caused the
design to abort.
If it becomes possible to enable abort-on-violation for the
unique/unique0/priority constructs, many design teams
Figure 4 - Violation scheduling and removal from concurrent would mandate that the switch be permanently enabled during
always_comb blocks simulation to catch these potentially fatal design errors.

In this example the unique case is checking for overlap in the If vendors are unwilling to provide the abort-on-violation
two case_item selects. When a and not_a are in states 0 and 1 capability, then this enhancement has done nothing more than to
respectively and a transitions to 1, the following sequence of change the warning messages from "warning" to "violation" and
events can happen (see Figure 4): little has been gained.

(1) a changes from 0 to 1, which would cause process a1 and Engineers, unite! Tell your vendors that you would like a vendor
b1 to trigger with indeterminate order. For this example, option (such as a command line switch) to force
assume that process b1 triggers first. priority/unique violations to cause the simulation to abort.

(2) Process b1 triggers and both a and not_a both 10. ACKNOWLEDGEMENTS
momentarily have the values of 1. My thanks to my friends and colleagues Heath Chambers of HMC
Design Verification and Shalom Bresticker of Intel Israel for
(2a) In process b1, the unique case could be executed while a
offering valuable suggestions to improve the quality and content
and not_a are both true, so the violation check for of this paper.
uniqueness will fail, and the scheduled failure will be
reported in the Observed region.
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Boston, MA, 1999. Also available at [5] "IEEE Standard For SystemVerilog - Unified Hardware
www.sunburst-design.com/papers Design, Specification and Verification Language," IEEE
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Verilog Synthesis, Coding Styles That Kill!,” SNUG-2000 2005
proceedings, March 2000. Also available at [6] "IEEE Standard For SystemVerilog - Unified Hardware
www.sunburst-design.com/papers Design, Specification and Verification Language," IEEE
[3] Don Mills and Clifford E. Cummings, “RTL Coding Styles Computer Society, IEEE, New York, NY, IEEE Std 1800-
That Yield Simulation and Synthesis Mismatches,” SNUG- 2009
1999 Proceedings, March 1999. Also available at [7] "SystemVerilog 3.0 Accellera's Extensions to Verilog,"
www.lcdm-eng.com/papers.htm and www.sunburst- Accellera, 2002, freely downloadable from:
design.com/papers www.systemverilog.org