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Sardar Patel Institute of Technology: Experiment No. 2

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6 views6 pages

Sardar Patel Institute of Technology: Experiment No. 2

See what u want to see

Uploaded by

anshsharma497097
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We take content rights seriously. If you suspect this is your content, claim it here.
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Sardar Patel Institute of Technology

Bhavan’s Campus, Munshi Nagar, Andheri (West), Mumbai-400058-India


(Empowered Autonomous Institute Affiliated to University of Mumbai)
Electronics and Telecommunication Engineering Department
Academic year 2024-2025

Experiment No. 2

AIM : To Design, implement and verify the functionality of decoder circuit in VHDL using behaviorial
style of modelling (active high)

PROBLEM STATEMENT:

1) Draw the schematic of the given combinational circuits. Write truth table in support of the
given combinational circuits.

2) Develop the VHDL code of the given combinational circuits. Simulate in Vivado design suite and
verify the truth table.

3) Take the screenshot of simulation showing verification of Truth table of the given combinational
circuits.

SCHEMATIC DIAGRAM:

Name: Ansh Sharma Batch: B3


UICD: 2023200108 Class-S.E.-B
Sardar Patel Institute of Technology
Bhavan’s Campus, Munshi Nagar, Andheri (West), Mumbai-400058-India
(Empowered Autonomous Institute Affiliated to University of Mumbai)
Electronics and Telecommunication Engineering Department
Academic year 2024-2025

Name: Ansh Sharma Batch: B3


UICD: 2023200108 Class-S.E.-B
Sardar Patel Institute of Technology
Bhavan’s Campus, Munshi Nagar, Andheri (West), Mumbai-400058-India
(Empowered Autonomous Institute Affiliated to University of Mumbai)
Electronics and Telecommunication Engineering Department
Academic year 2024-2025

Name: Ansh Sharma Batch: B3


UICD: 2023200108 Class-S.E.-B
Sardar Patel Institute of Technology
Bhavan’s Campus, Munshi Nagar, Andheri (West), Mumbai-400058-India
(Empowered Autonomous Institute Affiliated to University of Mumbai)
Electronics and Telecommunication Engineering Department
Academic year 2024-2025

HDL PROGRAMMING: library IEEE;


use IEEE.STD_LOGIC_1164.ALL;

entity DECODER is
port (
e : in std_logic;
a : in std_logic_vector(1 downto 0);
y : out std_logic_vector(3 downto 0)
);
end entity DECODER;

architecture behaviour of DECODER is


begin
process(e, a)
begin
if e = '1' then
case a is
when "00" =>y<= "0001";
when "01" =>y<= "0010";
when "10" =>y<= "0100";
when "11" =>y<= "1000";
when others =>y<= "0000";
end case;
else
y <= "0000";
end if;
end process;
end architecture behaviour;
RESULTS AND ANALYSIS: Screenshot of waveforms and inference

Name: Ansh Sharma Batch: B3


UICD: 2023200108 Class-S.E.-B
Sardar Patel Institute of Technology
Bhavan’s Campus, Munshi Nagar, Andheri (West), Mumbai-400058-India
(Empowered Autonomous Institute Affiliated to University of Mumbai)
Electronics and Telecommunication Engineering Department
Academic year 2024-2025

Name: Ansh Sharma Batch: B3


UICD: 2023200108 Class-S.E.-B
Sardar Patel Institute of Technology
Bhavan’s Campus, Munshi Nagar, Andheri (West), Mumbai-400058-India
(Empowered Autonomous Institute Affiliated to University of Mumbai)
Electronics and Telecommunication Engineering Department
Academic year 2024-2025

CONLCLUSION:

The VHDL code provided demonstrates a structured approach to implementing a decoder circuit
with an enable high. I learned how to use the when and if function in a VHDL code.

Name: Ansh Sharma Batch: B3


UICD: 2023200108 Class-S.E.-B

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