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CADIC Micro Lesson Plan - Section A, B, C & D

Cmos Analog and digital IC design

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Madhavarao K
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14 views3 pages

CADIC Micro Lesson Plan - Section A, B, C & D

Cmos Analog and digital IC design

Uploaded by

Madhavarao K
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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B.V.

Raju Institute of Technology


(Autonomous)
Vishnupur, Narsapur, Medak (District) – 502313
Department of Electronics and Communication Engineering
Lesson
CMOS Digital and AnalogPlan
L T P C
Course Code: A24B9 IC Design 4 1 - 4
Pre-requisites: DLD & IC applications
Name of the Faculty Dr. K. Madhavarao
Designation Assistant Professor
Department ECE
Academic year 2023-24 Class: III B.Tech I Sem Section: A,B,C & D

The purpose of learning this course is to


Learning 1. Understand MOSFET working characteristics.
Rationale
2. Design Current mirrors using CMOS technology.
3. Design Differential amplifier and various its architectures.
4. Design and Analysis of operational amplifiers.
Learning
Outcomes At the end of this course, learners will be able to:

Po1 Po Po3 Po4 Po5 Po6 Po7 Po8 Po9 Po10 Po11 Po12 Pso1 Pso2
2
Understand MOSFET working 3 2 1
characteristics and current mirrors
design.
Design and analysis of Complex Logic 2 3
circuits design –Realizing Boolean
expressions using NMOS gates and
CMOS gates
Design and analysis of Sequential 2 3 1 2
CMOS Logic Circuits
Design and Analysis of differential and 2 3 1 1
operational amplifiers.
Analyze the High performance of 1 3 1
operational amplifiers
Attainment Target 1.8 3 1.4 2 1

Learning Content & Plan

No. of Teaching aids Text


Unit Title Name of the Topic Date
Periods book
Unit- I
MOS Device Modeling: -MOSFET 1 25-07-2024 Online WB/ --
introduction Introduction
Video
MOSFET
Device Simple MOS small signal Model
Modeling 1 26-07-2024 WB T1

Simple MOS Large-Signal model 2 27-07-2024 WB T1


Analog CMOS Sub-Circuits: 1 01-08-2024 WB --
Current Sinks and Sources 1 02-08-2024 WB T1

Current mirrors 2 03-08-2024 WB T1

Unit Assessment 1 08-08-2024 WB T1

TOTAL 8+1
B.V. Raju Institute of Technology
(Autonomous)
Vishnupur, Narsapur, Medak (District) – 502313
Department of Electronics and Communication Engineering
Lesson
Plan
Learning Content & Plan

Unit- II

MOS Design Pseudo NMOS Logic: 1 09-08-2024 WB T1

Introduction to NMOS logic, Inverter 1 15-08-2024


NMOS
NMOS logic gates 1 16-08-2024 WB T1

MOS Design Pseudo NMOS Logic 2 17-08-2024 WB T1


Pseudo NMOS
Logic:
CMOS Inverter logic, Complex Logic 1 22-08-2024 WB T1
circuits design
Realizing Boolean expressions using 1 23-08-2024 WB T1
NMOS gates and CMOS gates

Introduction to CMOS transmission gates, 2 24-08-2024 WB T1

Designing with Transmission gates 1 29-08-2024 WB T1

1 30-08-2024 Test/ Interactive


Unit Assessment
Session

TOTAL 11+1

Unit- III
Sequential CMOS Logic Circuits: CMOS 2 05-09-2024 WB T1
based SR Latch
Clocked latch and flip flop circuits 1 06-9-2024 WB T1

CMOS D latch 1 07-09-2024 WB T1


Sequential
CMOS Logic edge triggered flip-flop 2 12-09-2024 WB T1
Circuits
1 13-09-2024 Test/ Interactive
Unit Assessment
Session
TOTAL 6+1
B.V. Raju Institute of Technology
(Autonomous)
Vishnupur, Narsapur, Medak (District) – 502313
Department of Electronics and Communication Engineering
Unit-IV
CMOS Amplifiers: Current Amplifiers 1 26-09-2024
Ideal characteristics of differential 1 27-09-2024 WB T1
amplifiers
CMOS Differential amplifiers and 2 28-09-2024 WB T1
CMOS Amplifiers parameters

Cascode Differential amplifier 2 3-10-2024 WB T1


4-10-2024
Output Amplifiers 2 5-10-2024 WB T1
1 10-10-2024 Test/ Interactive
Unit Assessment
Session
TOTAL 9+1 11-10-2024
Reserved Class 2

Unit- V
CMOS Operational CMOS Operational Amplifiers 2 WB T1
Amplifiers
17-10-2024
19-10-2024
Ideal characteristics of CMOS 2 WB
operational amplifiers
7-11-2014 T1

8-11-2024
Design of CMOS Two- stage operational 2 WB
amplifiers
14-11-2024 T1

15-11-2024
CMRR and Power- Supply Rejection 2 WB
Ratio of Two-Stage Op Amps.
16-11-2024 T1

21-11-2022
Unit Assessment 1 22-11-2024 Test/ Interactive
Session
TOTAL 8+1
Reserved Class 2

Learning Resources

Unit Unit Unit Unit Unit


1 2 3 4 5

1 . CMOS Analog Circuit Design -Philip E. Allen and ✓ ✓ ✓ ✓ ✓


Douglas R.Holberg, Oxford University Press,
International Second Edition/Indian Edition,
2010.
2 CMOS Digital Integrated Circuits Analysis and ✓ ✓ ✓ ✓ ✓
Design – Sung-Mo Kang,
Yusuf Leblebici, TMH, 3rd Ed., 2011.

Head of Department
Signature of Faculty

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