CADIC Micro Lesson Plan - Section A, B, C & D
CADIC Micro Lesson Plan - Section A, B, C & D
Po1 Po Po3 Po4 Po5 Po6 Po7 Po8 Po9 Po10 Po11 Po12 Pso1 Pso2
2
Understand MOSFET working 3 2 1
characteristics and current mirrors
design.
Design and analysis of Complex Logic 2 3
circuits design –Realizing Boolean
expressions using NMOS gates and
CMOS gates
Design and analysis of Sequential 2 3 1 2
CMOS Logic Circuits
Design and Analysis of differential and 2 3 1 1
operational amplifiers.
Analyze the High performance of 1 3 1
operational amplifiers
Attainment Target 1.8 3 1.4 2 1
TOTAL 8+1
B.V. Raju Institute of Technology
(Autonomous)
Vishnupur, Narsapur, Medak (District) – 502313
Department of Electronics and Communication Engineering
Lesson
Plan
Learning Content & Plan
Unit- II
TOTAL 11+1
Unit- III
Sequential CMOS Logic Circuits: CMOS 2 05-09-2024 WB T1
based SR Latch
Clocked latch and flip flop circuits 1 06-9-2024 WB T1
Unit- V
CMOS Operational CMOS Operational Amplifiers 2 WB T1
Amplifiers
17-10-2024
19-10-2024
Ideal characteristics of CMOS 2 WB
operational amplifiers
7-11-2014 T1
8-11-2024
Design of CMOS Two- stage operational 2 WB
amplifiers
14-11-2024 T1
15-11-2024
CMRR and Power- Supply Rejection 2 WB
Ratio of Two-Stage Op Amps.
16-11-2024 T1
21-11-2022
Unit Assessment 1 22-11-2024 Test/ Interactive
Session
TOTAL 8+1
Reserved Class 2
Learning Resources
Head of Department
Signature of Faculty