Digital Circuit Design Using Verilog Lab manual

EXPERIMENT NO. 1.a

HALF/FULL ADDER AND HALF/FULL SUBTRACTOR

Aim: - To realize half/full adder and half/full subtractor using logic gates.

Apparatus Required: -

IC Trainer Kit, patch chords, IC 7486, IC 7432, IC 7408, IC 7400, etc.

Procedure: -

1. Verify the gates.

2. Make the connections as per the circuit diagram.

3. Switch on VCC and apply various combinations of input according to the truth table.

4. Note down the output readings for half/full adder and half/full subtractor
sum/difference and the carry/borrow bit for different combinations of inputs.

Half Adder

Logic Diagram Truth Table

Sum Carry
A B
(S) (C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
K-map simplification:

Circuit Diagram
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USING BASIC AND XOR GATES

Full Adder

Logic Diagram Truth table

Sum Carry
A B Ci
(S) (Co)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
K-map Simplification:

Sum = AB’C’+A’B’C+A’BC’+ABC Carry = Acin + Bcin +AB

Circuit Diagram+ C(A’B’+AB)

= C’(AB’+A’B)
USING BASIC AND XOR GATES
= C’(AB) + C(AB)’

= C  (AB)

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Half Subtractor :

Logic Diagram Truth Table

A B Diff (D) Borrow (B0)

0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Circuit Diagram
USING BASIC AND XOR GATES

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Full subtractor:

7486 DIFF(D)

A
B 7486 7404
7408
Cin

7404 7432 BORROW (B)

7408

Circuit Diagram
(USING BASIC AND XOR GATES)

Logic Diagram: Truth Table

Result:

EXPERIMENT NO. 1.b

Develop and verify the Verilog code for the given Boolean expressions and Half /
full adder using different types of modeling

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module logic_gate (a,b,c,d,e,f,g,h,i);

input a,b;
output c,d,e,f,g,h,i;
assign c= a&b;
assign d= a|b; AIM: Write a Verilog
assign e= ~ a; code for Logic gates,
assign f= a^b;
simulate it using
assign g= ~(a&b);
modelsim simulator
assign h= ~(a|b);
assign f= ~(a^b);
and implement it on
end module FPGA kit.

LOGIC c
GATES
d

f Logic Symbol
a b c(and) d(or e(not) f(nand ) g(nor) h(xor) i(xnor)
for Logic
) g gates
0 0 0 0 1 1 h1 0 1 TRUTH
TABLE:
0 1 0 1 1 1 i 0 1 0

1 0 0 1 0 1 0 1 0

1 1 1 1 0 0 0 0 1

Boolean Expressions:

c= ab
d= a+b
e= a̅
f= ab
g= a+b
h= aƟb
i= aƟb

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TRUTH TABLE: Logic Circuit for Half Adder:

a b sum(s) carry(c)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Boolean Expressions:

s= aƟb
c= ab

Dataflow modeling: Behavioral modeling:

module half_adder(a,b,s,c);
module half_adder (a,b,s,c); input a,b ;
input a,b; output s,c;
output s,c; reg s,c;
assign s= a^b; always @(a,b)
assign c= a&b; begin
endmodule if (a==0 & b==0)
begin
s=0; c=0;
end
Structural modeling: else
if (a==0 & b==1)
module half_adder(a,b,s,c); begin
input a,b; s=1; c=0;
output s,c; end
xor u1(s,a,b); else
and u2(c,a,b); if (a==1 & b==0)
endmodule begin

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s=1; c=0;
end
else
if (a==1 & b==1)
begin
s=0; c=1;
end
end
endmodule

TRUTH TABLE: Logic Circuit for Full Adder:

a b cin sum(s) carry(co)

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Boolean Expressions: s=aƟbƟcin
co=ab+bcin+cina

Dataflow modeling: Behavioral modeling:

module full_adder(a,b,cin, s,co); module end
input a,b,cin; full_adder(a,b,cin,s,c); else
output s,co; input a,b,cin ; if (a==1 & b==0 & cin==0)
assign s = a^b^cin; output s,c; begin
assign c = (a&b) | (b&cin | (cin&a); reg s,c; s=1; c=0;
endmodule always @(a,b,cin) end
begin else
if (a==0 & b==0 & cin==0) if (a==1 & b==0 & cin==1)
begin begin
s=0; c=0; s=0; c=1;
end end
else else
if (a==0 & b==0 & cin==1) if (a==1 & b==1 & cin==0)
begin begin
s=1; c=0; s=0; c=1;
end end
else else
if (a==0 & b==1 & cin==0) if (a==1 & b==1 & cin==1)
begin begin
s=1; c=0; s=1; c=1;
end end
else end

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if (a==0 & b==1 & cin==1) endmodule

begin
s=0; c=1

EXPERIMENT NO. 2.a:

PARALLEL ADDER/SUBTRACTOR and HALF/FULL SUBTRACTOR USING MUX IC 74153

AIM: - To realize IC 7483 as parallel adder / Subtractor and realize half/full subtractor using mux
IC 74153

Apparatus Required: -

IC Trainer Kit, patch chords, IC 7483, IC 7404,74153 etc.

Procedure: -

1. Apply the inputs to A0 to A3 and B0 to B3.

2. Connect C0 to the Ground.

3. Check the output sum on the S0 to S3 and also C4.

4. For subtraction connect C0 to Vcc, Apply the B input through NOT gate, which gives the
complement of B.

5. The truth table of adder and Subtractor are noted down.

Pin Detail: -

7483

Adder: -

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Truth Table: -

A3 A2 A1 A0 B3 B2 B1 B0 C4 (V) S3(V) S2(V) S1(V) S0(V)

0 0 0 1 0 0 1 0 0 0 0 1 1
0 1 0 1 1 0 1 1 1 0 0 0 0
1 0 1 0 1 0 1 0 1 0 1 0 0
1 1 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 0 0 1 1 0 1 0 1 0

Subtractor:-

Truth Table for Subtractor

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A3 A2 A1 A0 B3 B2 B1 B0 C4(V) S3(V) S2(V) S1(V) S0(V)

0 0 1 0 0 0 0 1 1 0 0 0 1
0 1 0 1 0 0 1 1 1 0 0 1 0
0 0 1 1 0 1 0 1 0 1 1 1 0
1 0 1 0 0 1 1 0 1 0 1 0 0
1 0 0 0 1 1 1 1 0 1 0 0 1

Procedure for MUX:

1. The Pin [16] is connected to + Vcc.
2. Pin [8] is connected to ground.
3. The inputs are applied either to ‘A’ input or ‘B’ input.
4. If MUX ‘A’ has to be initialized, Ea is made low and if MUX ‘B’ has to be initialized, Eb
is made low.
5. Based on the selection lines one of the inputs will be selected at the output and thus
the truth table is verified.
6. In case of half adder using MUX, sum and carry is obtained by applying a constant
inputs at I0a, I1a, I 2a, I 3a and I 0b, I 1b, I 2b and I3b and the corresponding values of select
lines are changed as per table and the output is taken at Z0a as sum and Z0b as
carry.
7. In this case, the channels A and B are kept at constant inputs according to the table
and the inputs A and B are varied. Making Ea and Eb zero and the output is taken at
Za, and Zb.
8. In full adder using MUX, the input is applied at Cn-1, An and Bn. According to the
table corresponding outputs are taken at Cn and Dn.

Pin Details: -

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SELECT INPUTS
SELECT INPUTS
LINES
LINES
S1 S2 Ēa Ioa I1a I2a I3a Za
S1 S2 Ēb Iob I1b I2b I3b Zb
X X 1 X X X X 0
X X 1 X X X X 0
0 0 0 0 X X X 0
0 0 0 0 X X X 0
0 0 0 1 X X X 1
0 0 0 1 X X X 1
0 1 0 X 0 X X 0
0 1 0 X 0 X X 0
0 1 0 X 1 X X 1
0 1 0 X 1 X X 1
1 0 0 X X 0 X 0
1 0 0 X X 0 X 0
1 0 0 X X 1 X 1 Truth Table:
- 1 0 0 X X 1 X 1
1 1 0 X X X 0 0
1 1 0 X X X 0 0
1 1 0 X X X 1 1
1 1 0 X X X 1 1

Half Subtractor Using MUX IC 74153

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Full subtractror Half subtractor

An Bn Cn- Dn Bn A B Dn Bn (V)
1 (V) (V) (V)
0 0 0 0 0 0 0 0 0
0 0 1 1 1 0 1 1 1
0 1 0 1 1 1 0 1 0
0 1 1 0 1 1 1 0 0
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Full Subtractor Using 74153

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Experiment No.: 2.b

Develop the Verilog code for the following combinational circuits in gate level/data flow any
type of modelling. – MUX, DEMUX, encoder, decoder.

TRUTH TABLE:

Select Lines(I/P) Output

S(1) S(0) f
0 0 d(0)
0 1 d(1)
1 0 d(2)
1 1 d(3)

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module mux4_1 (s,d,f);

output f;
input [1:0] s;
input [3:0] d;
reg [3:0] d;
always @(d,s)
begin
case (s )
2’d0: f = d[0];
2’d1: f = d[1];
2’d2: f = d[2];
2’d3: f = d[3];
endcase
end
endmodule

Module mux 4_1(i,s,y);

Input [3:0]i;
Input[3:0]s;
Output y;
Wire p1,p2,p3,p4,p5,p6;
Notu1 (p1,,s[0]);
Not u2 (p2, s[1]);
And u3 (p3, p1, p2, i[0]);
And u4 (p4, p2, s[0], i[1]);
And u5 (p5, p1, s[1], i[2]);
And u6 (p6, s[1], s[0], i[3]);
Or u7(y, p3, p4, p5, p6);
End module

TRUTH TABLE:

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Select Lines (I/P) Output

S(1) S(0) d(3) d(2) d(1) d(0)
0 0 X X X f
0 1 X X f X
1 0 X f X X
1 1 f X X X

module demux1_4 (s,d,f);

input f;
input [1:0] s;
output [3:0] d;
reg [3:0] d;
always @(f,s)
begin
case (s )
2’d0:d[0]=f;
2’d1: d[1]=f;
2’d2: d[2]=f;
2’d3:d[3]=f;
End case
end
end module

TRUTH TABLE:

Inputs Outputs
s(7) s(6) s(5) s(4) s(3) s(2) s(1) s(0) y(2) y(1) y(0)
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0

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0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

module pri_encod(y, s);

input [7:0] s;
output [2:0] y;
reg [2:0] y;
always @(s)
begin
case (s)
8'b00000001:y=3'd0;
8'b00000010:y=3'd1;
8'b00000100:y=3'd2;
8'b00001000:y=3'd3;
8'b00010000:y=3'd4;
8'b00100000:y=3'd5;
8'b01000000:y=3'd6;
8’b10000000:y=3'd7;
endcase
end
endmodule

TRUTH TABLE:

Inputs Outputs
s(1) s(0) y(3) y(2) y(1) y(0)
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

Boolean Expressions:
y[0]= s[1]s[0]
y[1]= s[1]s[0]
y[2]= s[1]s[0]
y[3]= s[1]s[0]

module decoder2_4(s,y);
input [1:0] s;
output [3:0] y;
assign y[0]=(~s[1]) & (~s[0]);
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assign y[1]=(~s[1]) & s[0];

assign y[2]=s[1] & (~s[0]);
assign y[3]=s[1] & s[0];
endmodule
Experiment No.: 3.a

FLIP-FLOPS

Aim: Verification of truth-tables of the following types of SR flip flop and master slave JK flip-flops
using NAND gates

Apparatus Required: -
IC 7410, IC 7400, etc.

Procedure: -
1. Connections are made as per circuit diagram.
2. The truth table is verified for various combinations of inputs.

SR Flip-flop: Truth-table:

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Circuit Diagram: - (Master Slave JK Flip-Flop)

PR
J 7410 7410
7400
7400 Q

7400 Q’
7400
K 7410 7410
clr

7410

Truth Table:- (Master Slave JK Flip-Flop)

Preset Clear J K Clock Qn+1

0 1 X X X 1 0 Set
1 0 X X X 0 1 Reset
No
1 1 0 0 Qn
Change
1 1 0 1 0 1 Reset
1 1 1 0 1 0 Set
1 1 1 1 Qn Toggle

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Experiment No.: 3.b

Develop and verify Verilog code using behavioural modelling for sequential circuits- flip-flops .

AIM: Write a Verilog code for D Flip Flop in Behavioral modeling, simulate it using modelsim simulator.
Clear

D FLIP-FLOP
D Q

Clk
Qb

Preset

Logic Symbol for D Flip-Flop

TRUTH TABLE:-

Clk Clear Preset D Q Qb

Π 0 1 X 0 1
Π 1 0 X 1 0
Π 1 1 0 0 1
Π 1 1 1 1 0

module dff(d, preset,clear,clk, q,qb);

input d;
input clk,preset,clear;
output q,qb;
reg q,qb;

always@(posedge clk)
begin
if(clear==0)
begin
q=0;qb=1;
end
else
if(preset==0)
begin
q=1;qb=0;
end
else

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begin
case(d)
1'b0:begin q=0;qb=1; end
1'b1:begin q=1;qb=0;end
endcase
end
end
endmodule

AIM: Write a Verilog code for JK Flip Flop in Behavioral modeling, simulate it using modelsim
simulator
Clear

J K FLIP-FLOP
J Q

Clk
Qb

K Preset

Logic Symbol for JK Flip-Flop

TRUTH TABLE:-

Clk Clear Preset J K Q Qb

Π 0 1 X X 0 1
Π 1 0 X X 1 0
Π 1 1 0 0 Q Qb
Π 1 1 0 1 0 1
Π 1 1 1 0 1 0
Π 1 1 1 1 Q Qb

JK Flip Flop

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module jkff(jk, preset,clear,clk, q,qb); always@(posedge clkd)

input [1:0] jk; begin
input clk,preset,clear; if(clear==0)
output q,qb; begin
reg q,qb; q=0;qb=1;
wire clkd; end
reg [20:0] COUNT; else
initial COUNT=0; if(preset==0)
assign clkd=COUNT[20]; begin
always @(posedge clk) q=1;qb=0;
begin end
COUNT = COUNT + 1; else
end begin
case(jk)
2'b00:begin q=q;qb=qb; end
2'b01:begin q=0;qb=1;end
2'b10:begin q=1;qb=0;end
2'b11:begin q=~q;qb=~qb;end
endcase
end
end
endmodule

Experiment No.: 4.a

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ASYNCHRONOUS COUNTERS

Aim: Realization of 3-bit asynchronous up/down counters

Apparatus Required: -IC 7476

Procedure: -

1. Connections are made as per circuit diagram.

2. Clock pulses are applied one by one at the clock I/P and the O/P is observed at QA, QB &
QC for IC 7476.

3. Truth table is verified.

Circuit Diagram: - 3-Bit Asynchronous Up Counter

Truth-table:

3-bit Asynchronous up counter

Clock QC QB QA
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
9 0 0 1

Circuit Diagram: - 3-Bit Asynchronous Down Counter

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Truth-table:

3-bit Asynchronous down counter

Clock QC QB QA
0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
8 1 1 1
9 1 1 0

EXEPRIMENT 4.B
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Develop and verify the Verilog code for 3 bit binary up/down counter

AIM: Write a Verilog code for Asynchronous binary 4-bit up counter in Behavioral modeling, simulate it
using modelsim simulator.

BINARY
rst q[3:0]
COUNTER

clk

Logic Symbol for Binary Counter

TRUTH TABLE :

Inputs Outputs
rst Clk q(3) q(2) q(1) q(0)
1 X 0 0 0 0
0 Π 0 0 0 0
0 Π 0 0 0 1
0 Π 0 0 1 0
0 Π 0 0 1 1
0 Π 0 1 0 0
0 Π 0 1 0 1
0 Π 0 1 1 0
0 Π 0 1 1 1
0 Π 1 0 0 0
0 Π 1 0 0 1
0 Π 1 0 1 0
0 Π 1 0 1 1
0 Π 1 1 0 0
0 Π 1 1 0 1
0 Π 1 1 1 0
0 Π 1 1 1 1

Binary Up Counter

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module binarycounter(clk,rst,q); always@(posedge clkd)

input clk,rst; begin
output [3:0] q; if(rst==1)
reg [3:0] q; begin
reg [22:0] COUNT; q=4'b0000; /*FOR ASYNCRONOUS DOWN
wire clkd; COUNTER CHANGE q=4'b1111*/
initial COUNT=0; end
assign clkd=COUNT[22]; else
always @(posedge clk) begin
begin q=q+1; /*FOR ASYNCRONOUS DOWN
COUNT = COUNT + 1; COUNTER CHANGE q=q-1*/
End end
end
endmodule

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Experiment No.: 5.a

DECODER

AIM:-To drive the LED display using 7447 7-segment decoder/ driver.

APPARATUS REQUIRED: -

IC 7447, 7-segment display, etc.

PROCEDURE: -

1. Connections are made as per the circuit diagram.

2. Connect the pins of IC 7447 to the respective pins of the LED display board.

3. Give different combinations of the inputs and observe the decimal numbers displayed on the board.

BCD TO SEVEN SEGMENT DECODER CIRCUIT DIAGRAM WITH LED DISPLAY

NC

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TRUTH-TABLE:

INPUTS LED SEVEN SEGMENTS LEVEL

DECIMAL
DISPLAY
DIGIT D C B A a’ b’ c’ d’ e’ f’ g’
VALUE
0 0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 1 0 1 1 0 0 0 0
2 0 0 1 0 2 1 1 0 1 1 0 1
3 0 0 1 1 3 1 1 1 1 0 0 1
4 0 1 0 0 4 0 1 1 0 0 1 1
5 0 1 0 1 5 1 0 1 1 0 1 1
6 0 1 1 0 6 0 0 1 1 1 1 1
7 0 1 1 1 7 1 1 1 0 0 0 0
8 1 0 0 0 8 1 1 1 1 1 1 1
9 1 0 0 1 9 1 1 1 0 0 1 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
No seg.
15 1 1 1 1
glows

Result:

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Experiment No.: 5.b

Develop the Verilog code for comparator (n-bit), and BCD counter.

AIM: Write a Verilog code for N-bit comparator in behavioral modeling, simulate it using modelsim
simulator.

a[n:0] N-BIT y(0)

COMPARATOR y(1)
b[n:0]
y(2)

Logic Symbol for N-bit Comparator

TRUTH TABLE:
INPUT OUTPUT (Y)
a>b 100
a=b 010
a<b 001

module comp_n(a,b,y);
parameter n=3;
input [n:0] a,b;
output [2:0] y;
reg [2:0] y;

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always @ (a,b)
begin
if(a==b)
y=3’b010;
else
if(a<b)
y=3’b001;
else
if(a>b)
y=3’b100;
end
endmodule

AIM: Write a Verilog code for Asynchronous BCD 4-bit up counter in Behavioral modeling, simulate it
using modelsim simulator.

Logic Symbol for BCD Counter

TRUTHTABLE :

Inputs Outputs
rst Clk q(3) q(2) q(1) q(0)
1 X 0 0 0 0
0 Π 0 0 0 0
0 Π 0 0 0 1
0 Π 0 0 1 0
0 Π 0 0 1 1
0 Π 0 1 0 0
0 Π 0 1 0 1
0 Π 0 1 1 0
0 Π 0 1 1 1
0 Π 1 0 0 0
0 Π 1 0 0 1

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BCD Up Counter

module BCDcounter(clk,rst,q); always@(posedge clkd)

input clk,rst; begin
output [3:0] q; if(rst==1 | q==4’b1001) /*FOR ASYNCRONOUS
reg [3:0] q; DOWN COUNTER CHANGE q=4'b1111*/
reg [22:0] COUNT; begin
wire clkd; q=4'b0000; /*FOR ASYNCRONOUS DOWN
initial COUNT=0; COUNTER CHANGE q=4'b1001*/
assign clkd=COUNT[22]; end
always @(posedge clk) else
begin begin
COUNT = COUNT + 1; q=q+1; /*FOR ASYNCRONOUS DOWN
end COUNTER CHANGE q=q-1*/
end
end
endmodule

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