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CE 213: DIGITAL LOGIC AND DESIGN
Assignment -3 Combinational Circuits
Issue Date: Wednesday, 17 April 2024
Submission Deadline: Monday, 22 April 2024
Dept. of Computer Engineering
King Faisal University Al Ahsa 31982, Saudi Arabia. April 17, 2024 Dr. Al-Amin Bhuiyan [email protected] Page 1 of 2 CE 213: DIGITAL LOGIC AND DESIGN
1. Design an 8:1 multiplexer.
2. Design a 4:1 Demultiplexer 3. Implement the function Y ( A, B, C ) AB BC AC using (i) MUX and (ii) DEMUX. 4. Implement the following functions with multiplexers F1 (A, B, C) =∑m (1, 3, 6, 7) F2 (A, B, C) =∑m (0, 3, 4, 5) 5. Implement a full adder using (i) MUXs and (ii) DEMUXs. 6. Implement the following Boolean function using a MUX F(A, B, C, D)=∑m(0, 1, 3, 4, 8, 9, 15) 7. Construct a full adder using a 3 to 8 decoder.