EXPT. NO.

: 1
DATE :

IMPLEMENTATION OF BOOLEAN FUNCTION ,ADDER ,SUBTRACTOR

AIM:

To realize the various logic gates and their verify their outputs

APPARATUS REQUIRED:

SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1

2. OR GATE IC 7432 1

3. NOT GATE IC 7404 1

4. NAND GATE 2 I/P IC 7400 1

5. NOR GATE IC 7402 1

6. X-OR GATE IC 7486 1

7. NAND GATE 3 I/P IC 7410 1

8. IC TRAINER KIT - 1

As per
9. PATCH CORD -
Required

THEORY:

Circuit that takes the logical decision and the process are called logic gates. Each gate
has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal
gates. Basic gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as AND function.
The output is high when both the inputs are high. The output is low level when any one of the
inputs is low.

OR GATE:

The OR gate performs a logical addition commonly known as OR function. The

output is high when any one of the inputs is high. The output is low level when both the inputs
are low.

NOT GATE:

The NOT gate is called an inverter. The output is high when the input is low. The
output is low when the input is high.

NAND GATE:

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are
low and any one of the input is low .The output is low level when both inputs are high.

NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are
low. The output is low when one or both inputs are high.
X-OR GATE:

The output is high when any one of the inputs is high. The output is low when both the
inputs are low and both the inputs are high.

AND GATE:

SYMBOL:

PIN DIAGRAM:

OR GATE:
NOT GATE:

SYMBOL:

X-OR GATE :

SYMBOL :

2-INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

2-INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE :

NOR GATE:
PROCEDURE:

(i)Connections are given as per circuit diagram.

(i) Logical inputs are given as per circuit diagram.

(iii)Observe the output and verify the truth table.

RESULT:
EXPT. NO. : 1b
DATE :
VERIFICATION OF BOOLEAN THEOREMS
USING DIGITAL LOGIC GATES

AIM:

To verify the Boolean Theorems using logic gates.

APPARATUS REQUIRED:

SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1

2. OR GATE IC 7432 1

3. NOT GATE IC 7404 1

4. IC TRAINER KIT - 1

CONNECTING As per
5. WIRES -
Required

BOOLEAN THEOREM:

Theorem : 1. x + x = x ; x.x=x
2. x + 1 = 1 ; x.0=0
3. (x’)’ = x ( Involution )
4. Associative x + (y + z) = (x + y) + z

x . (y . z) = (x . y) . z
5. De Morgan’s (x + y)’ = x’ . y’
 (x . y)’ = x’ + y’
6. Absorption x + x.y = x
x . (x + y) = x
CIRCUIT DIAGRAM:

THEOREM : 1

THEOREM: 2

Truth Table:

1 Y=X+1=
X 1
0 1 1
1 1 1

X
0 Y=X.0=0
0 0 0
1 0 0
THEOREM: 3 (INVOLUTION THEOREM)

Truth Table:
(2) (X.Y).Z =X.(Y.Z) Truth Table:

THEOREM: 5 DE-MORGAN’S LAW:

Truth Table:
THEOREM: 6 (ABSORPTION)

PROCED
URE:
1. The connections are made as per the circuit diagram.
2. Give the logical inputs as per the truth table.
3. The corresponding output is verified with their truth table.

RESULT:
EXPT. NO. :2
DATE :

DESIGN OF ADDER AND SUBTRACTOR

AIM:

To design and construct half adder, full adder, half subtractor and full subtractor circuits
and verify the truth table using logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1 AND GATE IC 7408 1
2 X-OR GATE IC 7486 1
3 NOT GATE IC 7404 1
4 OR GATE IC 7432 1
5 IC TRAINER KIT - 1
As per
6 PATCH CORD - required

THEORY:

HALF ADDER:

A half adder has two inputs for the two bits to be added and two outputs one from the
sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is called as
a carry signal from the addition of the less significant bits sum from the X-OR Gate the carry
out from the AND gate.
FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of input; it consists
of three inputs and two outputs. A full adder is useful to add three bits at a time but a half
adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will
be taken from OR Gate.
HALF SUBTRACTOR:

The half subtractor is constructed using X-OR and AND Gate. The half subtractor has

two input and two outputs. The outputs are difference and borrow. The difference can be

applied using X-OR Gate, borrow output can be implemented using an AND Gate and an

inverter.

FULL SUBTRACTOR:

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full

subtractor the logic circuit should have three inputs and two outputs. The two half subtractor

put together gives a full subtractor .The first half subtractor will be C and A B. The output will

be difference

output of full subtractor. The expression AB assembles the borrow output of the half
subtractor and the second term is the inverted difference output of first X-OR.

LOGIC DIAGRAM:

HALF ADDER
 A B CARRY SUM
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

LOGIC DIAGRAM:

FULL ADDER USING TWO HALF ADDER:

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY:

CARRY = AB + BC + AC

LOGIC DIAGRAM:

HALF SUBTRACTOR

TRUTH TABLE:
A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

K-Map for DIFFERENCE:

DIFFERENCE = A’B + AB’

K-Map for BORROW:

BORROW = A’B

LOGIC DIAGRAM:

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

TRUTH TABLE:

A B C BORROW DIFFERENCE

0 0 0 0 0
 0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference:

DIFFERENCE = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for Borrow:

BORROW = A’B + BC + A’C

PROCEDURE:

(i) Connections are given as per circuit diagram.

 (ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

EXPT. NO. : 3
DATE :
DESIGN AND IMPLEMENTATION OF CODE CONVERTER
AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.

1. X-OR GATE IC 7486 1

2. AND GATE IC 7408 1
3. OR GATE IC 7432 1

4. NOT GATE IC 7404 1

5. IC TRAINER KIT - 1

As per
6. PATCH CORDS -
Required

THEORY:

The availability of large variety of codes for the same discrete elements of information

results in the use of different codes by different systems. A conversion circuit must be inserted

between the two systems if each uses different codes for same information. Thus, code

converter is a circuit that makes the two systems compatible even though each uses different

binary code.

The bit combination assigned to binary code to gray code. Since each code uses four bits
to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-
weighted code.
 The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.
A code converter is a circuit that makes the two systems compatible even though each
uses a different binary code. To convert from binary code to Excess-3 code, the input lines
must supply the bit combination of elements as specified by code and the output lines generate
the corresponding bit combination of code. Each one of the four maps represents one of the
four outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that implements
this circuit. Now the OR gate whose output is C+D has been used to implement partially each
of three outputs.

LOGIC DIAGRAM:

BINARY TO GRAY CODE CONVERTOR

TRUTH TABLE:
| Binary input | Gray code output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-Map for G3:

 G3 = B 3
K-Map for G2:

K-Map for G1:

K-Map for G0:

LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR
TRUTH TABLE:

| Gray Code | Binary Code |

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

K-Map for B3:

B3 = G3
K-Map for B2:

K-Map for B1:

K-Map for B0:

LOGIC DIAGRAM:
BCD TO EXCESS-3 CONVERTOR
TRUTH TABLE:

| BCD input | Excess – 3 output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

K-Map for E3:

E3 = B3 + B2 (B0 + B1)
K-Map for E2:

K-Map for E1:

K-Map for E0:

LOGIC DIAGRAM:

EXCESS-3 TO BCD CONVERTOR

TRUTH TABLE:

| Excess – 3 Input | BCD Output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

K-Map for A:

A = X1 X2 + X3 X4 X1
K-Map for B:

K-Map for C:
K-Map for D:

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

RESULT:
EXPT NO:4
DATE:
DESIGN AND IMPLEMENTATION OF 4 BIT ADDER AND SUBTACTER

AIM:
To design and implement 4-bitadderandsubtractor usingIC7483.

APPARATUSREQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. IC IC7483 1
2. EX-ORGATE IC7486 1
3. NOTGATE IC7404 1
3. ICTRAINERKIT - 1
4. PATCHCORDS - 40

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two
binary numbers. It can be constructed with full adders connected in cascade, with
theoutput carry from eachfull adder connectedtotheinput carry of next full adder in
chain. The augends bits of ‘A’ and the addend bits of ‘B’ are designated by
subscript numbers from right to left, with subscript 0 denoting the least significant
bits. The carries are connected in chain through the full adder. The input carry to
the adder is C0 and it ripples through the full adder to the output carry C4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed
between each data input ‘B’ and the corresponding input of full adder. The input
carry C0 must be equal to 1 when performing subtraction.
4 BIT BINARYADDER/SUBTRACTOR:

4 BIT BCD ADDER:

Consider the arithmetic addition of two decimal digits in BCD, together

with an input carry from a previous stage. Since each input digit does not exceed 9,
the output sum cannot be greater than 19, the 1 in the sum being an input carry.
The output of two decimal digits must be represented in BCD and should appear in
the form listed in the columns.
ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2
decimal digits,togetherwiththeinputcarry,arefirst addedinthetop4bitadderto produce
the binary sum.

PINDIAGRAMFORIC 7483:
LOGICDIAGRAM:
2- BITBINARY ADDER

LOGICDIAGRAM:
4-BITBINARY SUBTRACTOR
LOGICDIAGRAM:
4-BITBINARY ADDER/SUBTRACTOR
TRUTHTABLE :

InputDataA InputDataB Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
LOGICDIAGRAM:
BCDADDER

K-Map

Y= S4(S3 + S2)
TRUTH TABLE:

BCDSUM CARRY

S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

RESULT:

The 4-bit adder and subtractor are designed and implement usingIC7483.
EXPT NO:5
DATE: DESIGN OF RIPPLE COUNTERS

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JKFLIPFLOP IC7476 2
2. NAND GATE IC7400 1
3. ICTRAINERKIT - 1
4. PATCHCORDS - 30

THEORY:

A counter is a register capable of counting number of clock pulse arriving at

its clock input. Counter represents the number of clock pulses arrived. A specified
sequence of states appears as counter output. This is the main difference between a
register and a counter. There are two types of counter, synchronous and
asynchronous. In synchronous common clock is given to all flip flop and in
asynchronous first flip flop is clocked by external pulse and then each successive
flip flop is clocked by Q or Q output of previous stage. A soon the clock of second
stage is triggered by output of first stage. Because of inherent propagation delay
time all flip flops are not activated at same time which results in asynchronous
operation.
PIN DIAGRAM FOR IC 7476:
LOGIC DIAGRAM FOR 4 BIT RIPPLES COUNTER:

TRUTH TABLE:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1
13 1 0 1 1
14 0 1 1 1
15 1 1 1 1
LOGIC DIAGRAM FOR MOD-10 RIPPLE COUNTER:

TRUTH TABLE:

CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0
LOGIC DIAGRAM FOR MOD-12 RIPPLE COUNTER:

TRUTH TABLE:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 0 0
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table

RESULT:

Thus the 4 bit ripple counter and mod10/mod12ripple counters were

designed and verified.
 EXPT NO:6
DATE:
DESIGN AND IMPLEMENTATION OF3BIT SYNCHRONOUS
UP/DOWN COUNTER

AIM:
To design and implement 3bit synchronous up/down counter.

APPARATUSREQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JKFLIPFLOP IC7476 2
2. 3I/PANDGATE IC7411 1
3. ORGATE IC7432 1
4. XORGATE IC7486 1
5. NOTGATE IC7404 1
6. ICTRAINERKIT - 1
7. PATCHCORDS - 35

THEORY:

A counter is a register capable of counting number of clock pulse arriving at

its clock input.Counter represents thenumber ofclock pulses arrived. An up/down
counteris onethatiscapable ofprogressing inincreasing orderordecreasing order
through a certain sequence. An up/down counter is also called bidirectional
counter. Usually up/downoperation ofthecounter is controlled by up/down signal.
When this signal is high counter goes through up sequence and when up/down
signal is low counter follows reverse sequence.
K MAP
STATE DIAGRAM:
CHARACTERISTICSTABLE:
Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

TRUTH TABLE:
Input PresentState NextState A B C
Up/Down QA QB QC QA+1QB+1QC+1 JA KA JB KB JC KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
LOGICDIAGRAM:

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus the design and implementation of 3bit synchronous up/downcounter

were done.
EXPT NO :7
DATE :
DESIGN AND IMPLEMENTATION OF SHIFT REGISTER

AIM:
To design and implement
(i) Serial in series out
(ii) Serial in parallel out
(iii) Parallel in series out
(iv) Parallel in parallel out

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. DFLIPFLOP IC7474 2

2. ORGATE IC7432 1

3. ICTRAINERKIT - 1

4. PATCHCORDS - 35
THEORY:

A register is capable of shifting its binary information in one or both

directions is known as shift register. The logical configuration of shift register
consist of a D-Flip flop cascaded with output of one flip flop connected to input of
next flip flop. All flip flops receive common clock pulses which causes the shift in
theoutputoftheflipflop.The simplest possible shift register is one that uses only flip
flop. The output of a given flip flop is connected to the input of next flip flop of the
register. Each clock pulse shifts the content of register one bit position to right.

PIN DIAGRAM:
 LOGIC DIAGRAM:

SERIAL IN SERIAL OUT:

TRUTH TABLE:
Serial in Serial out
CLK
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1
SERIAL IN PARALLEL OUT:

TRUTH TABLE:
OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:
TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
2 0 0 0 0 0
3 0 0 0 0 1
1 0 0 0 0 0

LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:

TRUTH TABLE:
DATA INPUT OUTPUT
CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus the design and implementation of shift register were done.

EXPT. NO. :8
DATE :

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND

DEMULTIPLEXER

AIM:
To design and implement multiplexer and demultiplexer using logic gates
APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. IC TRAINER KIT - 1
As per
5. PATCH CORD -
Required

THEORY:

MULTIPLEXER:

Multiplexer means transmitting a large number of information units over a smaller

number of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of
a particular input line is controlled by a set of selection lines. Normally there are 2 n input line
and n selection lines whose bit combination determine which input is selected.

DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this reason,
the demultiplexer is also known as a data distributor. Decoder can also be used as
demultiplexer.
 In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The

data select lines enable only one gate at a time and the data on the data input line will pass

through the selected gate to the associated data output line.

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUTS Y

0 0 D0 → D0 S1’ S0’

0 1 D1 → D1 S1’ S0

1 0 D2 → D2 S1 S0’

1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

LOGIC DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:

S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3
BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

LOGIC DIAGRAM FOR DEMULTIPLEXER:

TRUTH TABLE:

INPUT OUTPUT

S1 S0 I/P D0 D1 D2 D3

0 0 0 0 0 0 0

0 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 1 0 1 0 0
 1 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 0

1 1 1 0 0 0 1

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
EXPT NO :9
DATE: DESIGN AND IMPLEMENTATION OF ENCODER AND
DECODER
AIM:
To design and implement encoder and decoder using logic gates and study of IC 7445
and IC 74147.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P NAND GATE IC 7410 2
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 27

THEORY:
ENCODER:
An encoder is a digital circuit that perform inverse operation of a decoder. An encoder
has 2n input lines and n output lines. In encoder the output lines generates the binary code
corresponding to the input value. In octal to binary encoder it has eight inputs, one for each
octal digit and three output that generate the corresponding binary code. In encoder it is
assumed that only one input has a value of one at any given time otherwise the circuit is
meaningless. It has an ambiguila that when all inputs are zero the outputs are zero. The zero
outputs can also be generated when D0 = 1.

DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input
into coded output where input and output codes are different. The input code generally has
fewer bits than the output code. Each input code word produces a different output code word
i.e there is one to one mapping can be expressed in truth table. In the block diagram of decoder
circuit the encoded information is present as n input producing 2 n possible outputs. 2n output
values are from 0 through out 2n – 1.
PIN DIAGRAM FOR IC 7445:

BCD TO DECIMAL DECODER:

PIN DIAGRAM FOR IC 74147:

LOGIC DIAGRAM OF ENCODER:

TRUTH TABLE:
INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1

LOGIC DIAGRAM FOR DECODER:

TRUTH TABLE:

INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

PROCEDURE:
 (i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

EXPT. NO. :9
DATE :
 SIMULATION OF ADDER AND SUBTRACTOR

AIM:

To design and construct half adder, full adder, half subtractor and full subtractor circuits
and verify the truth table using PSpice.

SCHEMATIC DIAGRAM:

S = A xor B i.e. (A’B + AB’)

C = A and B i.e. (A.B)

WAVEFORM:
SCHEMATIC DIAGRAM(FULL ADDER):

S = A xor B xor C

C = A.B +C(A xor B)

WAVEFORM:
SCHEMATIC DIAGRAM(HALF SUBTRACTOR)

D = A xor B i.e.

(A’B + AB’)

B =A’B

WAVEFORM:
SCHEMATIC DIAGRAM (FULL SUBTRACTOR)

WAVEFORM

RESULT: