LM5158, LM51581

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LM5158x 2.2-MHz Wide VIN 85-V Output Boost/SEPIC/Flyback Converter with Dual
Random Spread Spectrum
• Industrial PLC
1 Features • Inverter bias supply
• Suited for wide operating range for battery • Piezo driver/motor driver bias supply
applications
3 Description
– 3.2-V to 60-V input operating range (65-V abs
max) The LM5158x device is a wide input range, non-
– 83-V maximum output (85-V abs max) synchronous boost converter with an integrated 85-V,
– Minimum boost supply voltage of 1.5 V when 3.26-A (LM5158) or 85-V, 1.63-A (LM51581) power
BIAS ≥ 3.2 V switch.
– Input transient protection up to 65 V The device can be used in boost, SEPIC, and flyback
– Minimized battery drain topologies. It can start up from a single-cell battery
• Low shutdown current (IQ ≤ 2.6 µA) with a minimum of 3.2 V. It can operate with the input
• Low operating current (IQ ≤ 670 µA) supply voltage as low as 1.5 V if the BIAS pin is
• Small solution size and low cost greater than 3.2 V.
– Maximum switching frequency up to 2.2 MHz
– 16-pin QFN package (3 mm × 3 mm) The BIAS pin operates up to 60 V (65-V absolute
– Integrated error amplifier allows primary-side maximum). The switching frequency is dynamically
regulation without optocoupler (flyback) programmable from 100 kHz to 2.2 MHz with an
– Accurate current limit (see the Device external resistor. Switching at 2.2 MHz minimizes AM
Comparison Table) band interference and allows for a small solution size
• EMI mitigation and fast transient response. The device provides a
selectable Dual Random Spread Spectrum to help
– Selectable dual random spread spectrum
reduce the EMI over a wide frequency range.
– Lead-less package
• Higher efficiency with low-power dissipation Device Information
– 133-mΩ RDSON switch PART NUMBER PACKAGE(1) BODY SIZE (NOM)
– Fast switching, small switching loss LM5158
WQFN (16) 3.00 mm × 3.00 mm
• Avoid AM band interference and crosstalk LM51581
– Optional clock synchronization
– Dynamically programmable wide switching (1) For all available packages, see the orderable addendum at
the end of the data sheet.
frequency from 100 kHz to 2.2 MHz
• Integrated protection features VSUPPLY VLOAD

– Constant current limiting over input voltage

– Selectable hiccup mode overload protection
Optional

BIAS VCC SW
– Programmable line UVLO UVLO FB
– OVP protection RT COMP

– Thermal shutdown SS PGOOD

PGND AGND MODE
• Accurate ±1% accuracy feedback reference
• Adjustable soft start
• PGOOD indicator Typical SEPIC Application
• Create a custom design using the LM5158x with
the WEBENCH® Power Designer
2 Applications
• Battery-powered wide input boost, SEPIC, flyback
converter
• LED bias supply
• Multiple-output flyback without optocoupler
• Loop powered fire detection
• Hold-up capacitor charger
• Power module

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 10 Application and Implementation................................ 27
2 Applications..................................................................... 1 10.1 Application Information........................................... 27
3 Description.......................................................................1 10.2 Typical Boost Application........................................ 27
4 Revision History.............................................................. 2 10.3 System Examples................................................... 30
5 Description (continued).................................................. 3 11 Power Supply Recommendations..............................33
6 Device Comparison Table...............................................3 12 Layout...........................................................................34
7 Pin Configuration and Functions...................................4 12.1 Layout Guidelines................................................... 34
8 Specifications.................................................................. 6 12.2 Layout Examples.................................................... 35
8.1 Absolute Maximum Ratings........................................ 6 13 Device and Documentation Support..........................36
8.2 ESD Ratings............................................................... 6 13.1 Device Support....................................................... 36
8.3 Recommended Operating Conditions.........................6 13.2 Documentation Support.......................................... 36
8.4 Thermal Information....................................................7 13.3 Receiving Notification of Documentation Updates..36
8.5 Electrical Characteristics.............................................7 13.4 Support Resources................................................. 36
8.6 Typical Characteristics................................................ 9 13.5 Trademarks............................................................. 36
9 Detailed Description......................................................12 13.6 Electrostatic Discharge Caution..............................37
9.1 Overview................................................................... 12 13.7 Glossary..................................................................37
9.2 Functional Block Diagram......................................... 13 14 Mechanical, Packaging, and Orderable
9.3 Feature Description...................................................13 Information.................................................................... 38
9.4 Device Functional Modes..........................................25

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
October 2021 * Initial Release

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5 Description (continued)
The device features an accurate peak current limit over the input voltage, which avoids overdesigning the power
inductor. Low operating current and pulse-skipping operation improve efficiency at light loads.
The device has built-in protection features such as overvoltage protection, line UVLO, thermal shutdown, and
selectable hiccup mode overload protection. Additional features include low shutdown IQ, programmable soft
start, precision reference, a power-good indicator, and external clock synchronization.
6 Device Comparison Table
DEVICE OPTION MINIMUM PEAK CURRENT LIMIT MAXIMUM SW VOLTAGE
LM5158 3.26 A
83 V (85-V abs max)
LM51581 1.63 A

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7 Pin Configuration and Functions

PGND

SW
SW
NC
16 15 14 13

PGND 1 12 NC

VCC 2 11 MODE
EP
BIAS 3 10 SS

PGO OD 4 9 FB

5 6 7 8

COMP
RT

EN/UV LO/SYNC

AGND
Figure 7-1. RTE Package 16-Pin WQFN Top View

Table 7-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NO. NAME
1, 16 PGND P Power ground pin. Source connection of the internal N-channel power MOSFET
Output of the internal VCC regulator and supply voltage input of the internal MOSFET driver.
2 VCC P
Connect a 1-µF ceramic bypass capacitor from this pin to PGND.
3 BIAS P Supply voltage input to the VCC regulator. Connect a bypass capacitor from this pin to PGND.
Power-good indicator. An open-drain output, which goes low if FB is below the undervoltage
4 PGOOD O
threshold (VUVTH). Connect a pullup resistor to the system voltage rail.
Switching frequency setting pin. The switching frequency is programmed by a single resistor
5 RT I
between RT and AGND.
Enable pin. The converter shuts down when the pin is less than the enable threshold (VEN).
Undervoltage lockout programming pin. The converter start-up and shutdown levels can be
programmed by connecting this pin to the supply voltage through a voltage divider. If using a
EN/UVLO/
6 I programmable UVLO, connect the low-side UVLO resistor to AGND. This pin must not be left
SYNC
floating. Connect to the BIAS pin if not used.
External synchronization clock input pin. The internal clock can be synchronized to an external clock
by applying a negative pulse signal into the pin.
7 AGND G Analog ground pin. Connect to the analog ground plane through a wide and short path.
Output of the internal transconductance error amplifier. Connect the loop compensation components
8 COMP O
between this pin and AGND.
Inverting input of the error amplifier. Connect a voltage divider to set the output voltage in boost,
9 FB I SEPIC, or primary-side regulated flyback topologies. Connect the low-side feedback resistor as close
to AGND as possible.
Soft-start time programming pin. An external capacitor and an internal current source set the ramp
10 SS I rate of the internal error amplifier reference during soft start. Connect the ground connection of the
capacitor to AGND.
MODE = 0 V or connect to AGND during initial power up: Hiccup mode protection is disabled and
spread spectrum is disabled.
MODE = 370 mV or connect a 37.4-kΩ resistor between this pin and AGND during initial power up:
Hiccup mode protection is enabled and spread spectrum is enabled.
11 MODE I
MODE = 620 mV or connect a 62.0-kΩ resistor between this pin and AGND during initial power up:
Hiccup mode protection is enabled and spread spectrum is disabled.
MODE > 1 V or connect a 100-kΩ resistor between this pin and AGND during initial power up:
Hiccup mode protection is disabled and spread spectrum is enabled.

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Table 7-1. Pin Functions (continued)

PIN
TYPE(1) DESCRIPTION
NO. NAME
13, 14 SW Switch pin. Drain connection of the internal N-channel power MOSFET
12, 15 NC — No internal electrical contact
Exposed pad of the package. The exposed pad must be connected to AGND and the large ground
— EP —
copper plane to decrease thermal resistance.

(1) G = Ground, I = Input, O = Output, P = Power

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8 Specifications
8.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range(1)
MIN MAX UNIT
BIAS to AGND –0.3 65
UVLO to AGND –0.3 VBIAS + 0.3
SS, RT to AGND(2) –0.3 3.8
Input V
FB to AGND –0.3 4.0
MODE to AGND –0.3 3.8
PGND to AGND –0.3 0.3
VCC to AGND –0.3 5.8(3)
PGOOD to AGND(4) –0.3 18
Output COMP to AGND(5) –0.3 V
SW to AGND (DC) –0.3 85
SW to AGND (5-ns transient) –6
Junction temperature, TJ (6) –40 150
°C
Storage temperature, Tstg –55 150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) These pins are not specified to have an external voltage applied.
(3) Operating lifetime is de-rated when the pin voltage is greater than 5.5 V.
(4) The maximum current sink is limited to 1 mA when VPGOOD > VBIAS.
(5) This pin has an internal max voltage clamp which can handle up to 1.6 mA.
(6) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

8.2 ESD Ratings

VALUE UNIT

Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000
V(ESD) V
discharge Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

Over the recommended operating junction temperature range(1)
MIN NOM MAX UNIT
VSUPPLY Boost converter input (when BIAS ≥ 3.2 V) 1.5 60 V
VLOAD Boost converter output VSUPPLY 83(2) V
VBIAS BIAS input(3) 3.2 60 V
VUVLO UVLO input 0 60 V
VFB FB input 0 4.0 V
ISW Switch current 0 See note(4) A
fSW Typical switching frequency 100 2200 kHz
fSYNC Synchronization pulse frequency 100 2200 kHz
TJ Operating junction temperature –40 125 °C

(1) Recommended Operating Conditions are conditions under the device is intended to be functional. For specifications and test
conditions, see the Electrical Characteristics.
(2) The boost converter output can be up to 83 V, but the SW pin voltage should be less than or equal to 85 V during transient.
(3) The BIAS pin operating range is from 3.2 V to 60 V when VCC is supplied from the internal VCC regulator.

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(4) The maximum switch current is limited by pre-programmed peak current limit (ILIM) when TJ < TTSD.

8.4 Thermal Information

LM5158x
THERMAL METRIC(1) RTE(QFN) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance (LM5158EVM-BST) 32.7 °C/W
RθJA Junction-to-ambient thermal resistance 45.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 44.8 °C/W
RθJB Junction-to-board thermal resistance 19.1 °C/W
ΨJT Junction-to-top characterization parameter (LM5158EVM-BST) 0.6 °C/W
ΨJT Junction-to-top characterization parameter 0.8 °C/W
ΨJB Junction-to-board characterization parameter (LM5158EVM-BST) 15.1 °C/W
ΨJB Junction-to-board characterization parameter 19.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.7 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

8.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C. Unless otherwise
stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ISHUTDOWN(BIAS) BIAS shutdown current VBIAS = 12 V, VUVLO = 0 V 2.6 5 μA
VBIAS = 12 V, VUVLO = 2.0 V, VFB = VREF,
IOPERATING(BIAS) BIAS operating current 670 850 μA
RT = 220 kΩ
VCC REGULATOR
VVCC-REG VCC regulation VBIAS = 8 V, IVCC = 18 mA 4.66 4.9 5.14 V
VVCC-
VCC UVLO threshold VCC rising 3.05 3.10 3.15 V
UVLO(RISING)

VCC UVLO hysteresis VCC falling 0.1 V

ENABLE
VEN(RISING) Enable threshold EN rising 0.4 0.52 0.7 V
VEN(FALLING) Enable threshold EN falling 0.33 0.49 0.63 V
VEN(HYS) Enable hysteresis EN falling 0.03 V
UVLO/SYNC
VUVLO(RISING) UVLO / SYNC threshold UVLO rising 1.425 1.5 1.575 V
VUVLO(FALLING) UVLO / SYNC threshold UVLO falling 1.370 1.45 1.520 V
VUVLO(HYS) UVLO / SYNC threshold hysteresis UVLO falling 0.05 V
IUVLO UVLO hysteresis current VUVLO = 1.6 V 4 5 6 μA
MODE, SPREAD SPECTRUM
FSW modulation (upper limit) 7.8%
FSW modulation (lower limit) –7.8%
SOFT START
ISS Soft-start current 9 10 11 μA
SS pulldown switch RDSON 50 Ω
PULSE WIDTH MODULATION
fsw1 Switching frequency RT = 220 kΩ 85 100 115 kHz

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Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C. Unless otherwise
stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fsw2 Switching frequency RT = 49.3 kΩ 388 440 492 kHz
fsw3 Switching frequency RT = 9.09 kΩ 1980 2200 2420 kHz
tON(MIN) Minimum on time RT = 9.09 kΩ 80 ns
DMAX1 Maximum duty cycle limit RT = 9.09 kΩ 80% 85% 90%
DMAX2 Maximum duty cycle limit RT = 220 kΩ 90% 93% 96%
RT regulation voltage 0.5 V
CURRENT LIMIT
ILIM Internal MOSFET current limit LM5158 3.26 3.75 4.24 A
Internal MOSFET current limit LM51581 1.63 1.875 2.12 A
HICCUP MODE PROTECTION
Hiccup enable cycles 64 Cycles
Hiccup timer reset cycles 8 Cycles
ERROR AMPLIFIER
VREF FB reference 0.99 1 1.01 V
Gm Transconductance 2 mA/V
COMP sourcing current VCOMP = 1.2 V 180 μA
COMP clamp voltage COMP rising (VUVLO = 2.0 V) 2.5 2.8 V
COMP clamp voltage COMP falling 1 1.1 V
ACS ΔVCOMP / ΔISW 0.19
OVP
VOVTH Overvoltage threshold FB rising (reference to VREF) 107% 110% 113%
Overvoltage threshold FB falling (reference to VREF) 105%
PGOOD
PGOOD pulldown switch RDSON 1-mA sinking 70 Ω
VUVTH Undervoltage threshold FB falling (reference to VREF) 87% 90% 93%
Undervoltage threshold FB rising (reference to VREF) 95%
POWER SWITCH
rDS(ON) Internal MOSFET on-resistance VBIAS = 12 V 133 290 mΩ
VBIAS = 3.5 V 138 300 mΩ
Leakage current VSW = 12 V 1100 nA
THERMAL SHUTDOWN
TTSD Thermal shutdown threshold Temperature rising 175 °C
Thermal shutdown hysteresis 15 °C

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8.6 Typical Characteristics

5 5
4.75 BIAS = 12V
4.5 BIAS = 60V
4.5

BIAS Shutdown Current (A)

BIAS Shutdown Current (A)

4
4.25
3.5 4
3 3.75
2.5 3.5
3.25
2
3
1.5
2.75
1 2.5
0.5 2.25

0 2
-40 -20 0 20 40 60 80 100 120 140 160
0 5 10 15 20 25 30 35 40 45 50 55 60
Temperature (C)
VBIAS (V)

Figure 8-1. BIAS Shutdown Current vs VBIAS Figure 8-2. BIAS Shutdown Current vs
Temperature
1000 10
BIAS
900
VCC
800 8
BIAS operating current (A)

700
600 6
Voltage (V)

500
400
4
300
200
2
100
0
-40 -20 0 20 40 60 80 100 120 140 160 0
Temperature (C) 0 2 4 6 8 10
VBIAS (V)
Figure 8-3. BIAS Operating Current vs Temperature
Figure 8-4. VVCC vs VBIAS
6 11
10.8
10.6
Soft-Start Current (A)

10.4
4
10.2
VVCC (V)

10
9.8
2 9.6
9.4
9.2
9
0 -40 -20 0 20 40 60 80 100 120 140 160
0 20 40 60 80 100 120 Temperature (C)
IVCC (mA)
Figure 8-6. ISS vs Temperature
Figure 8-5. VVCC vs IVCC

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0.57 1.6
0.56 EN Rising UVLO Rising
EN Falling 1.58 UVLO Falling
0.55
1.56
0.54

UVLO Threshold (V)

1.54
EN Threshold (V)

0.53
0.52 1.52
0.51 1.5
0.5 1.48
0.49
1.46
0.48
1.44
0.47
0.46 1.42
0.45 1.4
-40 -20 0 20 40 60 80 100 120 140 160 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (C) Temperature (C)

Figure 8-7. EN Threshold vs Temperature Figure 8-8. UVLO Threshold vs Temperature

1.01 2400
1.008 2200
2000
1.006
1800
1.004
FB Reference (V)

1600

Frequency (kHz)
1.002 1400
1 1200
0.998 1000
800
0.996
600
0.994
400
0.992 200
0.99 0
-40 -20 0 20 40 60 80 100 120 140 160 8 10 20 30 40 50 60 70 100 200 250
Temperature (C) RT Resistor (k)
Figure 8-9. FB Reference vs Temperature Figure 8-10. Frequency vs RT Resistance
110 2400 4.5 3
RT=220k LM5158
Frequency, RT=220k  (kHz)

108 RT=9.09k 2360 LM51581 2.75

4.25
106 2320

LM51581 Current Limit (A)

LM5158 Current Limit (A)

4 2.5
Frequency, RT=9.09k

104 2280
102 2240 3.75 2.25

100 2200 3.5 2

98 2160
3.25 1.75
96 2120
3 1.5
94 2080
92 2040 2.75 1.25

90 2000 2.5 1
-40 -20 0 20 40 60 80 100 120 140 160 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (C) Temperature (C)

Figure 8-11. Frequency vs Temperature Figure 8-12. Current Limit Threshold vs

Temperature

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4.5 3 290
LM5158
4.25 LM51581 2.75 270

LM51581 Peak Current Limit (A)

LM5158 Peak Current Limit (A)

4 2.5 250
230
3.75 2.25

RDSON (m)
210
3.5 2
190
3.25 1.75
170
3 1.5
150
2.75 1.25 130
FSW=1MHz, LM=5H, VIN=6V
2.5 1 110 BIAS = 12V
0 20 40 60 80 100 BIAS = 3.5V
Duty Cycle (%) 90
-40 -20 0 20 40 60 80 100 120 140 160
Temperature (C)

Figure 8-13. Peak Current Limit vs Duty Cycle Figure 8-14. Internal MOSFET Drain Source On-
state Resistance vs Temperature
200 94
190
93
180

Maximum Duty Cycle Limit (%)

170 92
Minimum On-Time (ns)

160
91
150
140 90
130
89
120
110 88
100 87
90
80 86
70 85
0 250 500 750 1000 1250 1500 1750 2000 2250 0 250 500 750 1000 1250 1500 1750 2000 2250
Frequency (kHz) Frequency (kHz)
Figure 8-15. Minimum On Time vs Frequency Figure 8-16. Maximum Duty Cycle Limit vs
Frequency

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9 Detailed Description
9.1 Overview
The LM5158x is a wide input range, non-synchronous boost converter that uses peak-current-mode control. The
device can be used in boost, SEPIC, and flyback topologies.
The device can start up with a minimum of 3.2 V. It can operate with input supply voltage as low as 1.5 V if the
BIAS pin is greater than 3.2 V. The internal VCC regulator also supports BIAS pin operation up to 60 V (65-V
absolute maximum). The switching frequency is dynamically programmable from 100 kHz to 2.2 MHz with an
external resistor. Switching at 2.2 MHz minimizes AM band interference and allows for a small solution size and
fast transient response. The device provides an optional dual random spread spectrum to help reduce the EMI
over a wide frequency span.
The device features an accurate current limit over the input voltage range. Low operating current and pulse
skipping operation improve efficiency at light loads.
The device also has built-in protection features such as overvoltage protection, line UVLO, and thermal
shutdown. Selectable hiccup mode overload protection protects the converter during prolonged current limit
conditions. Additional features include the following:
• Low shutdown IQ
• Programmable soft start
• Precision reference
• Power-good indicator
• External clock synchronization

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9.2 Functional Block Diagram

VSUPPLY LM D1 VLOAD

CIN COUT
RFBT
RLOAD
FB

VUVTH PGOOD BIAS SW RFBB

+
IUVLO
±
VCC_OK FB
VSUPPLY + AGND
± TSD Ready OVP
VUVLO VOVTH ±
RUVLOT + BIAS
SYNC
Detector Clock_Sync VCC
EN VCC
RUVLOB +
/UVLO VCC_EN Regulator
VCC_EN
/SYNC ±
VEN Hiccup CVCC
C/L Comparator Mode VCC
VCC_OK
ICS + UVLO
ILIM S Q
±

ISS PWM ICS

R Q
1.1V+VSLOPE Comparator
SS VCS - + Gain
+
= ACS
+
VREF + ± Clock Generator MODE
CSS VCS
± Spread Spectrum Selection
Gm Clock_Sync
FB AGND PGND
COMP RT MODE

RT
RCOMP

CCOMP

9.3 Feature Description

9.3.1 Line Undervoltage Lockout (EN/UVLO/SYNC Pin)
The device has a dual-level EN/UVLO circuit. During power-on, if the BIAS pin voltage is greater than 2.7 V,
the UVLO pin voltage is in between the enable threshold (VEN), and the UVLO threshold (VUVLO) for more than
1.5 µs (see Section 9.3.6 for more details), the device starts up and an internal configuration starts. The device
typically requires a 90-µs internal start-up delay before entering standby mode. In standby mode, the VCC
regulator and RT regulator are operational, the SS pin is grounded, and there is no switching at the SW pin.

IUVLO

VSUPPLY
±
VUVLO
RUN
RUVLOT +

RUVLOB EN
/UVLO +
/SYNC VCC_EN
±
VEN

Figure 9-1. Line UVLO and Enable

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When the UVLO pin voltage is above the UVLO threshold, the device enters run mode. In run mode, a
soft-start sequence starts if the VCC voltage is greater than VCC UV threshold (VVCC-UVLO). UVLO hysteresis is
accomplished with an internal 50-mV voltage hysteresis and an additional 5-μA current source that is switched
on or off. When the UVLO pin voltage exceeds the UVLO threshold, the UVLO hysteresis current source
is enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the UVLO
threshold, the current source is disabled, causing the voltage at the UVLO pin to fall quickly. When the UVLO pin
voltage is less than the enable threshold (VEN), the device enters shutdown mode after a 40-µs (typical) delay
with all functions disabled.
90-µs (typical) > 3 cycles
internal start-up delay

BIAS 2.7 V
= VSUPPLY
VUVLO

VEN
UVLO
VVCC-UVLO
Shutdown

VREF
VCC
1.5 µs
SS is grounded
UVLO should be greater than with 2 cycles
VEN more than 1.5 µs to start-up delay
SS

SW

TSS
SS VLOAD
=
1V VLOAD(TARGET)

VLOAD

Figure 9-2. Boost Start-Up Waveforms Case 1: Start-Up by VCC UVLO, UVLO Toggle After Start-Up

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> 40us(typical) 90us (typical)

90-µs (typical)
internal start-up delay
internal start-up delay

BIAS 2.7 V
= VSUPPLY
VUVLO

VEN

UVLO
VVCC-UVLO
Shutdown
VREF
VCC
1.5 µs
SS is grounded
UVLO should be greater than with 2 cycles
0.55 V more than 1.5 µs to start-up delay
SS

SW

TSS
SS VLOAD
=
1V VLOAD(TARGET)

VLOAD

Figure 9-3. Boost Start-Up Waveforms Case 2: Start-Up by VCC UVLO, EN Toggle After Start-Up

The external UVLO resistor divider must be designed so that the voltage at the UVLO pin is greater than 1.5
V (typical) when the input voltage is in the desired operating range. The values of RUVLOT and RUVLOB can be
calculated as shown in Equation 1 and Equation 2.

VUVLO(FALLING)
VSUPPLY(ON) u VSUPPLY(OFF)
VUVLO(RISING)
RUVLOT
IUVLO
(1)

where
• VSUPPLY(ON) is the desired start-up voltage of the converter.
• VSUPPLY(OFF) is the desired turn-off voltage of the converter.

VUVLO(RISING) u RUVLOT
RUVLOB
VSUPPLY(ON) VUVLO(RISING)
(2)

A UVLO capacitor (C UVLO) is required in case the input voltage drops below the VSUPPLY(OFF) momentarily during
the start-up or during a severe load transient at the low input voltage. If the required UVLO capacitor is large,
an additional series UVLO resistor (RUVLOS) can be used to quickly raise the voltage at the UVLO pin when the
5-μA hysteresis current turns on.

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IUVLO

VSUPPLY

VUVLO
RUVLOT ±
RUVLOS RUN
+
RUVLOB
CUVLO EN/UVLO/SYNC

Figure 9-4. Line UVLO Using Three UVLO Resistors

Do not leave the UVLO pin floating. Connect to the BIAS pin if not used.
9.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)
The device has an internal wide input VCC regulator that is sourced from the BIAS pin. The wide input VCC
regulator allows the BIAS pin to be connected directly to supply voltages from 3.2 V to 60 V (transient protection
up to 65 V).
The VCC regulator turns on when the device is in standby or run mode. When the BIAS pin voltage is below the
VCC regulation target, the VCC output tracks the BIAS with a small dropout voltage. When the BIAS pin voltage
is greater than the VCC regulation target, the VCC regulator provides a 5-V supply (typical) for the device and
the internal N-channel MOSFET driver.
The VCC regulator sources current into the capacitor connected to the VCC pin. The recommended VCC
capacitor value is 1 µF.
The minimum supply voltage after start-up can be further decreased by supplying the BIAS pin from the boost
converter output or from an external power supply as shown in Figure 9-5. Also, this configuration allows the
device to handle more power when the VSUPPLY is less than 5 V. Practical minimum supply voltage after start-up
is decided by the maximum duty cycle limit (DMAX).
VSUPPLY VLOAD

VLOAD
Optional

BIAS VCC SW

UVLO FB
RT COMP
SS PGOOD
PGND AGND MODE

Figure 9-5. Decrease the Minimum Operating Voltage After Start-Up

In flyback topology, the internal power dissipation of the device can be decreased by supplying the BIAS using
an additional transformer winding, especially in PSR flyback. In this configuration, the external BIAS supply
voltage (VAUX) must be greater than the regulation target of the external LDO, and the BIAS pin voltage must
always be greater than 3.2 V.

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VSUPPLY VLOAD =12V

Optional
VAUX =12V

<11V

VAUX

BIAS VCC SW

UVLO FB
RT COMP
SS PGOOD
PGND AGND MODE

Figure 9-6. External BIAS Supply (PSR Flyback)

9.3.3 Soft Start (SS Pin)

The soft-start feature helps the converter gradually reach the steady state operating point, thus reducing start-up
stresses and surges. The device regulates the FB pin to the SS pin voltage or the internal reference, whichever
is lower.
At start-up, the internal 10-μA soft-start current source (ISS) turns on after the VCC voltage exceeds the VCC
UV threshold. The soft-start current gradually increases the voltage on an external soft-start capacitor connected
to the SS pin. This results in a gradual rise of the output voltage. The SS pin is pulled down to ground by an
internal switch when the VCC is less than the VCC UVLO threshold, the UVLO is less than the UVLO threshold,
during hiccup mode off time or thermal shutdown.
In boost topology, soft-start time (tSS) varies with the input supply voltage. The soft-start time in boost topology is
calculated as shown in Equation 3.

CSS § VSUPPLY ·
tSS u ¨1 ¸
ISS © VLOAD ¹ (3)

In SEPIC topology, the soft-start time (tSS) is calculated as follows.

CSS
tSS
ISS (4)

TI recommends choosing the soft-start time long enough so that the converter can start up without going into an
overcurrent state. See Section 9.3.11 for more detailed information.
Figure 9-7 shows an implementation of primary-side soft start in flyback topology.

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FB SS COMP

Figure 9-7. Primary-Side Soft Start in Flyback

Figure 9-8 shows an implementation of secondary-side soft start in flyback topology.

VLOAD

Secondary Side
Soft-start

Figure 9-8. Secondary-Side Soft Start in Flyback

9.3.4 Switching Frequency (RT Pin)

The switching frequency of the device can be set by a single RT resistor connected between the RT and the
AGND pins. The resistor value to set the RT switching frequency (fRT) is calculated as shown in Equation 5.

2.21u 1010
RT 955
fRT(TYPICAL)
(5)

The RT pin is regulated to 0.5 V by the internal RT regulator when the device is enabled.
9.3.5 Dual Random Spread Spectrum – DRSS (MODE Pin)
The device provides a digital spread spectrum, which reduces the EMI of the power supply over a wide
frequency range. This function is enabled by a single resistor (37.4 kΩ or 100 kΩ) between the MODE pin
and the AGND pin or by programming the MODE pin voltage (370 mV or greater than 1.0 V) during initial
power up. When spread spectrum is enabled, the internal modulator dithers the internal clock. When an external
synchronization clock is applied to the SYNC pin, the internal spread spectrum is disabled. DRSS (a) combines
a low frequency triangular modulation profile (b) with a high frequency cycle-by-cycle random modulation profile
(c). The low frequency triangular modulation improves performance in lower radio frequency bands (for example,
the AM band), while the high frequency random modulation improves performance in higher radio frequency
bands (for example, the FM band). In addition, the frequency of the triangular modulation is further modulated
randomly to reduce the likelihood of any audible tones. In order to minimize output voltage ripple caused by
spread spectrum, duty cycle is modified on a cycle-by-cycle basis to maintain a nearly constant duty cycle when
dithering is enabled (see Figure 9-9).

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Frequency

0.156 x fSW
fSW (a) Low + High Frequency
Random Modulation

(b) Low Frequency

Random Modulation

(c) High Frequency

Random Modulation

Spread Spectrum Spread Spectrum

OFF ON

Figure 9-9. Dual Random Spread Spectrum

9.3.6 Clock Synchronization (EN/UVLO/SYNC Pin)

The switching frequency of the device can be synchronized to an external clock by pulling down the EN/UVLO/
SYNC pin. The internal clock of the device is synchronized at the falling edge, but ignores the falling edge input
during the forced off time, which is determined by the maximum duty cycle limit. The external synchronization
clock must pull down the EN/UVLO/SYNC pin voltage below VUVLO(FALLING). The duty cycle of the pulldown
pulse is not limited, but the minimum pulldown pulse width must be greater than 150 ns, and the minimum
pullup pulse width must be greater than 250 ns. Figure 9-10 shows an implementation of the remote shutdown
function. The UVLO pin can be pulled down by a discrete MOSFET or an open-drain output of an MCU. In
this configuration, the device stops switching immediately after the UVLO pin is grounded, and the device shuts
down 40 µs (typical) after the UVLO pin is grounded.
VSUPPLY

MCU

UVLO/SYNC
SHUTDOWN

Figure 9-10. UVLO and Shutdown

Figure 9-11 shows an implementation of shutdown and clock synchronization functions together. In this
configuration, the device stops switching immediately when the UVLO pin is grounded, and the device shuts
down if the fSYNC stays in high logic state for longer than 40 µs (typical) (UVLO is in low logic state for more than
40 µs (typical)). The device runs at fSYNC if clock pulses are provided after the device is enabled.

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VSUPPLY

MCU

UVLO/SYNC

FSYNC

Figure 9-11. UVLO, Shutdown, and Clock Synchronization

Figure 9-13 and Figure 9-14 show implementations of standby and clock synchronization functions together. In
this configuration, The device stops switching immediately if fSYNC stays in high logic state and enters Standby
mode if fSYNC stays in high logic state for longer than two switching cycles. The device runs at fSYNC if clock
pulses are provided. Because the device can be enabled when the UVLO pin voltage is greater than the enable
threshold for more than 1.5 µs, the configurations in Figure 9-13 and Figure 9-14 are recommended if the
external clock synchronization pulses are provided from the start before the device is enabled. This 1.5-µs
requirement can be relaxed when the duty cycle of the synchronization pulse is greater than 50%. Figure 9-12
shows the required minimum duty cycle to start up by synchronization pulses. When the switching frequency is
greater than 1.1 MHz, the UVLO pin voltage must be greater than the enable threshold for more than 1.5 µs
before applying the external synchronization pulse.
80
75
70
65
60
Duty Cycle [%]

55
50
45
40
35
30
25
20
15
100 200 300 400 500 600 700 800 900 1000 1100
fSW [kHz] SUby

Figure 9-12. Required Duty Cycle to Start Up by External Synchronization Clock

VSUPPLY

MCU

UVLO/SYNC
>0.7V

FSYNC

Figure 9-13. UVLO, Standby, and Clock Synchronization (a)

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VSUPPLY

MCU UVLO/SYNC

FSYNC

Figure 9-14. UVLO, Standby, and Clock Synchronization (b)

If the UVLO function is not required, the shutdown and clock synchronization functions can be implemented
together by using one push-pull output of the MCU. In this configuration, the device shuts down if fSYNC stays
in low logic state for longer than 40 µs (typical). The device is enabled if fSYNC stays in high logic state for
longer than 1.5 µs. The device runs at fSYNC if clock pulses are provided after the device is enabled. Also, in
this configuration, it is recommended to apply the external clock pulses after the BIAS is supplied. By limiting the
current flowing into the UVLO pin below 1 mA using a current limiting resistor, the external clock pulses can be
supplied before the BIAS is supplied (see Figure 9-15).
MCU

10
UVLO/SYNC

FSYNC

Figure 9-15. Shutdown and Clock Synchronization

Figure 9-16 shows an implementation of inverted enable using external circuit.

VSUPPLY

UVLO/SYNC

LMV431

Figure 9-16. Inverted UVLO

The external clock frequency (fSYNC) must be within +25% and –30% of fRT(TYPICAL). Because the maximum
duty cycle limit and the peak current limit with slope resistor (RSL) are affected by the clock synchronization,
take extra care when using the clock synchronization function. See Section 9.3.7 and Section 9.3.12 for more
information.
9.3.7 Current Sense and Slope Compensation
The device senses switch current, which flows into the SW pin and provides a fixed internal slope compensation
ramp, which helps prevent subharmonic oscillation at high duty cycle. The internal slope compensation ramp is
added to the sensed switch current for the PWM operation. But, no slope compensation ramp is added to the

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sensed inductor current for the current limit operation to provide an accurate peak current limit over the input
supply voltage (see Figure 9-17).

SW
Current Limit
Comparator
± ILIM
ICS
+
1.1V+VSLOPE
+ -
+
VCS
I-to-V
PWM ±
Gain = ACS
Comparator
COMP

CHF RCOMP
(optional)

CCOMP

Figure 9-17. Current Sensing and Slope Compensation

V VCOMP

Slope
Compensation VSLOPE x D + 1.1V
Ramp

ACS x ICS

Figure 9-18. Current Sensing and Slope Compensation (a) at PWM Comparator Inputs

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I
ILIM

Sensed Inductor
Current (ICS)

Figure 9-19. Current Sensing (b) at Current Limit Comparator Inputs

Use Equation 6 to calculate the value of the peak slope voltage (VSLOPE).

fRT
VSLOPE 500mV u
fSYNC (6)

where
• fSYNC is fRT if clock synchronization is not used.
According to peak current mode control theory, the slope of the compensation ramp must be greater than half
of the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle. Therefore, the
minimum amount of slope compensation in boost topology must satisfy the following inequality:

VLOAD VF VSUPPLY
0.5 u u ACS u Margin 500mV u fSW
LM (7)

where
• VF is a forward voltage drop of D1, the external diode.
Typically 82% of the sensed inductor current falling slope is known as an optimal amount of the slope
compensation. By increasing the margin to 1.6, the amount of slope compensation becomes close to the optimal
amount.
If clock synchronization is not used, the fSW frequency equals the fRT frequency. If clock synchronization is used,
the fSW frequency equals the fSYNC frequency.
9.3.8 Current Limit and Minimum On Time
The device provides cycle-by-cycle peak current limit protection that turns off the internal MOSFET when the
inductor current reaches the current limit threshold (ILIM). To avoid an unexpected hiccup mode operation during
a harsh load transient condition, it is recommended to have more margin when programming the peak-current
limit.
Boost converters have a natural pass-through path from the supply to the load through the high-side power
diode (D1). Because of this path and the minimum on-time limitation of the device, boost converters cannot
provide current limit protection when the output voltage is close to or less than the input supply voltage. The
minimum on time is shown in Figure 8-15 and is calculated as Equation 8.

800 × 10−15
1 −6 RT ≥ 20.83kΩ
tON MIN ≈ 8 × RT + 4 × 10 (8)
80 × 10−9 RT < 20.83kΩ

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9.3.9 Feedback and Error Amplifier (FB, COMP Pin)

The feedback resistor divider is connected to an internal transconductance error amplifier, which features high
output resistance (RO = 10 MΩ) and wide bandwidth (BW = 7 MHz). The internal transconductance error
amplifier sources current, which is proportional to the difference between the FB pin and the SS pin voltage or
the internal reference, whichever is lower. The internal transconductance error amplifier provides symmetrical
sourcing and sinking capability during normal operation and reduces its sinking capability when the FB is greater
than OVP threshold.
To set the output regulation target, select the feedback resistor values as shown in Equation 9.

§R ·
VLOAD VREF u ¨ FBT 1¸
© RFBB ¹ (9)

The output of the error amplifier is connected to the COMP pin, allowing the use of a Type 2 loop compensation
network. RCOMP, CCOMP, and optional CHF loop compensation components configure the error amplifier gain and
phase characteristics to achieve a stable loop response. The absolute maximum voltage rating of the FB pin is
4.0 V. If necessary, the feedback resistor divider input can be clamped by using an external Zener diode.
The COMP pin features internal clamps. The maximum COMP clamp limits the maximum COMP pin voltage
below its absolute maximum rating even in shutdown. The minimum COMP clamp limits the minimum COMP
pin voltage in order to start switching as soon as possible during no load to heavy load transition. The minimum
COMP clamp is disabled when FB is connected to ground in flyback topology.
9.3.10 Power-Good Indicator (PGOOD Pin)
The device has a power-good indicator (PGOOD) to simplify sequencing and supervision. The PGOOD switches
to a high impedance open-drain state when the FB pin voltage is greater than the feedback undervoltage
threshold (VUVTH), the VCC is greater than the VCC UVLO threshold and the UVLO/EN is greater than
the EN threshold. A 25-μs deglitch filter prevents any false pulldown of the PGOOD due to transients. The
recommended minimum pullup resistor value is 10 kΩ.
Due to the internal diode path from the PGOOD pin to the BIAS pin, the PGOOD pin voltage cannot be greater
than VBIAS + 0.3 V.
9.3.11 Hiccup Mode Overload Protection (MODE Pin)
To further protect the converter during prolonged current limit conditions, the device provides a selectable hiccup
mode overload protection. This function is enabled by a single resistor (37.4 kΩ or 62.0 kΩ) between the MODE
pin and the AGND pin or by programming the MODE pin voltage (370 mV or 620 mV) during initial power
up. The internal hiccup mode fault timer of the device counts the PWM clock cycles when the cycle-by-cycle
current limiting occurs after soft start is finished. When the hiccup mode fault timer detects 64 cycles of current
limiting, an internal hiccup mode off timer forces the device to stop switching and pulls down SS. Then, the
device restarts after 32,768 cycles of hiccup mode off time. The 64 cycle hiccup mode fault timer is reset if eight
consecutive switching cycles occur without exceeding the current limit threshold. The soft-start time must be long
enough not to trigger the hiccup mode protection after the soft start is finished.
4 cycles of
7 normal current limit
64 cycles of 32768 hiccup 60 cycles of switching 32768 hiccup
current limit mode off cycles current limit cycles mode off cycles

Inductor Current

Time

Figure 9-20. Hiccup Mode Overload Protection

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9.3.12 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
The practical duty cycle is greater than the estimated due to voltage drops across the MOSFET and sense
resistor. The estimated duty cycle is calculated as shown in Equation 10.

VSUPPLY
D 1
VLOAD VF
(10)

When designing boost converters, the maximum required duty cycle must be reviewed at the minimum supply
voltage. The minimum input supply voltage that can achieve the target output voltage is limited by the maximum
duty cycle limit, and it can be estimated as follows.

VSUPPLY(MIN) | VLOAD VF u 1 DMAX ISUPPLY(MAX) u RDCR ISUPPLY(MAX) u 110m u DMAX (11)

where
• ISUPPLY(MAX) is the maximum input current.
• RDCR is the DC resistance of the inductor.

fSYNC
DMAX1 1 0.1u
fRT
(12)

DMAX2 1 100ns u fSW

(13)

The minimum input supply voltage can be further decreased by supplying fSYNC, which is less than fRT. Practical
DMAX is DMAX1 or DMAX2, whichever is lower.
9.3.13 Internal MOSFET (SW Pin)
The device provides an internal switch where rDS(ON) is typically 133 mΩ when the BIAS pin is greater than 5 V.
The rDS(ON) of the internal switch is increased when the BIAS pin is less than 5 V. The device temperature must
be checked at the minimum supply voltage especially when the BIAS pin is less than 5 V.
The dV/dT of the SW pin must be limited during the 90-µs internal start-up delay to avoid a false turn-on, which
is caused by the coupling through CDG parasitic capacitance of the internal MOSFET switch.
9.3.14 Overvoltage Protection (OVP)
The device has OVP for the output voltage. OVP is sensed at the FB pin. If the voltage at the FB pin rises above
the overvoltage threshold (VOVTH), OVP is triggered and switching stops. During OVP, the internal error amplifier
is operational, but the maximum source and sink capability is decreased to 60 µA.
9.3.15 Thermal Shutdown (TSD)
An internal thermal shutdown turns off the VCC regulator, disables switching, and pulls down the SS when
the junction temperature exceeds the thermal shutdown threshold (TTSD). After the junction temperature is
decreased by 15°C, the VCC regulator is enabled again and the device performs a soft start.
9.4 Device Functional Modes
9.4.1 Shutdown Mode
If the EN/UVLO/SYNC pin voltage is below VEN for longer than 40 µs (typical), the device goes into shutdown
mode with all functions disabled. In shutdown mode, the device decreases the BIAS pin current consumption to
below 2.6 μA (typical).

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9.4.2 Standby Mode

If the EN/UVLO/SYNC pin voltage is greater than VEN and below VUVLO for longer than 1.5 µs, the device enters
standby mode with the VCC regulator operational, the RT regulator operational, the SS pin grounded, and no
switching. The PGOOD is activated when the VCC voltage is greater than the VCC UV threshold.
9.4.3 Run Mode
If the UVLO pin voltage is above VUVLO and the VCC voltage is sufficient, the device enters run mode.
9.4.3.1 Spread Spectrum Enabled
The spread spectrum function is enabled by a single resistor (37.4 kΩ ±5% or 100 kΩ ±5%) between the MODE
pin and the AGND pin or by programming the MODE pin voltage (370mV ±10% or greater than 1.0 V) during
initial power up. To switch the spread spectrum function, EN must be grounded for more than 60 μs or VCC must
be fully discharged.
9.4.3.2 Hiccup Mode Protection Enabled
Hiccup mode protection is enabled by a single resistor (37.4 kΩ ±5% or 62.0 kΩ ±5%) between the MODE pin
and the AGND pin or by programming the MODE pin voltage (370 mV ±10% or 620 mV ±10%) during initial
power up. To switch the hiccup mode protection function, EN must be grounded for more than 60 μs or VCC
must be fully discharged.

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10 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

10.1 Application Information

TI provides application notes explaining how to design boost and flyback converters using the device. These
comprehensive application notes include component selections and loop response optimization.
See these application reports for more information on loop response and component selection:
• How to Design a Boost Converter Using LM5157x / LM5158x
• How to Design an Isolated Flyback Converter Using LM5157x / LM5158x
10.2 Typical Boost Application
Figure 10-1 shows all optional components to design a boost converter.
RSNB CSNB

VSUPPLY LM VLOAD

CBIAS RBIAS D1
CVCC
CIN
COUT1 COUT2
RUVLOT
BIAS VCC SW + RLOAD
RUVLOS RFBT ±
UVLO FB

RUVLOB RT PGOOD MCU_VCC

SS COMP RFBB
CUVLO CSS
RT PGND AGND MODE
CHF
RMODE RCOMP

CCOMP

Figure 10-1. Typical Boost Converter Circuit with Optional Components

10.2.1 Design Requirements

Table 10-1 shows the intended input, output, and performance parameters for this application example.
Table 10-1. Design Example Parameters
DESIGN PARAMETER VALUE
Minimum input supply voltage (VSUPPLY(MIN)) 6V
Target output voltage (VLOAD) 12 V
Maximum load current (ILOAD) 1.2 A (≈ 14.4 Watt)
Typical switching frequency (fSW) 2100 kHz

10.2.2 Detailed Design Procedure

Use the Quick Start Calculator to expedite the process of designing of a regulator for a given application.
Download these Quick Start Calculator for more information on loop response and component selection:
• LM5158x-Q1 Excel Quickstart Calculator for Boost Converter Design
• LM5158x-Q1 Excel Quickstart Calculator for isolated Flyback Converter Design
• LM5158x-Q1 Excel Quickstart Calculator for SEPIC Converter Design

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The device is also WEBENCH® Designer enabled. The WEBENCH software uses an iterative design procedure
and accesses comprehensive data bases of components when generating a design.
10.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5158x device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2.2.2 Recommended Components
Table 10-2 shows a recommended list of materials for this typical application.
Table 10-2. List of Materials
REFERENCE
QTY. SPECIFICATION MANUFACTURER(1) PART NUMBER
DESIGNATOR
RT 1 RES, 9.53 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 Vishay-Dale CRCW06039K53FKEA
RFBT 1 RES, 49.9 k, 1%, 0.1 W, 0603 Yageo America RC0603FR-0749K9L
RFBB 1 RES, 4.53 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 Vishay-Dale CRCW06034K53FKEA
Inductor, Shielded, Composite, 1.5 μH, 14 A,
LM 1 Coilcraft XEL6030-152MEB
0.01052 Ω, AEC-Q200 Grade 1, SMD
COUT1 6 CAP, CERM, 4.7 µF, 50 V, ±10%, X7R, 1210 TDK C3225X7R1H475K250AB
CAP, Aluminum Polymer, 100 µF, 50 V, ±20%, 0.025
COUT2 (Bulk) 2 Chemi-Con HHXB500ARA101MJA0G
Ω, AEC-Q200 Grade 2, D10xL10mm SMD
CIN1 4 CAP, CERM, 10 µF, 50 V, ±10%, X7R, 1210 MuRata GRM32ER71H106KA12L
CAP, AL, 22 μF, 100 V, ±20%, 1.3 Ω, AEC-Q200
CIN2 (Bulk) 1 Panasonic EEE-FK2A220P
Grade 2, SMD
D1 1 Diode, Schottky, 45 V, 10 A, AEC-Q101, CFP15 Nexperia PMEG045V100EPDAZ
RCOMP 1 RES, 2.61 k, 1%, 0.1 W, 0603 Yageo America RC0603FR-072K61L
CCOMP 1 CAP, CERM, 0.01 μF, 50 V, ±10%, X7R, 0603 Kemet C0603X103K5RACTU
CAP, CERM, 100 pF, 50 V, ±5%, C0G/NP0, AEC-
CHF 1 TDK CGA3E2NP01H101J080AA
Q200 Grade 0, 0603
RUVLOT 1 RES, 61.9 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 Vishay-Dale CRCW060361K9FKEA
RUVLOB 1 RES, 71.5 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 Vishay-Dale CRCW060371K5FKEA
RUVLOS 1 RES, 0, 5%, 0.1 W, 0603 Yageo America RC0603JR-070RL
CSS 1 CAP, CERM, 0.022 μF, 50 V, ±10%, X7R, 0603 Kemet C0603X223K5RACTU
RBIAS 1 RES, 0, 5%, 0.1 W, 0603 Yageo America RC0603JR-070RL
CAP, CERM, 0.1 μF, 100 V, ±10%, X7R, AEC-Q200
CBIAS 1 MuRata GCJ188R72A104KA01D
Grade 1, 0603
CAP, CERM, 1 µF, 16 V, ±10%, X7R, AEC-Q200
CVCC 1 TDK CGA3E1X7R1C105K080AC
Grade 1, 0603
RPG 1 RES, 100 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 Vishay-Dale CRCW0603100KFKEA
RMODE 1 RES, 0, 5%, 0.1 W, 0603 Yageo America RC0603JR-070RL

(1) See the Third-Party Products Disclaimer.

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10.2.2.3 Inductor Selection (LM)

When selecting the inductor, consider three key parameters: inductor current ripple ratio (RR), falling slope of the
inductor current, and RHP zero frequency (fRHP).
The inductor current ripple ratio is selected to have a balance between core loss and copper loss. The
falling slope of the inductor current must be low enough to prevent subharmonic oscillation at high duty cycle
(additional RSL resistor is required if not). Higher fRHP (equal to lower inductance) allows a higher crossover
frequency and is always preferred when using a small value output capacitor.
The inductance value can be selected to set the inductor current ripple between 30% and 70% of the average
inductor current as a good compromise between RR, FRHP, and inductor falling slope.
10.2.2.4 Output Capacitor (COUT)
There are a few ways to select the proper value of output capacitor (COUT). The output capacitor value can be
selected based on output voltage ripple, output overshoot, or undershoot due to load transient.
The ripple current rating of the output capacitors must be enough to handle the output ripple current. By using
multiple output capacitors, the ripple current can be split. In practice, ceramic capacitors are placed closer to the
diode and the MOSFET than the bulk aluminum capacitors in order to absorb the majority of the ripple current.
10.2.2.5 Input Capacitor
The input capacitors decrease the input voltage ripple. The required input capacitor value is a function of the
impedance of the source power supply. More input capacitors are required if the impedance of the source power
supply is not low enough.
10.2.2.6 Diode Selection
A Schottky is the preferred type for D1 diode due to its low forward voltage drop and small reverse recovery
charge. Low reverse leakage current is important parameter when selecting the Schottky diode. The diode must
be rated to handle the maximum output voltage plus any switching node ringing. Also, it must be able to handle
the average output current. For the optimal performance, it is highly recommended to use a diode with a junction
capacitance lower than 1 nF at 0 V.
10.2.3 Application Curve

100%

95%

90%

85%

80%
Efficiency (%)

75%

70%

65%

60%
VIN = 3.5 V
55% VIN = 4V
VIN = 6V
VIN = 9V
50%
0 0.2 0.4 0.6 0.8 1 1.2
IOUT (A)

Figure 10-2. Efficiency Versus Output Current

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10.3 System Examples

VSUPPLY VLOAD

BIAS VCC SW

UVLO FB
RT COMP
SS PGOOD
PGND AGND MODE

Figure 10-3. Typical Boost Application

VSUPPLY VLOAD

Optional
BIAS VCC SW

UVLO FB
RT COMP
SS PGOOD
PGND AGND MODE

Figure 10-4. Typical SEPIC Application

Inducta nce shoul d b e small enoug h
VSUPP LY to o perate in DCM a t ful l loa d VLOAD = 15V - 83V

BIAS VCC SW

UVLO FB
RT COMP From MCU
SS PGO OD
PGND AGND MODE

Figure 10-5. LIDAR Bias Supply 1 (DCM Operation)

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VLOAD = 90V - 249V

Voltage
Tripler

Inducta nce shoul d b e b ig e nough

to o perate in CCM
VSUPP LY

BIAS VCC SW
From MCU
UVLO FB
RT COMP
SS PGO OD
PGND AGND MODE

Figure 10-6. LIDAR Bias Supply 2 (CCM Operation)

VSUPPLY VLOAD

BIAS VCC SW

UVLO FB
RT COMP
SS PGOOD
PGND AGND MODE

Enable Spread Spectrum

Figure 10-7. Low-Cost Single String LED Driver

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VSUPPLY VLOAD = 5V/12V

BIAS SW
UVLO/SYNC
PGND
AGND

PGOOD VCC
MODE

RT

FB SS COMP

Optional Primary-Side
Soft-Start

Figure 10-8. Secondary-Side Regulated Isolated Flyback

VLOAD 2 = +1 2V

VSUPP LY

V LOAD 3 = -8.5V
BIAS SW
UVLO/SYNC
Optiona l DC Coupli ng
Capacitor for Low EMI
AGND Isol ated S epic
PGND
To MCU
System Power PGO OD
MODE VLOAD1 = 3.3V/5V +/-2%
RT
FB
SS COMP VCC

Figure 10-9. Primary-Side Regulated Multiple-Output Isolated Flyback/Isolated SEPIC

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VSUPPLY VLOAD = 5V/12V

BIAS SW
UVLO/SYNC
PGND
AGND
To MCU
System Power PGOOD VCC
MODE

RT

SS COMP FB

Figure 10-10. Typical Non-Isolated Flyback

11 Power Supply Recommendations

The device is designed to operate from a power supply or a battery with a voltage range from 1.5 V to 60 V. The
input power supply must be able to supply the maximum boost supply voltage and handle the maximum input
current at 1.5 V. The impedance of the power supply and battery including cables must be low enough that an
input current transient does not cause an excessive drop. Additional input ceramic capacitors can be required at
the supply input of the converter.

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12 Layout
12.1 Layout Guidelines
The performance of switching converters heavily depends on the quality of the PCB layout. The following
guidelines can help users design a PCB with the best power conversion performance, thermal performance, and
minimize generation of unwanted EMI.
• Put the D1 component on the board first.
• Use a small size ceramic capacitor for COUT.
• Make the switching loop (COUT to D1 to SW to PGND to COUT) as small as possible.
• Leave a copper area near the D1 diode for thermal dissipation.
• Put the CVCC capacitor as near the device as possible between the VCC and PGND pins.
• Connect the COMP pin to the compensation components (RCOMP and CCOMP).
• Connect the CCOMP capacitor to the analog ground trace.
• Connect the AGND pin directly to the analog ground plane. Connect the AGND pin to the RMODE, RUVLOB, RT,
CSS, and RFBB components.
• Add several vias under the exposed pad to help conduct heat away from the device. Connect the vias to a
large ground plane on the bottom layer.

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12.2 Layout Examples

Thermal Dissipation
VSUPPLY GND
Area

VLOAD Do not connect input and output

capacitor grounds underneath the
device

D1

CVIN

LM
COUT2 COUT1
GND
CVIN
PGND

Power Ground Plane

SW
SW
NC

(Connect to EP via PGND pin)

16 15 14 13 Connect to the ground connection of
COUT using inner layer
CVCC PGND 1 12 NC Connect
EP
to VLOAD
2 11 MODE RMODE
VCC
Connect to the ground connection Connect to
of CIN using inner layer VLOAD / BIAS 3 10 SS CSS
RFBT

VSUPPLY
PGOOD 4 9 FB
RFBB
Connect to
pull-up 5 6 7 8
resistor
UVLO

COMP
AGND
RT

RCOMP CCOMP
RT
RUVLOB

Analog Ground Plane

(Connect to EP via AGND pin)
Connect
RUVLOT to
VSUPPLY

Figure 12-1. PCB Layout Example

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13 Device and Documentation Support

13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.1.2 Development Support
For development support see the following:
• LM5157x / LM5158x Boost Quick Start Calculator
• LM5157x / LM5158x Flyback Quick Start Calculator
• LM5157x / LM5158x SEPIC Quick Start Calculator
• How to Design a Boost Converter Using LM5157x / LM5158x
• How to Design an Isolated Flyback Converter Using LM5157x / LM5158x
13.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5158x device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, LM5158Q1EVM-BST User's Guide
• Texas Instruments, LM5158Q1EVM-FLY User's Guide
• Texas Instruments, LM5158Q1EVM-SEPIC User's Guide
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.

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WEBENCH® is a registered trademark of Texas Instruments.

All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

13.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

38 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

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 PACKAGE OPTION ADDENDUM

www.ti.com 7-Apr-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LM51581RTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 L51581 Samples

LM5158RTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LM5158 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 7-Apr-2023

OTHER QUALIFIED VERSIONS OF LM5158, LM51581 :

• Automotive : LM5158-Q1, LM51581-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM51581RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
LM5158RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM51581RTER WQFN RTE 16 3000 367.0 367.0 35.0
LM5158RTER WQFN RTE 16 3000 367.0 367.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RTE 16 WQFN - 0.8 mm max height
3 x 3, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4225944/A

www.ti.com
 PACKAGE OUTLINE
RTE0016C SCALE 3.600
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

3.1 B
A
2.9

PIN 1 INDEX AREA

3.1
2.9

SIDE WALL
METAL THICKNESS
DIM A
OPTION 1 OPTION 2
0.1 0.2
C
0.8 MAX

SEATING PLANE
0.05
0.00 0.08

1.68 0.07 (DIM A) TYP

5 8
EXPOSED
THERMAL PAD
12X 0.5
4
9

4X 17 SYMM
1.5

1
12
0.30
16X
0.18
PIN 1 ID 16 13 0.1 C A B
(OPTIONAL) SYMM
0.05

0.5
16X
0.3

4219117/B 04/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RTE0016C WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 1.68)
SYMM
16 13

16X (0.6)

1
12

16X (0.24)
17 SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4

( 0.2) TYP
VIA

5 8
(R0.05) (0.58) TYP
ALL PAD CORNERS
(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:20X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

EXPOSED EXPOSED
SOLDER MASK METAL METAL UNDER
METAL
OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4219117/B 04/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RTE0016C WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 1.55)
16 13

16X (0.6)

1
12

16X (0.24)

17 SYMM
(2.8)

12X (0.5)

9
4

METAL
ALL AROUND

5 8
SYMM
(R0.05) TYP

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X

4219117/B 04/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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