Control Logic Design NS ae 40-1 INTRODUCTION The process of logic design is a complex undertaking. Many installations develop various computer-automated design techniques to facilitate the design process. However, the specifications for the system and the development of algorithmic procedures for achieving the required data-processing tasks cannot be automated and require the mental reasoning of a. human designer. The most challenging and creative part of the design is the establishment of design objectives and the formulation of algorithms and procedures for achieving the stated objectives. This task requires a considerable amount of experience and ingenuity on the part of the designer. An algorithm is a procedure for obtaining a solution to a problem. A design algorithm is a procedure for implementing the problem with a given piece of equipment. The development of a design algorithm cannot start until the designer is certain of two things. First, the problem at hand must be thoroughly understood. Second, an initial configuration of equipment must be assumed for implementing the procedure. Starting from the problem statement and equipment availability, a solution is then found and an algorithm formed. The algorithm is stated by a finite number of well-defined procedural steps The binary infomation found i. i on Dae memory Tegisters, and it can be either data_or control information. Data are discrete elements of information that are manipulated by microoperations. Control ifomiiion prove 2 ee te fF microopera- tions. The logic design of a digital system is a process for deriving the digital Greuitg that i eat aa BS icesng and the digital circuits that sai fe control signals.) Eta te he ee The timing for all registers in a synchronous digital system is controlled by a 4 generator. The clock pulses are applied to all flip-flops and registers luding the flip-flops and registers in the control unit. (Th continuous clock pulses do ‘not change the state of a register unless the register is 407Ch. 408 CONTROL LOGIC DESIGN 0 ‘ ‘ trol the selecti ‘ enabled by a control signal. The binary td baitie cautel unit. The oxi Se Ee eee abis the datk prosessce part OF te Systert aif also of the control unit select and at a all Sai Pucaniie: Weed vthe ‘cottrol and the data Pe ae digital system is shown in Fig. 10-1£The data_processor Sr a _* 3 ae = Processor unit, or it may consist of, fcpersiaar ia te cate pee functions, )The control initiates all_microoperations in the micr a The control Togic that generates the signals for Cunt : ee 3 iS séquential circuit whose internal states dictate the control encnons 7 beh At any given time, the state of the sequential control initiates a ee set of microoperations. Depending on status conditions or other input , the Sequential control goes to the next state to initiate other microoperations. Thus, the digital circuit that acts as the control logic provides a time sequence of signals for initiating the microopérations in the data-processor part of the system. : The design of a digital system that requires a control sequence starts with the assumption of the availability of timing variables, We designate each timing variable in the sequence by a state and then form a state diagram or an equivalent Tepresentation for the transition between states. Concurrent with the development of the control sequence, we develop a list of microoperations to be initiated for each control state. If the system is too complicated for a state diagram, it may be convenient to specify the system entirely in the Tegister-transfer method by means of control functions and microoperation statements. The control sequence and register-transfer relationships may be derived directly from the word specification of the problem. However, it is sometimes of systems that need a control are A timing diagram clarifies the the various control signals in the sy: timing diagrams and flowcharts. timing sequence and other relationships among stem. In a clocked sequential circuit, the clock External inputs Input data Initiate Control Hoxie Micro-operations Data Processor Status conditions Output data Figure 10.1 Control and data-processor interactionSEC. 10-2 CONTROL ORGANIZATION 409 pulses synchronize all operations, includin, signe itions i ‘ #r an asynchronous aystein, a sigdal ane ignal transitions in control variables. change of another control variable. A. timing dene aiable may cause a asynchronous control because it provides a pictorial savesevat en of vintt changes and transitions of all control variables, Roa sear nc A flowchart is a convenient wat i and decision paths for an algorithm, A flowehan har enn Procedural steps normally use the variable names of registers defined in te intel nines configuration. It translates an algorithm from its word diieineat 40 toe tion-flow diagram that enumerates the sequence of register-transfer operations together with the conditions necessary for their execution. re Wie ae is 4 oem tat Consists of blocks connected by directed lines. “KS, 'y the procedural steps for implementing the algorithm. The directed lines between blocks designate the path to be taken from one procedural step to the next. Two major types of blocks are used: A rectangular block designates a function block within which the microoperations are listed. A diamond-shaped block is a decision block within which is listed a given status condition, A decision block has two or more alternate paths, and the path that is taken depends on the value of the status condition specified within the block. A flowchart is very similar to a state diagram. Each function block in the flowchart is equivalent to a state in the state diagram. The decision block in the flowchart is equivalent to the binary information written along the directed lines that connect two states in a state diagram. As a consequence, it is sometimes convenient to express an algorithm by means of a flowchart from which the control state diagram may be readily derived. In this chapter, we first present four possible configurations for a control unit. The various configurations are presented in block diagram form to emphasize the differences in organization. We then demonstrate the various procedures available for control logic design by going through specific examples. The design of control logic cannot be separated from the algorithmic develop- ment necessary for solving a design problem. Moreover, the control logic is directly related to the data-processor part of the system that it controls. As a consequence, the examples presented in this chapter start with the development of an algorithm for implementing the given problem. The data-processing part of the system is then derived from the stated algorithm. Only after this is done can we Proceed to show the design of the control that sequences the data processor according to the steps specified by the algorithm. 10-2 CONTROL ORGANIZATION Once a control sequence has been established, the sequential system that imple- ™ents the control operations must be designed. Since the control is a sequential Circuit, it can be designed by a sequential logic procedure as outlined in Chapter 6.410 CONTROL LOGIC DESIGN CH. 19 However, in most cases this method is impractical beter ot u umber States_that_the control circuit_may_have. Design pee th ase Slate ang excitation tables can be used in theory, but ‘in practice they mbersome ang difficult to manage. Moreover, the control circuit obtaine Naat ually Tequires an exci flip-flops and gates, w lies the use of sgt circuits, This type of CE nt with esoec lat ae f IC packages used and the num + of wires that mus tere . One major goal of control logic design should be the development of a circuit that implement, the desired control sequence in a logical and straightforward pea oe attempt to minimize the number of circuits would tend to produce an ur s er re Which would make it difficult for anyone but the designer 0 Mt may be Sequence of events that the control undergoes. As a consequence, difficult to service and maintain the equipment when it is in operation. Because of the reasons cited above, experienced logic designers Use special. ized methods for control logic design which may be considered an extension of the classical Sequential-logic method combined with the Tegister-transfer’ method. In this section, we onsidei@our taetnods of control organizations) “TL. One flip-flop per state method. /' Shep ooh te wy u x a eo tlie 2. Sequence register and decoder method. 3. PLA control, 4. Microprogram control, —ctoprogram contro Ge first two methods result in a Circuit that must use SSI and MSI circuits for the impl i '€ various Circuits are interconnected by wires to form the control network control unit implemented With SSI_and MSI devices is said to be a hard-wired GOntrol. If an alterations or modifications are needed, the circus ust be rewired to ull Re ew requirementsYThis is tio PLA of microprogram control whi ich uses an LSI device such as a pro; ble ‘Any alterations or modifications in a micropto- without wiri ing changes by removing the ROM from its socket and inserting another fulfill the new specifi- cations, J We shall now expla of this chapter deal with control units by each of logic array or a read-only memor Sram control can be easily achieved in each method in general terms, The subsequent sections 5] Pecific examples that demonstrate the detailed design of the four methods, One Flip-Flop per State Method This meth MAGS One flip-flop per State j flip-flop is Set at any particut in the control se uential ci 4 all others are cl eared | propagate from one flip-flop io the other uni such an array, each flip-flop, . "epresents a state and is activated only when the control bit is transferred to it) nnn HS activated only when he10-2 Cs CONTROL ORGANIZATION 4 It is obvious that this method des not use a -ninimum number ip for the sequential circuit. In fact, it uses a maximum number of thistle oes example, 2 sequential circuit with 12 states requires 4 ainien of eee flops because 2° < 12 < 2*. Yet by method, the control circuit uses 12 flip-flops, ane for each a * The advantage of the one flip-flop per state method is the simplicity with j)which it can be designed) This type of controll i inspection from the state diagram that describes the control Sequence’) At first glance, it may seem that this method would in nore flip-flops are used, example, it offers a saviitgs in design effort, an increase in operational simplicity, and a potential decrease in the combinational circuits Tequired to implement the Figure 10-2 shows the configuration of a four-state sequential control logic that uses four D-type flip-flops: one flip-flop per state T,, i =0, 1, 2,3. At any | Other control outputs - To . x External input j conditions 4 tr j pte = ty cP Figure 104 Geos logic with one flip-flop per state) i.412 CONTROL LOGIC DESIGN Chg iven time i etween two clock pulses, only ee Reet to L others ime The transition from the present state to the next isa ‘nena Of the present 7, that ve and cain pot sondions] The next ty i manifested when the previous fip-lop js-clenzed.and a new one is ef] Each of the flip-flop outputs is connected to the data-processing. section of the Bt ten tj initiate certain microoperations) The other control outputs shown in the agram Sand external inputs. These outputs may also injijay are a function o1 microoperations. f é 3 If the control circuit does not need external inputs for its sequencing, the circuit reduces to a straight shift register with a single bit shifted from one POsition to the next. If the control _sequi ated Over and over again, the control reduces to a ring counter. A ring counter is a shift register with the ou tput t_of the first flip-flop. In_a ring counter, of the last flip-flop connected to the input : the single bit inuously shifts from one position to the next in a circular manner For this reagon, the one flipflop per state method is sometimes called a ring-cour fer controller, Sequence Register and Decoder Method is method uses a register to sequence the control state: e_Tegister is decoded to provide one output for each statg) For n flip-flops in the sequence. register, the circuit will hav states and the decoder will have 2” outputs. For example, a 4-bit register can be in any oné of 16 states. A 4.x 16 decoder will have 16 outputs, one for each state of the register. Both the sequence register and decoder are MSI devices. Other control outputs External input conditions Decision logic Sequence register Present state Control logic with sequence register and decoderSEC. 10-2 CONTROL ORGANIZATION = 413 Figure 10-3 shows the configuration of a four-state sequential control logic. The sequence register has two flip-flops and the decoder establishes separate outputs for each ‘state in the register. The transition to the next state in the sequence register is a function of the present state and the external input condi- tions. Since the outputs of the decoder are available anyway, it is convenient to use them as present-state variables rather than use the direct flip-flop outputs.Other outputs which are a function of the present state and jay imtiate microoperations in addition to the decoder outputs. the control circuit of Fig. 10-3 does not need external inputs, the sequence register reduces to a counter that continuously sequences through the four states. For this reason, this method is sometimes called a counter-decoder method. The counter-decoder method and the ring-counter method were explained in Chapter 7 in conjunction with Fig. 7-22. \ ae tee PLA Control The programmable logic array was introduced in Section 5-8. It was shown there that the(PLA is an LSI device that can im t_any_ comple) ination circuit) The RLA control is essentially similar to the sequence register afid decoder method except that all combinational circuits are implement a PLA, including the decoder and the decision logig| By using a PLA for the combina- tional circuit, it is possible to reduce the number of ICs and the number of interconnection wires. Figure 10-4 shows the configuration of a PLA conttoller.An_external sequence regis ishes_the present state of the control cifcuit. The PLA outputs determin h_microoperati ti ex- ternal input Conditions the present state of the sequence register) At the same time, other PLA outputs determine the next state of the sequence regi ste The sequence register is external to the PLA if the unit implements_only combinational circuits) However, some PLAs are available which include not only Initiate micro- operations External input conditions ‘ Sequence register Figure 10-4 PLA control logichy, 414 CONTROL LOGIC DESIGN is ithil This type of PLA can implemen, ip-flops within the unit, p : me i spealtying the links that a be connected to the flip-flops in se ys : ; ry same manner that the gate links are specile Microprogram Control @he purpose of the control unit is to ne A scies ot egw ey a - eT ‘al ia cl 8 ring any given_time, certain operal e D aie a eee ‘ale. Thu the control variables at any sven time can be represented by a string of I's and 0’ called a controT word.) As ae ¥ Control words can be programmed to initiate the various components in the system in gy organized manner. A control unit whose control variables are stored in a me is called a microprogrammed control uni) Each control word of memory is called 2 microinstruction, and a sequence of microinstructions is called a microprogran?) Since alteration of the microprogram is seldom needed, the control memory can be a ROM The use of a microprogram involves placing all control variables in words of the ROM for use by the control unit through successive read operations. The content of the word in the ROM at a given address specifies the microoperations for the system. i : A more advanced development known as dynamic microprogramming per- mits a microprogram to be loaded initially from the computer console or from an auxiliary memory such as a magnetic disk. Control units that use dynamic micro Programming employ a writable control memory (WCM). This type of-memory can be used for writing (to change the microprogram) but is used mostly for reading. A ROM, PLA, or WCM, when used in a control unit, is referred to as a conirol mene igure 10-5 illustrates the general configuration of the microy rogram control unit. The control_memory is ass to be a ROM, within which soit which all_caatrol information is permanentiy stort Ue ono meny address register specifies the control word read from control memory. be realized that-= KOM C n It must be realized that a (erates as a combinational circuit, with the address valué as the Tapa and the corresponding word as the output)The cOnteAT OT THE Specified word yemuains on the output wires as long as the address value reining ie the address register2No read signal is needed as in should be transfei rred to a buffer rey ROM word is stil in uses TF a) $ still Tf the cha simultaneously, no but er register is needed, je word read from control memor microinstruction specifies one or more microoperations for the components of the system, Once these operations are executed, the control unit must determine its next address, The location of the next microinstruction may be the next one in Feaencts OF it may be located somewhere else in the control memory. For this Feason, it is Necessary to use some bils of the Microinstruction to control the generation of the address for the h NeXt microinstruction. ‘The next address may alsoextemal 4 Initiate ‘opt —"7 Next Control Control micto- conditions address, address memory operations renerator register (ROM) Next address information Figure 10-5 Microprogram control logic be a function of external tions. While the microoperations are being executed, the next address is computed in the next-address generator circuit and then transferred (with the next clock pulse) into the control address register to read the next microinstruction, The detailed construction of the next address generator depends on the particular application. The remainder of this chapter deals with specific examples of control logic design. The first example in Section 10-3 demonstrates the one flip-flop per state method, and Section 10-4 presents the same example with a microprogram control. Section 10-6 uses a second example to demonstrate the sequence register and decoder method, and Section 10-7 implements the second example with a PLA. Sections 10-5 and 10-8 consider the microprogram control method in more detail. 40-3 HARD-WIRED CONTROL—EXAMPLE 1 This example demonstrates the development of a design algorithm. We start from the statement of the problem and proceed through the design to obtain the control logic for the system. The design is carried out in five consecutive steps. V1. The problem is stated. >. An initial equipment configuration is assumed, 3. An algofithm is formulated. 4, The data-processor part is specified. 5, The control logic is designed. — |v secu x G> initia equipment configuration is necessary in order to formulate the design algorithm in terms of the register-transfer meth ie algori s lated by means of a flowc] cifies the sequence of microoperations for the system. Once we have a Tist_of microoperations, we can_choose_the- digital functions necessary for their implementation, In essence, 1 is supplies the data-processor part of the system,) The control is,then-designed to sequence the re juired mictoop- erations in the data processor. 415416 — CONTROL LOGIC DESIGN Ot r i ign’ is a hard-wit The control logic. derived in ia ac Fe fied contd of he 4 flip-flop per state ‘metifod,) ie digital system ee : bed . ample of mi am contro] the Next section to demonstrate an ex: micto} OF Statement of the Problem -! algorithm was stated for the addition and subtraction of bi tired pie ie ‘when negative numbers are in sign-2's-complement form} problem here is to implement with hardware the addition and subtraction of ty. fixed-point_binary numbers represented _in_sij n-magy jitude fe anthmetic m: ised, provided the final result is in sign-magnitude form) 1¢, addition of two numbers stored in registers of Fini en; Tesult in Possible overflow bit. Equipment Configuration Ge two signed binary numbers to be added or subtracted contai n bits. The nitud e numbers contain k = n— | bits and are stored in registers 4 ind Bie ge as ce A m= Lis ps A, and B,. Figure 10-6 shows ie Tegisters and associated equipment. (The ALU performs the arithmetic operations ‘and the T-bit register E serves as the overflow flip-flop) The output carry from the ALU is transferred to EF. aa paar It is assumed that the two numbers and their signs have been transferred to their respective registers and that the result of the operation is to be available in registers A and_A,,)Two input signals in the control specify the add_(¢,) and suOTat gy ope erations. Output variable x in cates the end of the operation. The control logic communicates with the outside environment through the input and output variables, Control recognizes input Signal g, or g, and provides the required epee EE a OF 4, and provides the require Magnitude Sign Overflow X (Operation terminated), Figure 10. aaah) \ Control Subtract) logie en © Register configuration for the adder-subtractorSEC. 10-3 HARD-WIRED CONTROL—EXAMPLE1 417 operation: Upon completion of the operation, control informs the external. en- vironment with output x that the sum or difference is in registers A ‘id that | the overflow bit is in E. sisters A and A, arid that Derivation of the Algorithm ‘The representation of numbers by sign-magnitude is familiar because it is used for paper and pencil arithmetic calculations. The procedure for adding or subtracting, two signed binary numbers with paper and pencil is simple and straightforward. A review of this procedure will be helpful for deriving the design algorithm. We designate the magnitude of the two numbers by A and B. When the numbers are added or subtracted algebraically, we find that there are eight different conditions to consider, depending on the sign of the numbers and the operation performed. The eight conditions may be expressed in a compact form as follows: [(@4) + (=B)| If the arithmetic operation specified is subtraction, we change the sign of B and add. This is evident from the relations: (+4) — (+B) = (+4) + (-8) (#4) — (-B) = (44) + (+8) This reduces the number of possible conditions to four, namely: (+4) + (+8) When the signs of A and B are the same, We add the two magnitudes and the sign of the result is the same as the common sign) When the signs of A and B are not the same, we subiract ‘he smaller number from the larger the sign of the result is the sign of the larger number, This is evident from the following relationships: ifA>B ifA B and the number in A is result again is equal to the original value of 4,, A ) ee this case, it is s_necessary To om the 2's com le nd | copplement_t te sg ign in A, 's complement of ie wit a | microoperation, A— A+ 1, Hbweher, we want to use the ALU of Chapter 9 aa ani this ALU does not havet the 2's complement ip) operation. For this reason, the 2’s 2s complement is obtained from the | eeable in the-ALU————--ement and inerement operations which are ALU (Table 9-4) A register L (Load) (a) Data processor registers and ALU x (Initial state) 5 (Mode select) 5, (Function select) so Control Tose Cjq (Input carry) L (Load A aid E from ALU) » (Complement B,) z (Complement A,) w (Clear#) (b) Control block diagram Figure 10-8 System block diagramData Processor Specification The flowchart algorithm lists all the microoperations a ihe Ne ea Part of the system. The operations between A and B can te eae contd U, operations with 4,, B,, and E must be initiated wi et echoes atiables, Figure 10-8(a) shows the dataprooessor_with the required control variables, K mentioned before, the ALU is from Chapter 9 and its function is specified in Table 9-4. (This ALU has four selection variables, as shown in the diagram. The Variable L loads the output of the ALU into register A and aso the output carry into E Variables y, z, and w complement B, and A, and clear E, sespective) 5 The block diagram of the control logic is shown in Fig. 10-8(b). The coy ol receives five inputs: two_from the external environment and three from the data-processor. To simplify the design, we define a new variable SY (G=458) This variable gives the result of the comparison between the two sign bits, The exclusive-OR operation is equal to 1 if the two signs are not the same, and it is equal to 0 if the signs are both positive or both negative. The control provides an output _x for the external circuit. It also selects the operations in the ALU through the four selection variables s,, s,, 5g, and Ca. The other four outputs go to registers in the data-processor as specified in the diagram. Although not shown in the diagram, the outputs of the control logic should be connected to the corresponding inputs in the data-processor) Now that the data- Processor is specified, we can design the control logic for the system. Control State Diagram The design of a hard-wired control is a sequential-logic problem. As such, it may be convenient to formulate the state diagram of the sequential control. he function boxes in a flowchart may be consider tates of the sequential circuit, and the decision boxes as next-state conditions, next-state le microoperations that must, be executed at a given state are specified wit in the function boxy Phe conditions for the next state transition are specified inside the decision box or in the directed lines bétween two function boxes) ATi ough one can formulate this relationship between a Towehart aid-a state agram, the conversion from one f ‘orm to the other is not unique, Consequently, different designers may produce diff ferent state diagrams for the same flowchart, and each may be a correct Tepresentation of the system. We start by assigning(an initial state, 7, sequential controller. We then determine the transition 10 other states 1» Ty, Ty arid 80 on.) For each state, we determine the microoperations that Tat be dniated Rae et nah This procedure produces the state di lor the controller, together with a list of register-transfer operations which are to be initiated while the control circuit is in each and every stajé,) re Cae ere eee (The control state diagram and are derived it Fig. 10 420Add Subtract ‘Signs unlike Output carry (a) State diagram Control outnit BER) Bye By Cee Linays ; & [ew Tp: Initial state x = 1 100000000 % T,:B, +B, 00000010 0 4 T,: nothing _ 000000000 8 T; 0 00101 00 0 Sot O20" at T Yr? 0 08 0 so Ts: E+0 0000000041 Ww Ty: ACA 0 1 1 4:0 1 0 0.0 SSL Ty:A+A +1, 4,04, 00 0 0 1 1 0 1 oO bee (b) Sequence of register transfers Figure 10-9 Control state diagram and sequence of microoperationsCH. 422 CONTROL LOGIC DESIGN flowchart of Fig. 10-7 and the variables defined in the block diagram of Fig 10g lowchar! . 10 is in this state, variable x j, fp ile the control is in a is m, ‘The initial control state is Tp. ve other states. As long as q, and q, are Qy is variable is 0 in al I pertornis ¢ t aval aie ta initial state. If g, becomes 1, a ees bc by oing to state 7). In this state, sign A jemtet es ro} ‘heh Eo shane T, to add the two numbers. If g, becomes 1, goes direc ge lative values of the sign bits ends on the relati 4 f Which eA Ra Tou bls S. If the signs are alike, S is 0 and contro} Boes determined from input val : . to state T,, In this state, the two magnitudes are added and the overflow bit se Once this is done, control goes back to the initial state. If i sone are unlike, Sis 1 and control goes from state 7; to state Ty. In this ae the Ce ate subtracted by taking the 2’s eo de eek scarry is transferred to ¢ ion, and control then goe: 52 aime Pe rele that the end carry from the ALU is transferred to E with a clock pulse. This happens with the same clock pulse that causes the control to fo from state T, to T;. Although we show the microoperation: EoeCun with timing variable T, this operation is not executed until a clock pulse occurs. Once this clock pulse executes the operation, control finds itself in state T,, Therefore, the value of E for an end carry should not be checked until control teaches state T;./The value of E is checked to determine the relative magnitudes of A and B. If E =, it indicates that A > B. For this case, E must be cleared and the operation is completed. If E = 0, it indicates that A < B. Control then goes to states T, and T; to complement A and 4,,) Note that E is cleared while the control is in state Ts. This is done whether E is 1 or 0, since trying to clear a flip-flop that is already 0 leaves the flip-flop in the 0 state anyway. Note also that E is cleared with the clock pulse that causes control to go out of state T;. It must be realized that clearing E and transferring control to state Tp or Te is done with one common clock pulse without a conflict, The original value of E at time T; determines the next state even though this flip-flop is cleared while the clock Pulse goes through an edge transition, It should be apparent from this example that the interpretation of a flowchart may result in a different state diagram forsthe same control logic, This is accept- able as long as the hardware constraints are taken into consideration and the system functions according to the specifications, For example, instead of checking E at time Tove sould have chosen to check Cy. at time Ty. If Coy is 1, control Boes to state T; to clear E. If it is 0, control ca irec % ssi Sie Tite ace n Bo directly to state 7, bypassing Design of Hard-wired Control Ge control outputs are afunction of the control states and are listed in Fig -9(b). These outputs are defined in the bloe f Fig. 10-8(b). The 4 J values for the ALU selection variables are determined from Table 9-4, The L (loaseC. 10-3 HARD-WIRED CONTROL—EXAMPLE 1 423 4) variable must be made equal to | every time the output of the ALU is transfer to register, itherwise, L is‘ and the ‘outputs have no effecton the register] To desigh the control for this system, we need to design the state Hhagram o} ig. 10-9(a) and provide the control outputs as specified in Fig. 10-9(b). ‘The control can be designed using the classical sequential-logic procedure. Ti Sie etal oe sate abe with igi ses, Fr ipa a four inputs, and nine outputs} The sequential circuit to be derived from such a state table will not be casy (0 obiain because of the large number of variables. The circuit obtained by using this method may have a minimum number of gates, but it will have an irregular pattern and will be difficult to analyze if a malfunction occurs. These diietdes are removed if the control is designed by the one flip-flop per state ethos Pig aan @ control organization that uses one flip-flop per state has the convenient characteristic that the circuit can be derived directly trom the state di by inspection:XNo state or excitation tables are needed if D flip-flops are employs ‘emember that the next state of a D flip-flop is a function of the D input and is independent of the present state. Since(the method requires one flip-flop for each state, we choose eight D flip-flops and label their outputs Ty, 7, Ty .- +) Ty. The condition for setting “a given Miptlop is specified in the state diagram) For example, flip-flop T; is set with the Ted see puse 7,21 oF Ty = 1 and q, = 1. This condition-can bé defined with the Boolean function: DT = qT) + Ty where DT; designates the D input of flip-flop 7) In fact, the condition for setting a flip-flop to | is obtained from the condition specified in the directed lines going into a given flip-flop state ANDed with the previous flip-flop state. If there is more than one directed line going into a state, all conditions must be ORed. Using this procedure for the other flip-flops, we obtain the input functions given in Table 10-1. Initially, flip-flop Ty is set and all others are cleared. At any given time, only one D input is in the 1 state while all others are maintained at 0. The next clock pulse sets the flip-flop whose D input is 1 and clears all others. For example, if ‘TaBLe 10-1 Boolean functions for control Flip-flop input functions Boolean functions for output control G,4;To + Ts) + ETs+ Tr x=T 4To n= Ts DT, = To + Ti = T+ Ts DT; = S'T; 52 Ty T DT, = ST; =T,+ ty DI5= Ts L= T+ Ty+ Tot Tr DT, = E'Ts yen DT, = Ts a z=7; wasCH. 1g ESIGN : 424 CONTROL LOGIC OF phate ial tea eaaheges ita, <0 and d = Ot ving the interval between two Pulses presently Ty = |. ae oe ate. 1 SUF Ne TD input of 7 wil be | gents acl the D inp of To will jah "r _ The flip-flop input functions are adem ke Piet 7 and et ata any B= time al oh - . iy one flip mutually exclusive and only is are O'8. Z are cleared because their pi fyruhe control outputs as Se 1G of ftp How p states, ve now sl f oe rn use he Dna ee Ny orca Lp ae i ‘rom Fig. a Functions are obtained BY NSPE? Tose variables are available from Outputs or i ee oat is necded here is a 4-input OR gate to generate output contro} of flip-flops. wn but can be easily obtained from : is not dra' et The circuit for the contre ee is creuit can be constru cted with eight D < in Tabl c a eas ied TAND gates, six OR gates, and four inverters. Note that five control outputs are taken directly from the flip-flop outputs. 10-4 MICROPROGRAM CONTROL rogram control, the co) variables that initi 2 are apes mory is usually a ROM, since trol stored_in_memory. The control_met n c sequence is permanent eds no alteration) The control variables stored in memory afé read one at a time to initiate the sequence of microoperations for the systerh, ¢ words stored in a control memory are_microi 101 each microinstruction specifies one or more microoperations for the components in the system. Once these microoperations are executed, the control unit must’ determine its next address, Therefore, a few bits of the microinstruction are to control the generation of the address for the nex! tion. Thus, a microinstruc- tion Contains bits for initiating microoperations and bits that b next address for the control i ee “Ip addilion to the contol menc, A i i in addition to the control memory, a microprogram control unit must include special circuits for seleting the next address as § yy the microinstructi ide circuits and the configuration of the microinstruction bits stored in memory od rom Nest unit to another. Instead of dwelling on all the possibilities encoun- tered in different situations, we choose here to introduce the microprogram pear by means of a simple example, 1 control logic signed i logic to be designed is for the sign-magnitude adder-subtractor developed in the previous secti i Srerepes i spe seein ‘The hard-wired control designed in Section 10-3 however, that the digi ayRtemr-eorseh to be designed subsequently. Realize; controller and, in practice, a hard-wired fu 48 (00 small for a microprogram ‘ m4 ‘ontrol would be ici The microprogram contro! i more efficient. a eT ole yareanicalin, 4s more efficient in large, complicated systems- i ry is represented = — tion. An address for yy the address ‘oinstruc- a SonlroT Memory species a control word witkin-3 mieroi?-SEC. 10-4 MICROPROGRAM CONTROL 425 struction, just as a state in_a sequential circuit specifies a_microoperation. The control we wish, to design is specified in Fig, 10-9. Since there are eight states in the control, we choose a control memory with eight words having addresses 0 through 7. The address of the control memory corresponds to the subscript number under the 7’s in the state diagram. Inspection of the state diagram reveals that the address sequencing in the microprogram control must have the following capabilities. 1. Provision for loading an external address as a result of the occurrence of external signals q, and q,. 2. Provision for sequencing consecutive addresses. 3, Provision for choosing between two addresses as a function of present values of the status variables S and E. Each microinstruction must contain a number of bits to specify the way that the next address is to be selected. Hardware Configuration control memory is an 8-word by 14-bit ROM. tion word contain the control variables that initiate the microoperations. The last five bits provide information for selecting the next address. The control address Tegister (CAR) holds the address for the control memory. This register receives an input value when its load control is enabled; otherwise, it is incremented by 1. is essentially a counter with paralle-load capability.) Gis io. mad 2 ‘of a microinstruction contain an address for CAR. Bits 13 .d 14 select an input for a multiplexer. Bit 1 provides the initial state condition fected by variable x and also enables an external address when g, or g, is equal 46.1] We stipulate that when x = 1. the address field of the microinstruction must be 000, Then if g, = 1, address 001 is available at the inputs of CAR, but if q, = 1, ress 010 is applied to CAR,JIf both q, and g, are 0's, the zero address from bits 10, 11, and 12 are applied to the inputs of CAR. In this way, the control memory Stays at address zero until an external variable is enabled. Id te noe eno has four inputs that are selected with bits 13 and 14 f the microinstruction\The functions of the multiplexer select bits are tabulated in Fig. 10-10. If bits 13 and 14 are 00, a multiplexer input that is equal to 0 is Selected. The output of the multiplexer is 0, and tenement To CAR is epabled. This configuration increments CAR to thoose the next_address in sequence. An input of | is selected by the multiplexer when bits 13 and 14 are equal to OL The Supt lanier lin "AR. Status variable Sig selected when bits 13 and 14 are equal to 10. If $ = 1, tte output of the multiplexer is | and the address bits of the microinstruction are loaded into CAR (provided x = 0). If S = 0, the, ut of the multiplexer is 0 and CARs incremented. With bits 13 and 14 equal to 11, status variable E is selectedregister (CAR) Control address Increment Load input MUX select function 13 14 0 0 Increment CAR Oar Ah te pO CAR k 1 0 oad input to CAR ii 1, increment CAR ifs = I 1 oad inputs to CAR if B= 1, increment CAR if E=0 Figure 10:10 Microprograni control block diagram‘SEC. 10-4 MICROPROGRAM CONTROL. 427 and the address field is londed_into CAR if{ = 1, but. CAR /is incremented jif E = 0. Thus, the multiplexer allows the contr(l-to choose between two addres depending on the value of the status bit select 27> cnt 2 SY The Microprogram oa nce the configuration of a microprogram control unit is established, the designer’s task is to generate the microcode 9 1 for the control memory, This code generation is called microprogramming and is a rocess that determines the bit configuration for each gad all words in contol memory|Tosppecat Wi poo we wl derive the microprogram Tor the adder-subtractor example. The control memory has eight words and each word contains 14 bits, To microprogram the control memory, we must determine the bit values of each of the ei it words, e register-transfer method can be adopted for developing a microprogram) The microoperation sequence can be Specified with register-transfer statements. There is no need for listing control functions with Boolean variables since, in this case, the control variables are the control words stored in control memory. Instead of a control function, we specify an address with each register-transfer statement. The address associated with each symbolic statement corresponds to the address where the microinstruction is to be stored in memory. (The sequencing from one address to the next can be indicated by means of conditional control statements: status Conditions.) Thus, instead of thinking in terms of the I's and O's that miist be inserted for each microinstruction, it is more convenient to think in terms of symbols in the register-transfer method, Once the symbolic microprogram is established, it is possible to translate the register-transfer statements to their equivalent binary form. The microprogram in symbolic form is given in Table 10-2. The eight addresses of the ROM. are listed in the first column. In the second column, the microinstruction that must be stored at each address is given in symbolic form. Taste 10-2 Symbolic microprogram for control memory ROM address Microinstruction Comments 0 x = 1, if(g, = 1) then (go to 1), if (ga = 1) Load 0 or external address then (20 TD, if (GA qa =9 then (go to.) 1 B,— B,, 4, = |, start subtraction 2 If(S = 1) then (go to. = T, start addition 3° TE pees | to Aadwagaitvs and return, A ACAFB HER Cu Subtract magnitudes 5 Mf (E = 1) then(go to 0), £0 Operation terminated if F = 1 “6 AeA i E = 0, complement 4 T AeA+1,4,—A,,B0 100 Done, return to address’428 CONTROL LOGIC DESIGN The start ister-transfer_statey ent: xd to clarify the regis oo ¢ comments are used 10 clarify the register-transfer statements, 4 : a) al state and produces an_output x = 1. The Next aq,0i equivalent to ne initial ernal variables ¢, and 1. The three ig et depends on the ion Use a go fo statement after the wee taLeangt ‘interpreted to mean that if the condition is satisfied Control goes to the” Thi is Tnerpretedto_me 0 f0,) Thus, if both q, and g, are 0, Control stays in adr Oto repeat the microinstruction. If q, or 4, SSL control goes to address on ieee ie conditional control statements in the other microinstructions Use ty status variables_S_and_£. The go to statement without_a condition at he specifies an unconditional branch Papen adress For example gt means that control goes to address 0 after the Present tt microinstruction ig xecutey If there is no go to statement in the muicroinstruct tion, it implies that in the microinstruction, : 7 microinstruction is taken from the next address in Sequence. Also, the oo. qu after an if sta Control goes to the next addres; e $i Sequence The microinstructions associated with the eight addresses are lem ety from the control specifications of Fig. 10-9. The microoperations listed are identi. cal to the ones listed in Fig. 10-9(b). The conditional control statement SPecifies the address sequence as given by the state diagram of Fig. 10- address number is the same as the subseri the 7”s in the state diagram. It should be obvious that the i different way to specify a state diagram. Thi hay nient method for developing the micro way that people e, lopi that the microprogram ig nore oo a ensetsand. But this ‘Knot the way i rol The symbolic microprogram tenanone nated ‘o binary Because this is the form that goes into memory. The tional parts called 2,8 °idine the bits oF cach microinstruction into their func Specify the coy re we have three func tional parts. Bits | through 9 T initiating the mi. ¥ 2 Specify an address field and bs «_mictooperations, Bits 10 through microinstruction listeq in embers and 14 Select a multiplexer input, }For each the corresponding Microinstruction fey” ‘ai’ “e must choose the appropriate bits it The equivalent bins tn Field AN se aa EE iven in Table 10-3. The inary. The content ofTame 103 Binary mieroprogram for control memory R non = OM outputs address |* "2 51 % Cn Ly z w Address Select Wer oa 4 pS no 8 9, on 12 1314 900/10 00 00009 > 2 09 Ot/0 000 0 0 + 9 Heed O41 021 0700207 0: KD HOH Hod o 100 1 0 911/00 01 0 1090 0 0 0 0-31 100/050 1001. 1 0-000 15.0% 1 01 1901/0000 0 90004 000 11 110/01 11 0 1009 1 tishesd 01 '11/0 0001 10106 QO. 0, ool word of ROM is also given in binary. This table constitutes the truth table needed for progré ampltg the OME The first nine bits in each ROM word give the control word that initiates the specified_microoperations) These bit values are taken directly from Fig. 10-9(b). The last five bits in each ROM word are derived from the conditional cgntrol statements in the symbolic program] At address 000, we have 01 for the select field. This allows an external address to_be loaded into CAR if g, or g, is equal to 4 Otherwise, address 00 is transferred to CAR) In address 001, the microinstruction select field is 01 and the address field is 010.) From the table in Fig. 10-10, we find that the clock pulse that initiates thé microoperation B, — B, (because y= 1) also transfers the address field into CAR. The next microinstruction out of ROM yall be the one stored in address 010. The select field at address 001 could have been chosen to be 00. This would have caused CAR to increment and go to address 010. Inspection of the select field in bits 13 and 14 shows that when these two bits are equal to Ol, the address field is the next address, When these two bits are 10, Status variable S is selected, and when they are II, status variable £ is selected, In the last two cases, the next address is the one specified in the address field if the selected status bit is equal to 1. If the selected status bit is equal to 0, the next address is the one next in sequence because CAR is incremented. 10-5 CONTROL OF PROCESSOR UNIT The hardware configuration of the microprogram control unit used in the preced- ing section is suitable for the particular example considered. In a practical situa- tion, the hardware organization of a microprogram control unit must have a Yai