Registration No :
109
Total 109 109
Number of Pages : 02 109 109 109 109
B.Tech109
PEE3I102/PEI3I101/PEL3I102/PET3I101
3rd Semester Back Examination : 2021-22
ANALOG ELECTRONICS CIRCUITS
BRANCH(S): ELECTRICAL, AEIE, EEE, ECE & ETC
Time : 3 Hour
109 109 109 109 Max Marks109
: 100 109 109 109
Q.Code : OF567
Answer Question No.1 (Part-1) which is compulsory, any eight from Part-II and any two
from Part-III.
The figures in the right hand margin indicate marks.
Part-I
109
Q1 109
Answer the109following questions
109
: 109 109 109
(2×10) 109
a) Draw the load line for the self-bias circuit where RC =4.5K, RE =5.5K, VCC=20V.
b) Why FET is a voltage controlled device?
c) Why common-collector circuit is called Emitter-Follower circuit ? What is the phase
difference between input & output ?
d) What do you mean by small-signal analysis? Draw the AC Equivalent model for
FET.
e) Draw the Transfer-curve characterstics & Drain characterstics for p-channel
109 109 DMOS. 109 109 109 109 109 109
f) Draw a unity follower circuit & why it called so ?
g) Write only the principle of operation of a crystal oscillator.
h) Draw the topology of different feedback circuits.
i) What is virtual ground & virtual circuit in op-amp.
j) Draw a current mirror circuit.
Part-II
109 Q2 109 Short Answer
109 Type Questions-
109 (Answer Any 109 Eight out of109 Twelve) 109 (6×8) 109
a) Design a self bias circuit where ICQ=0.5 IC(sat ) , IC(sat) =8mA , VC = 18v , β=110 ,
VCC=28V.
b) Derive the voltage gain of a common source configuration with self bias bypass
system.
c)
109 109 109 109 109 109 109 109
109 109 109 109 109 109 109 109
Determine gm & rd in the given fig. where
VGSQ=0.35v , IDQ=7.6mA , IDSS=6mA, Vp= -3v , y=10µS
109 109 109 109 109 109 109 109
d) Determine VGSQ , IDQ , VD for a voltage divider bias circuit, where R1=2.1MΩ ,
R2=270KΩ , RD=2.4KΩ , RS =1.5KΩ ,VDD=16v , IDSS=8mA , VP= - 4V.
109 109
e) Derive Output 109Impedance & 109
Voltage Gain for109
emitter-follower 109 109
circuit using hybrid 109
model.
f) Explain the working of E-MOSFET with required diagram.
g) If an amplifier with gain of -1000 and feedback of β= -0.1 has gain change of 20%
due to temperature variation, calculate the change in gain of the feedback
amplifier.
h) What do mean by stabilization? Determine the stability factor of voltage-divider
bias circuit.
109 109 109 109 109 109 109 109
i) Draw a subtractor circuit using op-amp & determine its output.
j) For a fixed bias circuit RB=470KΩ , RC=3KΩ , β=100 ,VCC=12V , RS=0.3KΩ,
RL=4.7KΩ, Cb=2µF, Cc=4µF. Draw the complete circuit & find out its overall voltage
gain.
k)
109 109 109 109 109 109 109 109
Find Vo in the above circuit.
109
l)
109
Find the low109
frequency response
109
of a BJT amplifier.
109 109 109 109
Part-III
Long Answer Type Questions (Answer Any Two out of Four)
Q3 Determine Zi , Zo , Av , Ai for a voltage-divider BJT circuit where R1=56KΩ , (16)
R2=8.2KΩ, RC=6.8KΩ , RE=1.5KΩ ,Vcc=22v, β=90 ,Cb=Cc=10µF. (Consider the
Unbypass system where ro =∞).
109 Q4 109 Explain the 109
a) 109
operation of a RC-phase 109
shift oscillator & derive109 109
its output frequency, (10) 109
also how that how Barkhausen condition is satisfied?
b) Design an Adder Circuit using op-amp, where its output VO = -(V1+2V2+3V3) with (6)
Rf =20kΩ .
Q5 What is Darlington connection? Draw its complete small signal model and derive (16)
its voltage gain. And write its application.
109 109 109 109 109 109 109 109
Q6 Draw a gain versus frequency plot for high frequency analysis of a R-C network. (16)
Define 3dB cut-off frequency & show in the plot.
109 109 109 109 109 109 109 109
109 109 109 109 109 109 109 109
