SKEL 4273

CAD with HDL

Modeling Sequential Hardware with

Verilog

Mun’im Zabidi ([email protected])

School of Electrical Engineering
Universiti Teknologi Malaysia
Overview of Sequential Logic

▪ Synchronous sequential logic circuits rely on storage elements for their operations.
▪ One-bit storage elements.
▸ Latches
▸ Flips-flops (FFs)
▪ Multibit
▸ Registers
▸ Shift registers
▸ Counters.
▪ Only synchronous sequential logic is considered.

2
Latches, Flip-Flops

▪ A latch is a level-sensitive memory device (transparent).

▸ As long as the pulse remains at the active high level, any changes in the data input will
change the state of the latch.
▪ A flip-flop (FF) is an edge-triggered memory device.
▪ An edge-triggered FF ignores the pulse while it is at a constant level (non-
transparent).
▸ Triggers only during a transition of the clock signal.
▸ Could on the positive edge of the clock (posedge), or negative edge (negedge).

CAD with HDL 3

D Latch
module latch (
input EN, D,
output reg Q
);
always @ (EN, D)
if (EN)
Q = D;
endmodule

4
Mux à Latch?

reg f; reg f;
always @ (sel, a, b) always @ (sel or a or b)
begin : if_else begin : pure_if
if (sel == 1) f = b;
f = a; if (sel == 1)
else f = a;
f = b; end
end

▪ if-else ▪ Simple if
Incomplete Assignment

reg f;
always @ (sel, a)
begin : latching_if
if (sel == 1)
f = a;
end

▪ A latch is inferred because the IF statement is incomplete.

▪ The notion of implied memory is instantiated in this case.
Signal edge detection

▪ The always blocks are sensitiveto the levels of the signals that appear in the
sensitivity list.

▪ FF changes only as a result of a clock transition of the clock signal, rather than its
level.

▪ Verilog uses event qualifier posedge and negedge

▪ e.g.,
always @ (posedge clock)
Signal edge detection

▪ To recognize 0-to-1 transition

always @ (posedge clock)

▪ If the clock is positive-edge triggered and reset is active-low:

always @ (posedge clock, negedge reset)

Mixed Sensitivity

▪ Synthesis tools do not support mixed sensitivity (combined edge

triggered and level), for example:

always @ (posedge clock, reset)

▪ Should be written as :

always @ (posedge clock, negedge reset)

CAD with HDL 9

Basic positive-edge triggered D flip-flop

module DFF (
input CLK, D,
output reg Q );

always @ (posedge CLK)

Q <= D ;
endmodule

10
Negative-edge triggered D flip-flop

module FF (
input CLK, d,
output reg q ) ;
d D
always @ (negedge CLK) f/f Q q
q = d ; CLK
endmodule
D flip-flop

clk

Q (+ve Flip-flop)

Q (-ve Flip-flop)
Blocking Assignments
module shiftregY (
▪ In a sequential block, input D, clk ,
blocking assignment output reg A, B,
statements (=) are C ) ;
evaluated immediately in
the order they are always @ (posedge clk)
specified. begin
C = D ;
▪ Called blocked B = C ;
assignments because a A = B ;
end
statement must complete endmodule
execution (i.e. update
memory) before the next
statement can execute.
D A
d q

clk
Non-blocking assignment

▪ A non-blocking assignment module shiftregY (

(<=) is called a concurrent input D, clk ,
procedural assignment. output reg A, B, C ) ;

▪ Allows scheduling of always @ (posedge clk)

assignments without blocking begin
execution of the next C <= D ;
B <= C ;
statements. A <= B ;
▪ Order has no effect. end
endmodule
▪ Results of each non-blocking
statement not seen until end
of always block. D
D Q C D Q B D Q A

clk
Effect of sequential execution
▪ Order is important
module shiftregX1 ( module shiftregY1 (
input D, clk, input D, clk,
output reg A, B, C); output reg A, B, C );

always @ (posedge clk) always @ (posedge clk)

begin begin
A = B; C = D;
B = C; B = C;
C = D; A = B;
end end
endmodule endmodule

15
Effect of concurrent execution
▪ Order is not important
module shiftregX2 ( module shiftregY2 (
input D, clk, input D, clk,
output reg A, B, C ); output reg A, B, C );
always @ (posedge clk) always @ (posedge clk)
begin begin
A <= B ; C <= D ;
B <= C ; B <= C ;
C <= D ; A <= B ;
end end
endmodule endmodule

16
Recommendations

▪ When modelling logic that includes edge-triggered register transfers:

▪ The synchronous (i.e. edge-sensitive)operations be described by non-blocking
assignments ( <= )
▪ The combinational logic be described with blocking assignment statements ( = )

“From now on, the non-blocking assignment

is used in all sequential logic designs”
DFF with asynchronous Reset

module DFF2 (
input CLK, Data_in, RST, Data_in D
output reg Data_out); f/f Q Data_out
CLK
clr
always @ (posedge RST, posedge CLK)
if ( RST ) Data_out <= 0 ;
RST
else Data_out <= Data_in ;
endmodule
DFF with active low asynchronous reset
module DFF2 (
input CLK, D, RST,
output reg Q ); Data_in
D D
f/f Q Q
Data_o ut
always @ (negedge RST, posedge CLK) CLK
clr
if ( !RST )
Q <= 0 ; RST
else
Q <= D ;
endmodule

Exercise:
Modify to have sync active-low reset
Exercise
▪ Modify to include negative-
edge triggered, active-high for
both asynchronous reset Dff3
PST

(RST) and preset (PST)

D pre
d
Q
CLK q

inputs. clr

RST

module Dff3 (input CLK, D, RST, PST, output reg Q);

always @ (negedge RST, posedge PST, negedge CLK)
if ( RST == 0 ) Q <= 0;
else if (PST == 1) Q <= 1;
else Q <= D;
endmodule
The timing diagram?

clk

pst

rst

load

d a ta d a ta 1 d a ta 2 d a ta 3

Q
Result :

CAD with HDL 22

Flip-flop with a tristate output

module tri_DFF (
Temp
input CLK, EN, OE, Data_In, Data_In D
Q
output Data_Out , EN f/f Data_out

reg Temp ) ; CLK C

always @ (posedge CLK) OE

if (EN)
Temp <= Data_In;
else
Temp <= Temp;
assign Data_Out = OE ? 1’bz : Temp ;
endmodule
Waveform of tri_DFF
Result
Registers

▪ Registers are just n-bit (n >1) structures consisting of FFs.

▪ A common clock is used for each FF in the register.
▪ Example 4.6(a) : 4-bit Register with active high enable, and asynchronous reset &
preset inputs
module reg8 (
input clock, load, reset, preset,
input [7:0] data,
output reg [7:0] Q );

always @ (posedge reset, posedge preset, negedge clock)

if (reset) Q <= 0 ;
else if (preset) Q <= {8{1’b1}} ;
else if (load) Q <= data ;
else Q <= Q;
endmodule
Timing diagram
clk

pst

rst

load

data data1 data2 data3

Q
Binary Counter

▪ An 8-bit binary counter consists of a register of 8 D-type flip-flops,

whose content is the binary representation of a decimal number. At
each clock edge, the contents of the counter are increased by one.

module binarycounter (
input rst, clk,
output reg [7:0] count );

always @ (negedge rst, posedge clk)

if ( rst == 0 )
count <= 0 ;
else
count <= count + 1 ; //Note that carry out
// is not generated
endmodule
Decade Counter

▪ Design a decade counter module DecadeCounter (

(also known as a modulo- input clk, rst,
10 counter or divide-by-10 output reg [3:0] Q);
counter)
always @ (negedge rst, posedge clk)
▪ Solution: if ( rst == 0 )
▸ The maximum count value Q <= 0;
is 9 or binary 1001. Use this else if ( Q == 9 )
value to reset the counter to Q <= 0;
0 on the next cycle, else
resulting in a wrap-around Q <= Q + 1;
count. endmodule