INTERNATIONALJOURNALOFAPPLIEDENGINEERINGRESEARCH,DINDIGUL Volume1,No2,2010 Copyright2010AllrightsreservedIntegratedPublishingAssociation RESEARCHARTICLEISSN 09764259

1 2 VijayKumarSharma ,SurenderSoni 1DepartmentofElectronics&Communication,CollegeofEngineering,Teerthanker MahaveerUniversity,Moradabad 2DepartmentofElectronics&Communication,NationalInstituteofTechnology,Hamirpur [email protected]

ComparisonamongdifferentCMOSinverterforLowleakageatdifferent Technologies

ABSTRACT InCMOScircuits,thereductionofthethresholdvoltageduetovoltagescalingleadstoincrease insubthresholdleakagecurrentandhence,staticpowerdissipation.Inthenanometertechnology regime, power dissipation and Process parameter variations have emerged as major design considerations.Theseproblemscontinuetogrowwithleakagepowerbecomingadominantform ofpowerconsumption.Ontheotherhand, variations inthedeviceparameters,bothsystematic andrandom,translateintovariationsincircuitparameterslikedelayandleakage.Leakagepower dissipation is projectedto grow exponentially in the next decade according tothe International TechnologyRoadmapforSemiconductors(ITRS).Thisdirectlyaffectsportablebatteryoperated devices such as cellular phones and PDAs since they have long idle times. Several techniques usedthatefficientlyminimizethisleakagepowerloss.Stackingisaleakagereductiontechnique. Keywords:LowPower,Leakage,CMOSinverter 1.Introduction Astechnologyscalesdown,thesizeoftransistorshasbeenshrinking.Thenumberoftransistors onchiphasthusincreasedtoimprovetheperformanceofcircuits.Thesupplyvoltage,beingone of the critical parameters, has also been reduced accordingly in order to maintain the characteristicsofanMOSdevice.Thereforeinordertomaintainthetransistorswitchingspeed, the threshold voltage is also scaled down at the same rate as the supply voltage. As a result, leakage currents increase dramatically with each technology generation [2,6]. As the leakage currentincreasesfaster,itwillbecomemoreandmoreproportionaltothetotalpowerdissipation. PLEAK =ILEAK*Vdd (1) Designers need to develop new low power techniques to reduce total leakage in nanoscale circuits, especially for chips that are used in powerconstrained portable systems. The leakage currentconsistsofreversebiasdiodecurrentsandsubthresholdcurrent.Theformerisduetothe storedchargebetweenthedrainandbulkofactivetransistorswhilethelaterisduetothecarrier diffusionbetweenthesourceanddrainoftheofftransistors.Thesubthresholdcurrentisgiven as:

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Ids = oCox
Where:
m =1+

w 2 ( m -1) ( Vt ) e( Vgs -Vth) /mVt* (1eVds/Vt)...(2) 1

Cdm 3tox = 1+ Cox Wdm

Where: Vth = Thethresholdvoltage Vt = Thethermalvoltage Cox = Gateoxidecapacitance 0 = Zerobiasmobility m = Thesubthresholdswingcoefficient(alsocalledbodyeffectcoefficient) Wdm= Themaximumdepletionlayerwidth tox = Thegateoxidethickness Cdm =Thecapacitanceofthedepletionlayer Inordertofacilitatevoltagescalingwithoutaffectingtheperformance,thresholdvoltagehasto bereduced.Thisalso leadstobetternoise marginsand helpstoavoidthe hotcarriereffects in short channel devices. Scaling down of threshold voltage results in exponential increase of the subthresholdleakagecurrent.So,beforegoingtoinnanometerregimeweneedsometechniques applied for CMOS logic to minimize the leakage power. Stacking is such technique used for minimizetheleakagepower [1]. 2.Leakagereductionbystackingoftransistors Subthresholdleakageisexponentiallyrelatedtothethresholdvoltageofthedeviceandthe thresholdvoltagechangesduetobodyeffect.Fromthesetwofacts,onecanreduce

Figure1:Blockdiagram thesubthresholdleakageinthedevicebystackingtwoormoretransistorsserially.Thetransistors abovethelowesttransistorwillexperienceahigherthresholdvoltageduetothedifferenceinthe 229

INTERNATIONALJOURNALOFAPPLIEDENGINEERINGRESEARCH,DINDIGUL Volume1,No2,2010 Copyright2010AllrightsreservedIntegratedPublishingAssociation RESEARCHARTICLEISSN 09764259

voltagebetweenthesourceandbody.Also,theVdsofthehighertransistorisdecreased,sincethe intermediatenodehasavoltageabovetheground.TheseresultsinreductionofDIBLaffecthence better leakage savings. However, forced stack deviceshavestrong performancedegradation thatbe taken intoaccountwhen applying the techniq ue.Figure (1) shows an inverter with aforced NMOS stack. Itisevidentthat the aforementioned ef fects areexplainedby lookingat the thresholdvoltage and leakage values of thisinverter. The leakage savingsislargewhen the conventional inverter and the forced NMOS, fo rced PMOS case are compared. Thenew threshold voltage of the devicevaries this fact. The nodevoltage at Vm does thefollowing: 1. IncreasesN1sthresholdvoltagedue tobodyeffect, 2. Increases N1 and N2s thresholdvoltagedueto lower Vds (lower DIBL), Puts N1 into strongoffstatesinceVgsisnegative Fromabove,itwas seen thatthesubthresholdleakage alsostronglydepends ontheinputapplied tothecircuit.Thiscreatesanothermethodforreducingsubthresholdleakage. 3.ResultandDiscussion TheimplementedcircuitsaresimulatedtomeasuretotalleakagePower.Techniqueusing70nm, 100 nm, 130, 180 nm technology has been simulated on TSPICE tool. Tables show the simulationresultsofeachcircuitatroomtemperature.Usingleakagemonitoringandthebalance between subthreshold leakage and BTBT (band to band tunneling) leakage, the new optimal bodybiastechniquegivesreductionintotalleakagepower.Sincetheoptimalbiasresultsinthe minimum leakage current for nanoscale device in standby mode, the power in active mode is also improved by applying the optimal body bias. The circuits for CMOS inverter are shown belowandtheircorrespondingtotalleakagepowervs.technologyislistedinthetables. Instackingoftransistorswevarythethresholdvoltageofthetransistorsbyprovidingbulkto source biasing negative [3]. This increase the threshold voltage of the device, more threshold voltage means less sub threshold current, this cause less total leakage power. The threshold voltageofadeviceisgivenas:

Vth = Vfb + 2 y B+
Where:

2 e siqN a (2 y B + Vbs) C ox
(4)

Vfb = Theflatbandvoltage Na = Thedopingdensityinthesubstrate B = ThedifferencebetweentheFermipotentialandtheintrinsicpotentialinthesubstrate

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Figure2:ConventionalCMOSinverter Figure3: ForcedNMOStransistor CMOS inverter

Figure4:ForcedPMOStransistorCMOS Figure(5) Forced2NMOS transistors CMOSinverter

Technology(nm) 70 100 130 180

Table1:ForconventionalCMOSinverter Totalleakagepower(nW) 8.1478 1.8172 0.3635 0.2873

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Table2:ForforcedNMOStransistor CMOSinverter Technology(nm) 70 100 130 180 Totalleakagepower(nW) 1.2271 0.1495 0.0897 0.0371 Table3:forforcedPMOStransistorCMOSinverter Technology(nm) 70 100 130 180 Totalleakagepower(nW) 2.8180 1.0102 0.2364 0.1278 Table4:forforced2NMOStransistorsCMOSinverter Technology(nm) 70 100 130 180 Totalleakagepower(nW) 0.5798 0.0761 0.0525 0.0112

Figure6:Totalleakagepower(nW)VsTechnology(nm) 232

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4.Conclusion Scaling down of device dimensions, supply voltage and threshold voltage for achieving high performance and low dynamic power dissipation has largely contributed to the increase in leakagepowerdissipation.Wehavepresentedanefficientdesignmethodologyforreducingthe leakage power in CMOS inverter circuit. Implications of technology scaling on the choice of techniquestomitigatetotalleakageareexamined.Theresultsareguidelinesfordesigninglow leakage circuits in nanometre technology. Logic gate in the 70, 100, 130 and 180 nm technologies are simulated and analyzed. Stacking performs well as the threshold voltage decreasesandhenceaidsfurtherreductionofsupplyvoltageandminimizationoftransistorsizes. 5.References 1. Johnson,M.C.,D.Somasekhar,L.Y.ChiouandK.Roy,2002.Leakagecontrolwith efficientuseoftransistorstacksinsinglethresholdCMOS.IEEETVLSI,10:pp 15. 2. Kim,N.S.etal.,2003.Leakagecurrent:Mooreslawmeetsstaticpower.IEEEComputer, 36:pp6875. 3. Kuroda,T.andT.Sakurai1996.Thresholdvoltagecontrolschemesthroughsubstrate biasforlowpowerhighspeedCMOSLSIdesign.J.VLSISignalProc.Syst.,13:pp 191 201. 4. Narendra,S.,V.D.S. Borkar,D. AntoniadisandA.Chandrakasan,2001.Scalingof stackeffectanditsapplicationforleakagereduction.ProceedingoftheInternational SymposiumLowPowerElectron.Des.,pp195200. 5. Powell,M.D.,S.H.Yang,B.Falsafi,K.RoyandT.N.Vijaykumar,2000.GatedVdd: Acircuittechniquetoreduceleakageindeepsubmicroncachememories.Proc.Of ISLPED,pp9095. 6. Roy,K.,S.MukhopadhayaandH.MahmoodiMeimand,2003.Leakagecurrent mechanismsandleakagereductiontechniquesindeepsubmicrometerCMOScircuits. Proc.IEEE,91:pp 305327.

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