Faculty of Computing and Information Technology (FCIT)

EI-231 Computer Organization & Design

ASSIGNMENT#2
BS(IT) – Special Section (Summer 2024)
Total Marks: 100 Deadline: August 21, 2024
Instructions
• You must complete all the tasks individually. The submission will be followed by viva-voce.
• Any traces of plagiarism/cheating would result in either Zero marks.
Questions
1. Draw the logic circuit of D flip flop using NAND gates. Design a sequential circuit using two D flip flops,
and a control input x. When x = 0, the circuit remains in the same state. When x = 1, the circ circuit goes
through the state transitions from 00 to 01 to 11 to 10 back to 00, and repeats. [10]
2. Design a 3-bit counter using T flip flops that follows the following sequence of states. Also determine whether
or not the counter is a self-correcting counter. [10]
0 → 1 → 2→ 4→ 5 → 6 →0
3. [20 pts.]
a) A JN flip-flop has two inputs, J and N, Input J behaves like the J input of a JK flip-flop and input N
behaves like the complement of the K input of a JK flip-flop (that is, N = K'). [6]
• Tabulate the characteristic table of the flip-flop and derive its characteristics equation.
• Tabulate the excitation table of the flip-flop.
b) Show the construction of a 3-bit down counter using T flip-flops with truncated sequence that counts
down a truncated sequence from 111 to 010. On reaching the count value 010, the counter must preset to
111. [7]
c) You are given the input equations for UP and DOWN counters using T flip flops as shown in the table
below. Using the given equations, show the construction of a 3-bit UP/DOWN counter using three T flip
flops and two 2x1 Multiplexers. [7]

FF Inputs UP Counter DOWN Counter

T2 Q1Q0 Q1'Q0'
T1 Q0 Q0'
T0 1 1

4. Implement the following state diagram using RS flip flops. [15]

5. Design a sequential circuit with two RS flip-flops, A and B, and two inputs, E and x. If E = 0, the circuit
remains in the same state regardless of the value of x. When E = 1 and x = 1, the circuit goes through the
state transitions from 00 to 10 to 01 to 11 back to 00, and repeats. When E = 1 and x = 0, the circuit goes
through the state transitions from 00 to 11 to 01 to 10 back to 00, and repeats. [10]
6. Derive the state table and state transition diagram of a sequential circuit shown in Figure P6-11, Page 253.
Starting at a state 00, determine the destination state and the output sequence y for the input sequence
0110101. [10]
7. Design a 3-bit synchronous counter using T flip flops, whose counting sequence is controlled an input x.
For x = 1, the counting sequence is 0 -> 3 -> 5 -> 2 -> 6 -> 4 Repeat.
For x = 0, counting sequence can be found in the table. [6+9]

Control Present State Next State Flip-Flop

Input (t) (t+1) Inputs
x Q2 Q1 Q0 Q2 Q1 Q0 T2 T1 T0
0 0 0 0 1 0 0
0 0 0 1 0 0 0
0 0 1 0 1 1 1
0 0 1 1 1 1 0
0 1 0 0 1 1 1
0 1 0 1 1 1 1
0 1 1 0 0 1 1
0 1 1 1 1 1 0
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

8. [10 pts. (7+3)]

a) Draw the logic circuit diagram for 4-bit register using D flip Control Inputs
Operation
flops capable of performing the operations given in the table. X1 X 0
b) Consider a 6-bit register that has been loaded with the 0 0 Parallel Load
contents 110101. Write the subsequent contents of the 0 1 Arithmetic Shift Right
register after each of the Arithmetic Shift Right, Rotate Left, 1 0 Rotate Left
Complement, Rotate Right, and Shift Left operations. 1 1 Complement