11/24/2020 VLSI Design - MOS Transistor - Tutorialspoint

VLSI Design - MOS Transistor

Complementary MOSFET (CMOS) technology is widely used today to form circuits in numerous
and varied applications. Today’s computers, CPUs and cell phones make use of CMOS due to
several key advantages. CMOS offers low power dissipation, relatively high speed, high noise
margins in both states, and will operate over a wide range of source and input voltages (provided
the source voltage is fixed)
For the processes we will discuss, the type of transistor available is the Metal-Oxide-
Semiconductor Field Effect Transistor (MOSFET). These transistors are formed as a ‘sandwich’
consisting of a semiconductor layer, usually a slice, or wafer, from a single crystal of silicon; a layer
of silicon dioxide (the oxide) and a layer of metal.

Structure of a MOSFET

As shown in the figure, MOS structure contains three layers −

The Metal Gate Electrode
The Insulating Oxide Layer (SiO22)
P – type Semiconductor (Substrate)
MOS structure forms a capacitor, with gate and substrate are as two plates and oxide layer as the
dielectric material. The thickness of dielectric material (SiO22) is usually between 10 nm and 50 nm.
Carrier concentration and distribution within the substrate can be manipulated by external voltage
applied to gate and substrate terminal. Now, to understand the structure of MOS, first consider the
basic electric properties of P – Type semiconductor substrate.

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Concentration of carrier in semiconductor material is always following the Mass Action Law. Mass
Action Law is given by −

2
2
n
n.. p
p =
= n
n
i
i

Where,
n is carrier concentration of electrons
p is carrier concentration of holes
ni is intrinsic carrier concentration of Silicon
Now assume that substrate is equally doped with acceptor (Boron) concentration NAA. So, electron
and hole concentration in p–type substrate is

2
2
n
n
i
i
n
np =
o =
po
N
NAA

p
pp = NA
o = NA
po

Here, doping concentration NAA is (1015

15
to 1016
16
cm−3
−3
) greater than intrinsic concentration ni. Now, to
understand the MOS structure, consider the energy level diagram of p–type silicon substrate.

As shown in the figure, the band gap between conduction band and valance band is 1.1eV. Here,
Fermi potential ΦFF is the difference between intrinsic Fermi level (Eii) and Fermi level (EFP
FP).

Where Fermi level EFF depends on the doping concentration. Fermi potential ΦFF is the difference
between intrinsic Fermi level (Eii) and Fermi level (EFP
FP).

Mathematically,

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E
EF − Ei
F − Ei
Φ
ΦF =
p =
Fp
q
q

The potential difference between conduction band and free space is called electron affinity and is
denoted by qx.
So, energy required for an electron to move from Fermi level to free space is called work function
(qΦSS) and it is given by

q
qΦΦs = (E c −
s = (Ec −EEF ) + qx
F ) + qx

The following figure shows the energy band diagram of components that make up the MOS.

As shown in the above figure, insulating SiO22 layer has large energy band gap of 8eV and work
function is 0.95 eV. Metal gate has work function of 4.1eV. Here, the work functions are different so
it will create voltage drop across the MOS system. The figure given below shows the combined
energy band diagram of MOS system.

As shown in this figure, the fermi potential level of metal gate and semiconductor (Si) are at same
potential. Fermi potential at surface is called surface potential ΦSS and it is smaller than Fermi
potential ΦFF in magnitude.

Working of a MOSFET

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MOSFET consists of a MOS capacitor with two p-n junctions placed closed to the channel region
and this region is controlled by gate voltage. To make both the p-n junction reverse biased,
substrate potential is kept lower than the other three terminals potential.

If the gate voltage will be increased beyond the threshold voltage (VGSGS>VTO
TO), inversion layer will be
established on the surface and n – type channel will be formed between the source and drain. This
n – type channel will carry the drain current according to the VDS
DS value.

For different value of VDS

DS, MOSFET can be operated in different regions as explained below.

Linear Region

At VDS
DS = 0, thermal equilibrium exists in the inverted channel region and drain current ID D = 0. Now if
small drain voltage, VDS
DS > 0 is applied, a drain current proportional to the VDS
DS will start to flow from
source to drain through the channel.

The channel gives a continuous path for the flow of current from source to drain. This mode of
operation is called linear region. The cross sectional view of an n-channel MOSFET, operating in
linear region, is shown in the figure given below.

At the Edge of Saturation Region

Now if the VDSDS is increased, charges in the channel and channel depth decrease at the end of drain.
For VDS
DS = VDSAT
DSAT, the charges in the channel is reduces to zero, which is called pinch – off point.
The cross sectional view of n-channel MOSFET operating at the edge of saturation region is shown
in the figure given below.

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Saturation Region

For VDS
DS>VDSAT
DSAT, a depleted surface forms near to drain, and by increasing the drain voltage this
depleted region extends to source.
This mode of operation is called Saturation region. The electrons coming from the source to the
channel end, enter in the drain – depletion region and are accelerated towards the drain in high
electric field.

MOSFET Current – Voltage Characteristics

To understand the current – voltage characteristic of MOSFET, approximation for the channel is
done. Without this approximation, the three dimension analysis of MOS system becomes complex.
The Gradual Channel Approximation (GCA) for current – voltage characteristic will reduce the
analysis problem.

Gradual Channel Approximation (GCA)

Consider the cross sectional view of n channel MOSFET operating in the linear mode. Here, source
and substrate are connected to the ground. VSS = VBB = 0. The gate – to – source (VGS
GS) and drain – to
– source voltage (VDS
DS) voltage are the external parameters that control the drain current ID
D.

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The voltage, VGSGS is set to a voltage greater than the threshold voltage VTO
TO, to create a channel
between the source and drain. As shown in the figure, x – direction is perpendicular to the surface
and y – direction is parallel to the surface.

Here, y = 0 at the source end as shown in the figure. The channel voltage, with respect to the
source, is represented by VC(Y)
C(Y). Assume that the threshold voltage VTO is constant along the
channel region, between y = 0 to y = L. The boundary condition for the channel voltage VCC are −

V
Vc (y = 0) = V s =
c (y = 0) = Vs = 0
0aan
nddV
Vc (y = L) = V DS
c (y = L) = VD S

We can also assume that

V
VG ≥ V TO
S ≥ VT
GS O

and

V
VG = V GS
D = VG
GD
− V DS
S − VD
≥ V TO
S ≥ VT O

Let Q1(y) be the total mobile electron charge in the surface inversion layer. This electron charge
can be expressed as −

Q
Q11(
(yy)
) =
= −
−CCo
ox
. [V GS
x . [VG
− V (Y ) −
S − VC −V
VT O]
TO
]
C (Y )

The figure given below shows the spatial geometry of the surface inversion layer and indicate its
dimensions. The inversion layer taper off as we move from drain to source. Now, if we consider the
small region dy of channel length L then incremental resistance dR offered by this region can be
expressed as −

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d
dyy
d
dRR =
= −
−
w
w.. μ
μn . Q1(y)
n . Q1(y)

Here, minus sign is due to the negative polarity of the inversion layer charge Q1 and μnn is the
surface mobility, which is constant. Now, substitute the value of Q1(y) in the dR equation −

d
dyy
d
dRR =
= −
−
w
w.. μ
μn . {−C ox
n . {−Co
[V GS
x [VG
− V (Y ) ]
S − VC ]−
−VVT
TO
}
O}
C (Y )

d
dyy
d
dRR =
=
w
w.. μ
μn .. C x [
[V −
−V ]
]−−V
n Co ox VG
GSS VC
C((Y
Y))
VTTO
O

Now voltage drop in small dy region can be given by

d
dVVc = I D .. d
c = ID dRR

Put the value of dR in the above equation

d
dyy
d
dVVC =
= I
ID ..
C D
w
w.. μ
μn . C ox
n . Co
[V GS
x [VG
− V (Y ) ]
S − VC ]−
−VVT
TOO
C (Y )

w
w.. μ
μn . C ox
n . Co
[V GS
x [VG
− V (Y ) −
S − VC −V
VT ] . dV C =
O ] . dVC
TO = I
ID . dy
D . dy
C (Y )

To obtain the drain current ID over the whole channel region, the above equation can be integrated
along the channel from y = 0 to y = L and voltages VC(y)
C(y) = 0 to VC(y)
C(y) = VDS
DS,

V
VDDS
S
L
L

C
Co . w. μ n.. ∫
x . w. μn
ox ∫ [
[VVG
GS
− V (Y ) −
S − VC −V
VT ] . dV C =
O ] . dVC
TO = ∫
∫ I
ID . dy
D . dy
C (Y )
V
Vcc=
=00 Y
Y==0
0

C
Co . w. μ n
x . w. μn
ox 2
2
(
(22 [[V
VG − V TO
S − VT
GS
] V DS
O ] VD
− V
S − V
)
) =
= I
ID [L − 0]
D [L − 0]
D
DSS
2
2

C
Co . μn
x . μn
ox
w
w
2
2
I
ID =
D =
.. (
(22 [[V
VG − V TO
S − VT
GS
] V DS
O ] VD
− V
S − V
)
)
D
DSS
2
2 L
L

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For linear region VDS

DS < VGS
GS − VTO
TO. For saturation region, value of VDS
DS is larger than (VGS
GS − VTO
TO).
Therefore, for saturation region VDS
DS = (VGS
GS − VTO
TO).

2
2
w
w [[2
2VVD
DS
] V DS
S ] VD
− V
S − V D
DSS
I
ID = C ox
D = Co
. μ n..
x . μn
(
( )
)
2
2 L
L

2
2 2
2
w
w 2
2VV −
−VV
D
DSS D
DSS
I
ID = C ox
D = Co
. μ n..
x . μn
(
( )
)
2
2 L
L

2
2
w
w V
V
D
DSS
I
ID = C ox
D = Co
. μ n..
x . μn
(
( )
)
2
2 L
L

2
2
w
w [[V
VG − V TO
S − VT
GS O]
]
I
ID = C ox
D = Co
. μ n..
x . μn
(
( )
)
2
2 L
L

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