National University of Computer and Emerging Sciences

School of Engineering Islamabad Campus

Serial No:
EE 1005 Final Exam (Solution)
Digital Logic Design Total Time: 03 Hours
Tuesday, May 23, 2023 Total Marks: 150
Course Instructor
________________
Engr. Aamer Hafeez Signature of Invigilator

_____________________________________________ _____________________
Student Name Roll No Section Signature

DO NOT OPEN THE QUESTION BOOK OR START UNTIL INSTRUCTED.

Instructions:
1. Verify at the start of the exam that you have a total of five (5) questions printed
on twenty-seven (27) pages including this title page.
2. Attempt all questions on the question book and in the given order.
3. The exam is closed books, and closed notes. Please see that the area in your
threshold is free of any material classified as ‘useful in the paper’ or else there
may a charge of cheating.
4. Read the questions carefully for clarity of context and understanding of the
meaning and make assumptions wherever required, for neither the invigilator will
address your queries, nor the teacher/examiner will come to the examination hall
for any assistance.
5. Fit in all your answers in the provided space. You may use extra space on the last
page if required. If you do so, clearly mark the question/part number on that
page to avoid confusion.
6. Use only your own stationery and calculator. If you do not have your own
calculator, use manual calculations.
7. Use only permanent ink-pens. Only the questions attempted with permanent ink-
pens will be considered. Any part of the paper done in lead pencil cannot be
claimed for rechecking.

Q-1 Q-2 Q-3 Q-4 Q-5 Total

Total
30 35 30 30 25 150
Marks
Marks Obtained

Assessment of CLO CLO2 CLO2 CLO3 CLO3 CLO4

Vetted By: ____________________________Vetter Signature: ____________________

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CLO-02: Analyze combination logic circuits to draw truth table and sequential logic circuits
to determine the state equations, state table, and state diagram.
_________________________________________________________________________
Question 1 [Marks=30]

Determine
A.
below. Determine
the output
thefunction,
output function,
Z, and derive
Z as the
a minimized
truth tablefunction
of the given
of input
logic variables,
diagram and
derive the truth table of the given below logic diagram. [Marks=5+5=10]

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B. Compare the NOR-based Latch with NAND based Latch on the following basis:

 Structure

 Working

 Function Table [Marks=3+4+3=10]

Two Types
The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates,
and two inputs (labelled S for set and R for reset).
NOR SR Latch
SR latch can be created with two NOR gates that have a cross-feedback loop.
NAND SR Latch
SR latches can also be made from NAND gates, but the inputs are swapped and negated. In
this case, it is sometimes called an SR’ latch.

SR Latch (NOR implementation)

The latch has two useful states.

When output Q = 1 and Q’ = 0, the latch is said to be in the set state.
When Q = 0 and Q’ = 1, it is in the reset state.
Outputs Q and Q’ are normally the complement of each other.

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In general (one exception, see below), the outputs are complements of each other (this is
why they are labeled Q and Q’

Case1: When S=1, R=0

the output is Q=1, Q’= 0 and the circuit in the set state.
When S=0, R=0,
the output holds at its previous value (storage).

Case2: When S=0, R=1

the output is Q=0, Q’=1 and the circuit in the reset state.
When S=0, R=0,
the output holds at its previous value (storage).

Case3: When S=1, R=1

the output is Q=Q’=0 which is not desirable. Both outputs are same which is in
contradiction and not true. We want to avoid this combination of inputs.
When S=0, R=0,
Q=0, Q’=1
Q=1, Q’=0

Note: Due to this behaviour Case 3 is not used.

SR Latch (NAND implementation)

The SR latch with two cross-coupled NAND gates is shown in Fig. 5.4.
It operates with both inputs normally at 1, unless the state of the latch has to be changed.

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Case 1: When S=0, R=0, (When any input is zero, output is 1)

Q=1, Q’=1 (But this is not true and not desirable) … Not used

Case 2: When S=1, R=0, (When any input is zero, output is 1)

Q’=1, Q=0 (and the circuit in the reset state)

Case 3: When S=0, R=1, (When any input is zero, output is 1)

Q=1, Q’=0 (and the circuit in the set state)

Case 4: When S=1, R=1, (Check the previous output)

Q=1, Q’=0 (the output holds at its previous value (storage works like memory).
Note: We will use Case 4, after Case 2 and 3 to hold the previous state(memory)

C. How is master slave D Flip Flop constructed? Discuss its working with a suitable
timing diagram. [Marks=10]

• Master slave D flip flop can be designed by the series connection of two gated D
latches and connecting an inverted enable input either to of the two latches.
• Only the change in Master latch will bring change in Slave latch. So these are called
Master Slave flip flops.
• The total circuit of master slave flip flop is triggered either on the rising edge of the
clock signal or on falling edge of clock signal depending on the design
• The symbolic representation of a master slave D flip flop that responds to the clock at
its falling edge as shown below

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• The Master slave D flip flop shown below is a positive edge triggered device that
means it will operate when clock input has raising edge.
• The first flip flop (master flip – flop) is connected with a negative clock signal i.e
inverted and the second flip – flop (slave flip – flop) is connected with double inverse
of clock signal i.e. normal clock signal

• A D flip flop takes only a single input, the D (data) input. The master-slave
configuration has the advantage of being edge-triggered, making it easier to use in
larger circuits, since the inputs to a flip-flop often depend on the state of its output.
The circuit consists of two D flip-flops connected together.
• Consider two latches combined together. Only one C value active at a time

• Note the layout here.

• The flip-flop input D is connected directly to the master latch.
• The master latch output goes to the slave.
• The flip-flop outputs come directly from the slave latch.

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• Stores a value on the positive edge of C

• Input changes at other times have no effect on output

CLO-02: Analyze combination logic circuits to draw truth table and sequential logic circuits
to determine the state equations, state table, and state diagram.
_________________________________________________________________________
Question 2 [Marks=35]

A. Consider the following synchronous sequential circuit and derive the following :
[Marks=5+5+5+5=20]

 Output equations

 Flip-flop input equations

 State table

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 State diagram

Output equations

• The characteristic equation for D flip-flops makes analysis a little easier than other
flip-flops
• Consider this circuit with JK flip-flops ¾Here we assume that A and B are the circuit
outputs
Flip-flop input equations

• Equations for inputs to FFs:

• JA = B
• KA = BX’
• JB = X’
• KB = A exclusive OR X = AX’+A’X
State table

• Fill in inputs and current state as usual

• Evaluate FF inputs based on inputs and current state
• Use characteristic table to obtain next state from FF inputs
• JK FF characteristic table

J K Q+
0 0 Q

0 1 0

1 0 1

1 1 Q’

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Current A FF B FF Next
InputX State inputs inputs State
A B JA KA JB KB A+ B+

0 0 0 0 0 1 0 0 1

1 0 0 0 0 0 1 0 0

0 0 1 1 1 1 0 1 1

1 0 1 1 0 0 1 1 0

0 1 0 0 0 1 1 1 1

1 1 0 0 0 0 0 1 0

0 1 1 1 1 1 1 0 0

1 1 1 1 0 0 0 1 1

State Diagram

• Now obtain state diagram from state table Based on inputs, current state, and next
state
• Now we can analyze circuit behavior Based on initial state and input sequence

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State order 00
0 X=0
AB
0
01 11 1

1 0
10
1

B. How can you show that T Flip Flop acts as a digital toggle switch? You are required
to explain in the light of the function table, characteristic table and excitation
equations. [Marks=5+5+5=15]

• A T flip flop is known as a toggle flip flop because of its toggling operation.
• It is a modified form of the JK flip flop.
• A T flip flop is constructed by connecting J and K inputs, creating a single input called T.
Hence why a T flip flop is also known as a single input JK flip flop.
• The defining characteristic of T flip flop is that it can change its output state. You can
change the output signal from one state (on or off) to another state (off or on).
• The simplest of the constructions of a T flip – flop is with JK flip – flop. The J input and K
input of the JK flip – flop are connected together and provided with the T input. The logic
circuit of a T flip – flop constructed from a JK flip – flop is shown below

• Function Table/ Truth Table

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• Characteristic Table

• Excitation Table

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• From the Characteristic table, we can observe that, when T input is 0, there is no change in
the state. So for the state transition from the present state to the next state, i.e., from Qn = 0
to Qn+1 = 0 and from Qn = 1 to Qn+1 = 1, the excitation input require is T = 0. It is filled in the first
and the fourth row in the excitation table.

Similarly, from the Characteristic Table, we can also observe, when T = 1, the state of
the flip flop toggles or complemented. Thus, for the transition of the state from either
0 to 1 or from 1 to 0, the excitation input is T = 1. It is filled in the second and the
third row of the excitation table

CLO-03: Design combinational and sequential logic circuits according to provided

requirements/specifications
________________________________________________________________________
Question 3 [Marks=30]

A. Design a circuit that has a 3-bit binary input and a single output (Z) specified as
follows:

 Z = 0, when the input is less than 5

 Z = 1, otherwise [Marks=5]

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B. A combination circuit is specified by the following three Boolean functions:

 F1( A, B, C) = ∑ ( 2, 4, 7)

 F2( A, B, C) = ∑ ( 0, 3)

 F3( A, B, C) = ∑ ( 0, 2, 3, 4, 7)

Implement the circuit with a decoder construction with NAND gates and NAND or
AND gates connected to the decoder outputs. Use a block diagram for the decoder.
Minimize the number of inputs in the external gates. [Marks=5]

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Note: Take two times complement for NAND conversion

C. Design an excess-3-to-binary decoder using the unused combinations of the code

as don’t-care conditions. [Marks=5]

Don’t Care conditions= 0, 1,2

In binary = 0000, 0001, 0010

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D. Implement the following Boolean function with a 4x1 multiplexer and external
gates.

F (A, B, C, D) = ∑ (1, 3, 4, 11, 12, 13, 14, 15) [Marks=5]

E. How can you justify the statement that “Priority encoders are often used to control
interrupt requests by acting on the highest priority interrupt input”? A logic

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diagram of this encoder is mandatory.
[Marks=5]

 A priority encoder is an encoder circuit that includes the priority function.

 The operation of the priority encoder is such that if two or more inputs are equal to 1
at the same time, the input having the highest priority will take precedence.
 The truth table of a four-input priority encoder is given in Table
 In addition to the two outputs x and y , the circuit has a third output designated by V
o V is a valid bit indicator that is set to 1 when one or more inputs are equal to
1.
o If all inputs are 0, there is no valid input and V is equal to 0.
o The other two outputs are not inspected when V equals 0 and are specified as
don’t-care conditions.
 Note
o x’s in output columns represent don’t-care conditions
o x’s in the input columns are useful for representing a truth table in condensed
form.
 Instead of listing all 16 minterms of four variables, the truth table uses
an x to represent either 1 or 0.
 For example, x100 represents the two minterms 0100 and 1100.

 According to Table, the higher the subscript number, the higher the priority of the
input.
 Input D3 has the highest priority, so, regardless of the values of the other inputs,
when this input is 1, the output for xy is 11 (binary 3).
 D2 has the next priority level. The output is 10 if D2 = 1, provided that D3 = 0,
regardless of the values of the other two lower priority inputs.
 The output for D1 is generated only if higher priority inputs are 0, and so on down the
priority levels.

 The maps for simplifying outputs x and y are shown in Fig.

 The minterms for the two functions are derived from Table. Although the table has
only five rows, when each X in a row is replaced first by 0 and then by 1, we obtain all
16 possible input combinations.
 For example, the fourth row in the table, with inputs XX10, represents the four
minterms 0010, 0110, 1010, and 1110.

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 The simplified Boolean expressions for the priority encoder are obtained from the
maps.
 The condition for output V is an OR function of all the input variables.
 The priority encoder is implemented in Fig. according to the following Boolean
functions:

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F. Can we use a quadruple 2:1 Multiplexer as a 4-bit register? Explanation with a logic
diagram is mandatory. [Marks=5]

A multiplexer doesn’t have any ability to store state. Data flows through it, but there’s no
feedback loop in the circuit. One needs a feedback loop to store state using only gates.

CLO-03: Design combinational and sequential logic circuits according to provided

requirements/specifications
________________________________________________________________________
Question 4 [Marks=30]

A. Design a 4-bit synchronous up counter using JK flip flops. [Marks=5]

 Synchronous binary counters have a regular pattern and can be constructed with
complementing flip-flops and gates

 The regular pattern can be seen from the four-bit counter depicted in Fig. 6.12 .

 The C inputs of all flip-flops are connected to a common clock.

 The counter is enabled by Count_enable.

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 If the enable input is 0, all J and K inputs are equal to 0 and the clock does not change the
state of the counter.

 The first stage, A0, has its J and K equal to 1 if the counter is enabled. The other J and K
inputs are equal to 1 if all previous least significant stages are equal to 1 and the count is
enabled.

 The chain of AND gates generates the required logic for the J and K inputs in each stage.

 The counter can be extended to any number of stages, with each stage having an
additional flip-flop and an AND gate that gives an output of 1 if all previous flip-flop
outputs are 1.

B. Design a BCD counter (using T Flip Flops), which is one of the types of most widely
used digital counters and counts up to 10 with an applied clock signal.
[Marks=10]

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 A BCD counter is one of the types of most widely used digital counters, which counts up
to 10 with an applied clock signal.

 It is a 4-bit binary digital counter, counts from 1 (0001) to 10 (1010). In practice, the BCD
counter counts from 0000 (0) to 1001 (9) in decimal form on the application of the clock
signal.

 Because of the return to 0 after a count of 9, a BCD counter does not have a regular
pattern, unlike a straight binary count.

 To derive the circuit of a BCD synchronous counter, it is necessary to go through a

sequential circuit design procedure

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The circuit can easily be drawn with four T flip-flops, five AND gates, and one OR gate.
Synchronous BCD counters can be cascaded to form a counter for decimal numbers of any length.

C. How the information can be transferred serially from register A to register B?

Explain with te assumed data and diagram.
[Marks=5]

 A digital system is to operate in a serial mode when information is transferred and

manipulated one bit at a time.
 This is in contrast to parallel transfer where all the bits of the register are transferred at the
same time.

 Scenario:
o Source Register (A) holds 1 (4-bit) value
o Which needs to be ‘copied’ in Destination Register (B)
o ‘Copied’ means Transfer into ‘B’ and Retain in ‘A’
 For Transfer (A → B):
o Connect O/p of ‘A’ into I/p of ‘B’
o Synchronize both Registers with same Clock
o Clock can be ‘anded’ with Shift Control I/p
 For Retain (A → A):
o Recirculate the O/p of ‘A’ as I/p of same register

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 The serial transfer of information from register A to register B is done with shift registers, as
shown in the block diagram of Fig.
 The serial output ( SO ) of register A is connected to the serial input ( SI ) of register B.
 To prevent the loss of information stored in the source register, the information in register A
is made to circulate by connecting the serial output to its serial input.
 The initial content of register B is shifted out through its serial output and is lost unless it is
transferred to a third shift register.
 The shift control input determines when and how many times the registers are shifted.
 For illustration here, this is done with an AND gate that allows clock pulses to pass into the
CLK terminals only when the shift control is active.
 (This practice can be problematic because it may compromise the clock path of the circuit, as
discussed earlier.)
 Data transfer one bit at a time
 Data loopback for register A

D. Explain the working of the given below “Bit Serial adder”. [Marks=5]

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 It is also called Bit Serial Adder

 Bit by Bit addition
 Serial Binary addition is done by a Flip Flop and a Full Adder
 D F/F stores the Carry Output
 Right Shift Register A
 Right Shift Register B

• Scenario:
• Register A holds ‘Augend’
• Register B holds ‘Addend’
• Contents of A and B needs to be added serially
• Design:
• Have a Full Adder (FA) (x + y + Cin)
• Connect O/ps of A and B into FA
• What to do with Sum (S) and Carry (C) O/ps?

• Carry (C) O/p:

• How to ‘feedback’ previous carry as next?
• C should also be synchronized together with Regs. A & B
• Remember, every component is synchronized with Clock
• So if somehow we manage to ‘attach’ C with Clock, it will get synchronized
with clock or with Reg. A & B
• We can not connect Clock with FA (Combinational cct.)
• Solution: Add a F/F (Say D-type) to store C

• Sum (S) O/p:

• Result of summation can be stored in another Register (say D)
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• Sum (S) O/p:

• In case, contents of one of the input Registers (‘A’ or ‘B’) are no more
required to be preserved
• ‘A’ can also be used to retain the result of Summation (previous data over-
written)
• Re-circulate ‘S’ into ‘A’

 Adding Clock controlled with ‘ Shift I/p’

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E. A state table of a circuit is given and you are required to reduce the number of
states to the extent possible. [Marks=5]

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CLO-04: Develop larger-size RAM from smaller memory elements and program PLD
devices.
___________________________________________________________________________

Question 5 [Marks=25]

A. Suppose you have multiple 1Mx4 memory chips. How will you design the following
memory Units using these chips? [Marks=10]

 1Mx8

 2Mx4

 Design a 1Mx8 using 1Mx4 memory chips

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 Design a 2Mx4 using 1Mx4 memory chips

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and combinational
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athe
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the
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is number
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generate
ROM?
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for adecoder
aa

B. How can you implement a full adder using PROM? All steps are mandatory.
[Marks=10]

Block Diagram of a Full Adder can be represented as:

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The truth table of a full adder is represented as:

Therefore, expression for sum is given as: Sum = ∑ m (1,2,4,7)

and expression for carry is given as: Carry = ∑ m (3,5,6,7)

Logic Diagram: There are three input variables = A, B, C, therefore we will be using a
3:8 decoder.

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C. Comment on the statement with a suitable diagram that “A PLD is an integrated

circuit with internal logic gates connected through electronic paths that behave
similarly to fuses”. [Marks=5]

 ROM is a programmable logic device (PLD).

 The binary information that is stored within such a device is specified in some
fashion and then embedded within the hardware in a process is referred to as
programming the device.
 The word “programming” here refers to a hardware procedure which
specifies the bits that are inserted into the hardware configuration of the
device.
 ROM is one example of a PLD.
 Other such units are the
 Programmable logic array (PLA)
 Programmable array logic (PAL)
 Field-programmable gate array (FPGA).
 A PLD is an integrated circuit with internal logic gates connected through electronic
paths that behave similarly to fuses.
 In the original state of the device, all the fuses are intact.
 Programming the device involves blowing those fuses along the paths that must be
removed in order to obtain the particular configuration of the desired logic function.

 A typical PLD may have hundreds to millions of gates interconnected through

hundreds to thousands of internal paths.
 In order to show the internal logic diagram of such a device in a concise form, it is
necessary to employ a special gate symbology applicable to array logic.

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 Figure 7.1 shows the conventional and array logic symbols for a multiple input OR
gate.
 Instead of having multiple input lines into the gate, we draw a single line entering
the gate.
 The input lines are drawn perpendicular to this single line and are connected to the
gate through internal fuses.
 In a similar fashion, we can draw the array logic for an AND gate.
 PLD consists of an array of AND and OR gates, which can be programmed to realize
the required logic function
 Inputs to the PLD are applied to a set of buffer/inverters. These devices have
both the true value of the input as well as the complemented value of the
input as its outputs.
 Outputs from these devices are the inputs to an array of and-gates. The AND
array generates a set of p product terms.
 The product terms are inputs to an array of or-gates to realize a set of m sum-
of-product expressions.
 One or both of the gate arrays are programmable.
 The logic designer can specify the connections within an array.
 PLDs serve as general circuits for the realization of a set of Boolean functions.
 PLD called a programmable logic device, it is a semiconductor device that can
be programmed to obtain required logic devices.
 The advantage of PLD is re-programmability, they have replaced special-
purpose different types of logic devices like logic gates, flip flop, counter, and
multiplexer in many semi-custom applications

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