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Assignment AEDE

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8 views2 pages

Assignment AEDE

Gh

Uploaded by

supriya sinha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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SUBJECT: Analog and Digital Electronics (3130907)

1) Simplify the following Boolean function using K-map F (w, x, y, z) = Σ m(1, 3, 7, 11,
15) with don’t care, d(w, x, y, z) = Σm(0,2,5)

2) Simplify the Boolean function F = A’B’C’+AB’D+A’B’CD’ using don’t-care conditions


d=ABC+AB’D’ in (i) sum of products and (ii) product of sums by means of Karnaugh map

3) Reduce using K-map


Σm(5,6,7,9,10,11,13,14,15)
ΠM(1,5,6,7,11,12,13,15)

4) Minimize using K-map


f(A,B,C,D) = Σ(1,3,4,6,8,11,15) +d(0,5,7)

5) Simplify equation using K-map : F(a,b,c,d) = Σm(3,7,11,12,13,14,15)


Realize the expression with minimum number of gates.

6) Minimize the following Boolean expression using K- Map and realize it using logic gates.
F(A,B,C,D)=Σm(0,1,5,9,13,14,15)+d(3,4,7,10,11)
7) Write short note on K-map. OR Explain K-map simplification technique.

8) What are SOP and POS forms of Boolean expressions? Minimize the following expression
using K-map
Y= Σm(4,5,7,12,14,15) + d( 3,8,10)

9) Give examples of standard and nonstandard SOP and POS forms. Explain how a NON standard
POS expression can be converted in to standard POS expression using example.

ASSIGNMENT: COMBINATIONAL LOGIC CIRCUITS


10) Explain full- subtractor in brief.

11) Explain how four bit combined binary adder and subtractor circuit can be constructed using full
adders?

12) Explain full adder circuit with the help of two half adders.

13) Write short note on half adder and full adder.

14) Draw truth table and logic diagram of 3 to 8 line decoder.

15) Explain in brief the working of decoders.

16) Explain octal to binary encoder.

17) Explain 2-bit magnitude comparator.


SUBJECT: Analog and Digital Electronics (3130907)

18) Discuss 4 – bit magnitude comparator.

19) Explain a parity generator and checker.

20) Design 3-bit odd parity generator circuit.

21) Describe multiplexer and de-multiplexer with circuit and application of each.

22) Implement a full adder using 8:1 multiplexer.

23) Implement the following Boolean function by using 8:1 MUX


F(A,B,C,D) = Σm(0,1,3,4,8,9,15).

24) Design a full adder circuit using decoder and multiplexer (4:1 MUX).

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