ECE/ENGRD 2300

Digital Logic and Computer Organization

Introduction to FPGAs
& the Verilog HDL

Spring 2024
 Learning Goals
• Understand FPGA’s structure and functionalities
• Verilog basics
– Signal, vectors, constants
– Operators, modules
– Wire, register types
• Verilog coding styles: structural v.s. behavioral
• Continuous assignment
• Procedural assignment
– Blocking v.s. non-blocking assignment
• Understand Verilog testbenches

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 Course Plan

• Lab 1: Display data with 7-segment display

– Build circuit using gates

• Labs 2-4: Hardware design using Verilog

– … and deploy on FPGAs

• Lab 5: Assembly programming

– … extension of Lab 4

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 Evolution of Design Abstractions
Results
?
(design productivity)

HDL (Verilog, VHDL)

Gate-level entry

Transistor-level entry

McKinsey S-Curve
Effort
(CAD tool effort)
Less human effort
ENGRD 2300
[source: Keutzer] FPGAs & Verilog Tutorial 4
 Hardware Description Languages
• Hardware Description Language(HDL)
– A language for describing hardware designs

• Advantages of HDLs
– Efficiently code large, complex designs
• Program at a more abstract level than schematics
• More readable than schematics
– EDA/CAD tools automatically generate hardware

• Industry standards
– Verilog
– VHDL
– SystemVerilog: a successor to Verilog, gaining
popularity
• Reading: Chapter 4
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 HDL-based Design Flow: Overview
• HDL code written to describe hardware after
brainstorming over a given problem

• HDL code, via testing scripts, can be simulated by

simulation tools.

• HDL code is synthesized by sophisticated compiler

tools into hardware circuits.

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 HDL-based Design Flow: Detailed Look
for extensive
functionality
testing

gradually more low-level to specific

representation of the circuit device e.g. FPGA

• Back-end differs by target technology The compilation tool is

– FPGA, ASIC, full-custom intelligent enough to
parse high-level circuit
descriptions, and can
also simplify logic
(recall K-Maps?)

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 FPGAs The platform to test/deploy
our designed hardware

• Field Programmable Gate Array [FPGA]

– is an Integrated Circuit (IC) that can be programmed in
the field *after* manufacturing.

Prototyping board with

peripherals and
everything required to
make the FPGA work

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 FPGA Structure
Inside a Logic Block

I/O blocks connected to

Stores Truth Tables Flip-flop storage
peripherals
element
[source: Brown/Vranesic DLD/Verilog Textbook]
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 Why FPGAs
• Parallel execution in hardware
• Reconfigurable unlimited no. of times
• Readily available boards so quick to develop
• HDL Code → Hardware with little manual effort

• Uses
– Accelerating/prototyping algorithms in hardware
– variety of fields like defense, medical, machine learning

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 FPGA Ecosystem
• Multiple vendors

We’ll use this in

our course

… among others
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 • Let’s look at a couple of Verilog programs mapped
to FPGAs

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 Recall Lab 1
• 4-bit Input I3
0
I2
0
I1
0
I0
0
Digit
0
to 7-Segment Decoder 0
0
0
0
0
1
1
0
1
2
0 0 1 1 3
0 1 0 0 4
• Digits 0-9 0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9

Each segment’s expression 𝒂 = 𝑰! + 𝑰" % 𝑰# + 𝑰$ % 𝑰# + 𝑰&$ % 𝑰&#

was derived using K-Maps
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 7-Segment Decoder

• Extended to all 16 inputs

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 Verilog code
For 7-Segment
Decoder

7 segments defined ON or
OFF for all 4-bit inputs

(straightforward & intuitive)

Let’s compile this code and see the

hardware mapping on the FPGA

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 Purely combinational circuit

4-bit Binary Input

Truth tables
for all 7
Gate Level Representation segments
of a single segment output

4-input Look-up Table

(Truth Table)
for a single segment
output

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 7 outputs connected
to 7-segment display

4 inputs connected
to switches

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 FPGA reads inputs
from switches and
determines the
output at 7-seg LEDs
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 Sequential circuit example

Result of compiling a T Flip-Flop in

Verilog (Prelab 2A)

D Flip-Flop storage element

as no direct T Flip-Flop available

Truth Table Logic determines

when to toggle/reset/retain
the D Flip-Flop value based
on inputs T and RESET

Notice the output feedback

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 VERILOG HDL

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 Verilog
• Developed in the early 1980s by Gateway Design
Automation (later bought by Cadence)

• Supports modeling, simulation, and synthesis

• We will use a subset of language features

– Synthesizable vs. non-synthesizable

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 Verilog HDL
• Verilog is not a computer programming language
• Verilog is not a computer programming language
• Verilog is not a computer programming language

• Verilog is a Hardware Description Language

– It describes hardware
– Things happen simultaneously / in parallel
– …. whereas software is sequential

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 Signal Values
• Verilog signals can have 1 of 4 values
– 0 Logical 0, or false
– 1 Logical 1, or true
– z High impedance, floating
– x Unknown logical value
• May be a 0, 1, z, in transition, or don’t cares.

You’ll be mostly concerned with Logical 0 and 1 only.

Actual hardware has levels 0 and 1 only.

X and Z values might arise in your simulation tool.

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 Vectors
• Multi-bit values are represented as bit vectors
(grouping of 1-bit signals)
– Right-most bit is least significant
– Example
• input [7:0] byte1, byte2, byte3;

• Common operations on bit vectors

– Bit selection
• byte1[5:2] or Zbus[3:7]
– Concatenation
• {byte1,byte2}
– Bitwise Boolean operators
• byte1 & byte2
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 Constants

• Binary constants
4’b1001 – 8’b00000001
– 4’b0111

• Decimal constants
– 4’d10
Base (b, d, h, o)
– 8’d345
– 32’d65536
Decimal number representing bit width

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 Operators
• Bitwise Boolean operators
~ NOT
Operate bit-by-bit on multi-bit signals
& AND
^ Exclusive OR
| OR

• Arithmetic operators
+ Addition / Division << Shift left
– Subtraction % Modulus >> Shift right
* Multiplication

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 Verilog Program Structure
module
• System is a collection of
modules
declarations
– Module corresponds to a
single piece of hardware
statements

• Declarations
– Describe names and types of inputs and outputs
– Describe local signals, variables, constants, etc.

• Statements specify what the module does

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 Verilog Program Structure
module V2to4dec( i0,i1,en,y0,y1,y2,y3 ); List of inputs and outputs
input i0,i1,en;
Structural Coding Style
output y0,y1,y2,y3; Declarations
wire noti0,noti1;

not U1(noti0,i0);
not U2(noti1,i1);
and U3(y0,noti0,noti1,en);
Statements
and U4(y1, i0,noti1,en);
and U5(y2,noti0, i1,en);
and U6(y3, i0, i1,en);
endmodule

In Declarations, can have something like: input [3:0] B;

This would be a 4-bit bus, with individual wire names
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B[0] (LSB), B[1], B[2], B[3] (MSB) FPGAs & Verilog Tutorial 28
 module A

Verilog declarations

Hierarchy statements

Module B Module C
A module can
instantiate declarations declarations

other modules inside, statements statements

forming a module
hierarchy
Module D

Akin to programming language ‘classes’

instantiating objects of other classes declarations

statements

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 Verilog Programming Styles
• Structural You just saw this a couple of slides ago

– Textual equivalent of drawing a schematic

– Uses instance statements to instantiate other modules
and uses wires to connect them

• Behavioral More efficient - we’ll mostly use this style in our labs

– Specify what a module does with a high-level description

– Uses procedural code (e.g., in always blocks) or
continuous assignment (i.e. assign) constructs

We can mix the structural and behavioral styles

in a Verilog design
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 Net and Variable Types
• Verilog provides multiple net and variable types
You must be clear on their usage!
• We will main use two types They’re a common source of errors.

– wire: represents a physical connection (net) between hardware elements

• Used for structural style and continuous assignments
• Default if you do not specify a type
• Can only be used to model combinational logic
• Cannot be used in the left-hand side in an always block

– reg: a variable that can be used to store state (registers)

• Used in the procedural code (always blocks)
• May also be used to express combinational logic
• Can be used to model both combinational & sequential logic
• Cannot be used in the left-hand side of a continuous assignment statement

More on this later.

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 Internal Wires
• Sometimes it is useful to name internal signals and
assign intermediate values
– Declaration:

wire temp_value;

– Assignment:

assign temp_value = some_statement;

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 Example: 2-to-1 MUX
• select = Selector signal
• If select = 0, out = x
• If select = 1, out = y out = select’ x + select y
select x y out
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

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 Structural Style
module MUX2_1 (x, y, select, out);
input x, y; inv_sel
input select;
output out; tx
Internal wires
used to connect
x
wire inv_sel, tx, ty; gates.

y out
NOT not0(inv_sel,select);
AND and0 (tx, x, inv_sel);
AND and1 (ty, y, select);
ty
OR or0 (out, tx, ty);
select
endmodule
The order of the gates instantiation does not matter.
Essentially describing the schematic textually.

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 Structural Practice Example
module mycircuit( ); A
input A, B, C; B F
output F; C

nand U1( );

….

endmodule

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 Structural Practice Example
module mycircuit(A, B, C, F ); A
input A, B, C; B F
output F; C temp
wire temp;

nand U1(temp, B, C);

nand U2(F, A, temp);

endmodule

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 Behavioral Coding Style

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 Behavioral Coding Style:
Continuous Assignments
• An assign statement represents continuously
executing combinational logic
module MUX2_1 (x, y, select, out);
input x, y;
input select; Output out is a wire
output out; by default.

assign out = (~select & x) | (select & y);

endmodule Assign used to set

values for wires

• Multiple continuous assignments happen in parallel; the

order does not matter
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 Continuous Assignments
• An assign statement means continuously executing
combinational logic
– LHS must be a wire type
– RHS is recomputed when a value in the RHS changes
– The new value of the RHS is assigned to the LHS

• Example:
– assign y0 = en & ~i0 & ~i1;

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 Behavioral Coding Style:
Combinational Logic with Always Blocks
module MUX2_1 (x, y, select, out); • An always block is
input x, y; reevaluated whenever a
input select; signal in its sensitivity
output reg out; list changes

always @(x, y, select) • Formed by procedural

begin assignment statements
out = (~select & x) | (select & y); – LHS inside the always
end block must be reg

endmodule

Here, the signal is a ‘reg’ even though modeling combinational logic!

reg can be used to model both combinational and sequential logic.

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 This is Behavioral Style Too!
module MUX2_1 (x, y, select, out);
• Closely resembles
input x, y;
verbal circuit
input select; description!
output reg out;
• High-level and intuitive.
always @(x, y, select)
begin Conditional Statement • Synthesis Tool is
if (select == 0) intelligent enough to be
out = x; able to infer a mux!
else
out = y;
end

endmodule

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 Conditionals
• Logical operators used in conditional expressions
– && logical AND
– || OR
– ! logical NOT
– == logical equality
– != logical inequality
– > greater than
– >= greater than or equal
– < less than
– <= less than or equal
• Don’t confuse with Bitwise Boolean operators

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 Concurrent Elements/Blocks
module temp (…..);
input …;
output …;
• Always blocks execute
assign … = ...; concurrently with other
always blocks, instance
always @(…)
begin … statements, and
end continuous assignment
statements in a module
always @(…)
begin …
end

endmodule

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 Sensitivity Lists in Always Blocks
• Include every variable in the always block
sensitivity list
– always @ (signal list)

• Simple alternative
– always @ (*) Used to describe Combinational Logic

• For edge-triggered behavior

– always @ (posedge/negedge SIGNAL_NAME)
Used to describe Sequential Logic
More later!

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 Assignments in Verilog
• Continuous assignments apply to combinational
logic only

• Always blocks contain a set of procedural

assignments (blocking or non-blocking)
– Can be used to model either combinational or
sequential logic
– Always blocks execute concurrently with other always
blocks, instance statements, and continuous
assignment statements in a module

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 Procedural Statements
• Procedural statements are similar to conventional
programming language statements
– Begin-end blocks
•begin procedural-statement … procedural-statement end

– If You saw this in the Behavioral example.

•if ( condition ) procedural-statement else procedural-statement
– Case
•case ( sel-expr ) choice : procedural-statement … endcase

– Blocking assignment
•variable name = expression ; More later!
– Nonblocking assignment
•variable name <= expression ;

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 • So far you’ve seen how to implement
combinational logic.
– output as a function of input
– determined using logic gates

• Now for sequential logic…

– introduce storage elements like latches, flip-flops

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 Sequential Logic in Always Blocks
reg Q;

always @( clk, D ) D Q • Sequential

begin C logic can only
if ( clk ) be modeled
Q <= D; D latch using always
end blocks

always @( posedge clk )

• Thus, Q must
D Q
begin be declared as
Q <= D; CLK a “reg”
end DFF

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 Flip-Flop with a reset?
reg q; Rising clock edge
Asynchronous
always @ (posedge clk or posedge reset) Reset
if (reset==1) in between
clock edges
q <= 1’b0;
else
q <= d;
Flip-Flop assignment

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 Flip-Flop with a reset?
reg q; Rising clock edge
Synchronous Reset
always @ (posedge clk)
if (reset==1)
q <= 1’b0;
else
q <= d;
Flip-Flop assignment

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 Blocking Assignments
• Blocking assignments ( = )
– Simulation behavior: Right-hand side (RHS) evaluated
sequentially; assignment to LHS is immediate
reg Y, Z;
always @ (posedge clk)
begin
Y = A & B; Y and Z are flip-flops
Z = ~Y; in actual hardware
end
Blocking assignments
Simulator interpretation Resulting circuit (post synthesis)
Ynext = A & B A
B
Znext = ~(A & B)

Y Z

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 Nonblocking Assignments
• Nonblocking assignment ( <= )
– Simulation behavior: RHS evaluated in parallel (order doesn’t
matter); Assignment to LHS is delayed until end of always block
reg Y, Z;
always @ (posedge clk)
begin
Y <= A & B; Y and Z are flip-flops
Z <= ~Y; in actual hardware
end
Nonblocking assignments
Simulator interpretation Resulting circuit (post synthesis)
Znext = ~Y // reading the old Y A
B
Ynext = A & B

Y Z

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 Rules to Follow
• Use blocking assignments to model combinational logic
within an always block.
– or just implement combinational without an always block, using assign statements

• Use non-blocking assignments to implement sequential

logic.

• Do not mix blocking and non-blocking assignments in the

same always block.

• Do not make assignments to the same variable from more

than one always block

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 VERILOG TESTBENCHES

To extensively test our HDL design using

simulations before deploying it in hardware

We should have a comprehensive test case

coverage (including edge cases)

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 Why Testbenches?
• Generate stimulus i.e. test inputs
• Monitor UUT (Unit Under Test) output
and hope it matches the expected output

• Automation
Verilog Testbench

UUT Verilog UUT

Stimulus UUT Monitor

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 Testbenches vs. Hardware
• Important distinction
– Verilog testbenches DO NOT describe hardware (i.e.,
non-synthesizable)
– Verilog testbenches look like a software program

e.g. we frequently use ‘delays’

Verilog in testing when applying new
test inputs, and print out
signal values in the output log
Synthesizable
subset Clearly such features are only
relevant to simulation, they
CAN’T translate to hardware

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 Building Blocks of a Testbench
• Timescale
• Module definition
• UUT instantiation
• Stimulus generation
• Monitoring output

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 Timescale
• Specifies the simulation granularity
• Syntax
`timescale time_unit base / precision base
unit of delays for fractional delay

• Example
// sets the granularity at which we simulate
`timescale 1 ps / 1 ps

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 Test Module Definition
• A testbench is a module too!
• No inputs or outputs

module treg4bit_test();

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 Module Declarations
• Define input and output signals that will link to our
UUT
// inputs
reg CLK50;
reg RESET;
reg [3:0] IN;

// outputs
wire [3:0] OUT;

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 UUT Instantiation
• Same as instantiating a submodule
// instance of treg4bit
treg4bit UUT (
.CLK(CLK50),
.RESET(RESET),
.IN(IN),
.OUT(OUT)
);
Verilog Testbench

UUT Verilog UUT

Stimulus UUT Monitor

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 Stimulus Generation: Clock
• Generate a 50MHz clock

always
begin
CLK50 = 1'b0;
CLK50 = #10000 1'b1;
#10000;
end
#10000 means a delay i.e. wait
for 10000 time units before
changing the value of CLK50

The total time period is 20000

time units

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 Stimulus Generation: Initial Block
• Use initial block to write sequential test cases for
the circuit

initial
begin

// reset circuit
...

// test cases
...

end

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 Stimulus Generation: Reset
• At beginning of initial block, give initial values to the
circuit

// reset circuit
RESET = 1'b1;
IN = 4'b0;

#20000;
// test whether reset is correct
...

// enable and start running

RESET = 1'b0;

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 Stimulus Generation: Set Inputs
• Set inputs to values for the test case

// enable toggling for only some of the flip-flops

IN = 4'b0011;

#20000; // wait a cycle to observe result

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 Monitoring Output
• Compare actual output with expected output
• Display information
if(OUT == 4'b0) begin
$display("MSIM> Reset is correct, OUT (value in
register) now %4b", OUT);
end
else begin
$display("MSIM> ERROR: Reset is incorrect. OUT
(value in register) should be 0000, but is %4b",
OUT);
end

• Can also use waveforms to see inputs and outputs

change over time
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 Input/Output
signals Waveform display

Testbench output i.e.

print/display statements

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 Pause/Terminate simulation
• Pause simulation (can resume later)

$stop;

• Terminate simulation

$finish;

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 Learning Goals
• Understand FPGA’s structure and functionalities
• Verilog basics
– Signal, vectors, constants
– Operators, modules
– Wire, register types
• Verilog coding styles: structural v.s. behavioral
• Continuous assignment
• Procedural assignment
– Blocking v.s. non-blocking assignment
• Understand Verilog testbenches

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