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Cao 12

Lab

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28 views12 pages

Cao 12

Lab

Uploaded by

rehanmunir276
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Computer Architecture and Organization

Lab No: 12

Name: Rehan Munir Awan


Enrollment No: 01-132222-036
Date: 13-June-2024
Submitted To: Mam Maryam Hassan

DEPARTMENT OF COMPUTER ENGINEERING


BAHRIA UNIVERSITY ISLAMABAD
CAMPUS
OBJECTIVE:
The Verilog Design of 16-bit RISC Processor-I lab aims to immerse
students in the foundational principles of designing and implementing
a RISC (Reduced Instruction Set Computing) processor using Verilog
HDL (Hardware Description Language). Throughout this lab, students
will embark on a journey to understand the core tenets of RISC
architecture, emphasizing simplicity in instruction set design and
efficient execution strategies. They will begin by designing crucial
components such as registers, the Arithmetic Logic Unit (ALU),
control units, and the data path in Verilog, fostering hands-on
proficiency in digital circuit design. Central to the lab is the creation
of a 16-bit instruction set architecture (ISA) tailored for the RISC
processor, encompassing a spectrum of instructions from arithmetic
and logical operations to memory access and control flow.
SOFTWARE USED:
 ISE Design.

Introduction:
In the rapidly evolving landscape of digital design and computer
architecture, understanding the intricacies of processor design is
fundamental. The Verilog Design of 16-bit RISC Processor-I lab
serves as a foundational exploration into the realm of RISC (Reduced
Instruction Set Computing) processors, leveraging Verilog HDL
(Hardware Description Language) as the primary tool for
implementation. This lab introduces students to the fundamental
concepts and methodologies involved in designing and simulating a
16-bit RISC processor, aiming to equip them with practical skills and
theoretical insights. The lab begins by familiarizing students with the
underlying principles of RISC architecture, emphasizing its
streamlined instruction set design and efficient execution strategies.
Verilog code for the RISC processor:
1. Verilog code for Instruction Memory :
`include "Parameter.v"
// Verilog code for RISC Processor //
Verilog code for Instruction Memory
module Instruction_Memory( input[15:0]
pc, output[15:0] instruction
);
reg [`col - 1:0] memory [`row_i - 1:0];
wire [3 : 0] rom_addr = pc[4 : 1]; initial
begin
$readmemb("./test/test.prog", memory,0,14); end
assign instruction = memory[rom_addr];
CEL-221 Computer Architecture & Organization Lab Page
endmodule

2. Verilog code for register file:


`timescale 1ns / 1ps
// Verilog code for RISC Processor
// Verilog code for register file
module GPRs( input clk,
// write port
input reg_write_en, input [2:0]
reg_write_dest, input [15:0]
reg_write_data, //read port 1
input [2:0] reg_read_addr_1,
output [15:0] reg_read_data_1,
//read port 2 input [2:0]
reg_read_addr_2, output [15:0]
reg_read_data_2
);
reg [15:0] reg_array [7:0];
integer i; // write port //reg
[2:0] i; initial begin
for(i=0;i<8;i=i+1)
reg_array[i] <= 16'd0;
end always @ (posedge clk ) begin
if(reg_write_en)
begin reg_array[reg_write_dest] <= reg_write_data;
end
end
CEL-221 Computer Architecture & Organization Lab Page
assign reg_read_data_1 = reg_array[reg_read_addr_1]; assign
reg_read_data_2 = reg_array[reg_read_addr_2];
endmodule

3. Verilog code for Data Memory:


`include "Parameter.v"
// Verilog code for RISC Processor
// Verilog code for data Memory
module Data_Memory( input clk,
// address input, shared by read and write port input
[15:0] mem_access_addr,
// write port
input [15:0]
mem_write_data, input
mem_write_en, input
mem_read,
// read port
output [15:0] mem_read_data
);
reg [`col - 1:0] memory [`row_d - 1:0]; integer f;
wire [2:0] ram_addr=mem_access_addr[2:0];
initial
begin
$readmemb("./test/test.data", memory);
CEL-221 Computer Architecture & Organization Lab Page
f = $fopen(`filename);
$fmonitor(f, "time = %d\n", $time,
"\tmemory[0] = %b\n", memory[0],
"\tmemory[1] = %b\n", memory[1],
"\tmemory[2] = %b\n", memory[2],
"\tmemory[3] = %b\n", memory[3],
"\tmemory[4] = %b\n", memory[4],
"\tmemory[5] = %b\n", memory[5],
"\tmemory[6] = %b\n", memory[6],
"\tmemory[7] = %b\n", memory[7]);
`simulation_time;
$fclose(f); end always
@(posedge clk) begin if
(mem_write_en) memory[ram_addr] <=
mem_write_data; end
assign mem_read_data = (mem_read==1'b1) ? memory[ram_addr]:
16'd0;
endmodule
Tasks No: 01
Implement instruction memory, data memory and register file of
RISC processor in Verilog using xilinx ISE and attach output.
Code:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
CEL-221 Computer Architecture & Organization Lab Page
// Create Date: 08:00 30/05/2023 //
Design Name:
// Module Name: Programcounter //
Project Name:
// Target Devices:
// Tool versions:
// Description:
// Dependencies:
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//////////////////////////////////////////////////////////////////////////////////
module programcounter(
input rst, input clk,
input PCselect, input
[31:0] immediate,
input writemem,
output [31:0] PCout
);
reg [31:0] nextins;
always@(posedge clk or posedge rst)
begin
if(rst)
nextins<=32'b0; // PCout=0
else if(writemem==0)
begin
if(PCselect==1)
begin
nextins<=PCout+4;
end
else
nextins<=PCout+immediate;
end
end
assign PCout=nextins;
endmodule
`timescale 1ns / 1ps module
Instructionmemory(
input [31:0] insnumber, input writemem, // if writemem is 1 then we
write instowrite to memory input [31:0] instowrite, input [31:0]
insnumbertowrite, input clk,
output reg [31:0] currentins
);
reg [7:0]insmem[499:0]; always@(posedge clk)
begin if(writemem==1) begin
insmem[insnumbertowrite]<=instowrite[7:0];
insmem[insnumbertowrite+1]<=instowrite[15:8];
insmem[insnumbertowrite+2]<=instowrite[23:16];
insmem[insnumbertowrite+3]<=instowrite[31:24];
end else
begin
currentins[7:0]<=insmem[insnumber];
currentins[15:8]<=insmem[insnumber+1];
currentins[23:16]<=insmem[insnumber+2];
currentins[31:24]<=insmem[insnumber+3];
end end endmodule
`timescale 1ns / 1ps module
riscblk(
input clk, input rst,
input writemem, input
[31:0] instowrite, input
[31:0] insnumtowrite,
output [31:0] currentins
);
wire PCselect , immediate; wire [31:0]PCout;
assign PCselect=1; assign immediate=6; programcounter
PC(.rst(rst),.clk(clk),.writemem(writemem),
.PCselect(PCselect),.immediate(immediate),
.PCout(PCout));
Instructionmemory IM(.insnumber(PCout),.writemem(writemem),
.instowrite(instowrite),.insnumbertowrite(insnumtowrite),
.clk(clk),.currentins(currentins));
Endmodule
`timescale 1ns / 1ps
module DataMemory(
input [31:0] Address,
input [31:0] WriteData,
CEL-221 Computer Architecture & Organization Lab Page
input clk,
input MemRead,
input MemWrite,
output reg [31:0] DataOut
);

reg [7:0]datamem[600:0];
always@(posedge
clk) begin
if(MemRead)
begin
datamem[Address+0]<=WriteData[7:0];
datamem[Address+1]<=WriteData[15:8];
datamem[Address+2]<=WriteData[23:16];
datamem[Address+3]<=WriteData[31:24];
end
else if(MemWrite)
begin
DataOut[7:0]<=datamem[Address+0];
DataOut[15:8]<=datamem[Address+1];
DataOut[23:16]<=datamem[Address+2];
DataOut[31:24]<=datamem[Address+3];
end
end
endmodule
Output:

Conclusion:
The Verilog Design of 16-bit RISC Processor-I lab has provided
students with a comprehensive introduction to the principles and
practices of designing a RISC (Reduced Instruction Set Computing)
processor using Verilog HDL (Hardware Description Language).
Throughout this lab, students have navigated through the complexities
of RISC architecture, focusing on the efficient execution of
instructions and the streamlined design of the instruction set. Starting
from the fundamental components such as registers, the Arithmetic
Logic Unit (ALU), control units, and the data path, students have
gained practical experience in translating theoretical concepts into
functional digital circuits.

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