Academic year 2024-25 July Dec 2024

Batch 2021-25

Shri G. S. Institute of Technology and Science

Department of Electronics and Instrumentation Engineering
B. Tech. IV Year SEM-A (4-YDC)
EI47053: PROCESS INSTRUMENTATION

HOURS PER CREDITS MAX. MARKS

WEEK
T P TU T P TU THEORY PRACTICAL TOTAL
MARKS
CW END SW END
3 2 1 3 1 - SEM SEM 200
30 70 40 60

PRE-REQUISITE: Knowledge of Sensors and Transducers, Control Systems.

COURSE OBJECTIVES: The purpose of this course is to

1. Apply key concepts of automatic control and instrumentation to process plants.
2. Expose the students to the advanced control methods used in industries and research.
3. Familiarize the students with PID tuning and PLC ladder diagram used in process plants.

COURSE OUTCOMES: After completion of course, the students should be able to:
1. CO1: Analyse process control system and evaluation.
2. CO2: Explain the application of pneumatic, hydraulic & controller in control systems.
3. CO3: To describe PLC and ladder programming for designing various logics.
4. CO4: To discuss final control elements.
5. CO5: To employ PLC and ladder programming to real world scenario.

COURSE CONTENTS:
THEORY:

UNIT-I: Introduction to process control. Control system Evaluation, Objective. ON-OFF control.
Time proportional control, proportional control, Integral control, Derivative control, Typical PID
controller characteristics and related terminology.

UNIT-II: Pneumatic controller: P, PD, PI, PID controllers. Hydraulic controller: P, PI, PD, PID
controller, electronic controller. Complex control schemes: ratio control systems, split range controls,
cascade controls, feed forward control. Tuning of controllers: Ziegler-Nicolas methods and other
methods.

UNIT-III Introduction to programmable logic controllers: Evolution, basic block diagram,

characteristics, advantages, types, PLC Vs PC. Ladder diagram, Ladder design, development of
Ladder diagrams for various logic gates, logics. PLC timers and counters, Application of PLCs:
Industrial applications.

UNIT-IV: Final control elements: Mechanical, Electrical, Fluid valves: control valve principles,
valve sport and plug and characteristics, control valve types, Valve sizing and selection. Type of
actuators: Pneumatic actuators, Hydraulic actuators.

UNIT-V: Feedback and connecting elements in the loop flow, pressure level and temperature control
loop, Pneumatic transmission, electric transmission, Thermal element lag, pressure element lag.
 Academic year 2024-25 July Dec 2024
Batch 2021-25

ASSESMENT:
Continuous evaluation of students through: Class attendance, Assignments, organizing
Seminars/Quizzes and two mid Semester Tests Exam with weightage of 30% of total marks. End
semester theory exam. Weight age is 70% of total marks.

TEXT BOOKS:
1. Donald P. Eckman, “Automatic Process Control”, Wiley India Pvt. Ltd., 2009.
2. D. Patranabis, “Principles of Process Control”, Third Edition, Tata McGraw Hill, 2012.
3. Curties D. Johnson, “Process Control Instrumentation Technology”, Eighth Edition, Pearson,
2005.

REFERENCE BOOKS:
1. S. K. Singh, “Industrial Instrumentation and Control”, Third Edition, Tata McGraw Hill,
2010.
2. Madhuchhanda Mitra and Samarjit Sen Gupta, “Programmable Logic Controller and
Industrial Automation: An Introduction” Penram International Publishing, 2008.

CO-PO Articulation Matrix

CO-PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 2 2 2 2 - 1 - - - - 1
CO2 3 2 1 3 2 - - - - - - 2
CO3 3 1 2 2 1 - - - - - - 2
CO4 3 2 1 1 1 - - - - - - -
CO5 3 2 1 2 3 - 1 - - - - 2
Avg. 3 1.8 1.4 2 1.8 - 1 - - - - 1.75

LABORATORIES OBJECTIVES:
1. To familiarize the students with the measurement and control of various process loops like
flow, level, temperature etc.
2. To provide hands-on experimentation of PID controller tuning for various parameters.
3. To enable the student to gain knowledge of ladder programming with PLC.

LABORATORY OUTCOMES: After completing the lab session, the student will be able to:
1. CO1: Analyse pressure-displacement characteristics of Flapper-Nozzle system.
2. CO2: Perform the measurement and control of flow, level and temperature loops using PID
controller.
3. CO3: Analyse the cascade control loop of Flow-level.
4. CO4: Analyse the feedback pressure control loop.
5. CO5: Design the ladder diagram for PLC based lift elevator, bottle filling system.

LIST OF EXPRIMENTS:
1. To obtain Pressure-displacement characteristics of Flapper Nozzle amplifier.
2. To measure flow of liquid in flow control loop and to maintain constant flow using PID
control.
3. To measure level of liquid in level control loop and to maintain constant level in a tank using
PID control.
4. To measure and control the temperature of heating fluid in heat exchanger loop using PID
control.
5. To perform the analysis of cascade control loop of Flow-level.
6. To perform the analysis of feedback pressure control loop.
7. To perform the analysis of feedback level control loop.
 Academic year 2024-25 July Dec 2024
Batch 2021-25

8. Implement the different logic functions using PLC ladder diagram.

9. Implement the rotary bottle filling logic using ladder diagram on PLC.
10. Design ladder diagram for ON-OFF level control and verify it using PLC.
11. Design and implement PLC based Lift simulator using ladder diagram.

ASSESMENT:
Evaluation of students through Continuous performance analysis of students based on experiment
performance, File preparation, internal viva and file submission with weightage of 40% of total marks
and End Semester practical Examination (external viva) with weightage of 60% of total marks.

CO-PO Articulation Matrix for LAB

CO-PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 3 2 2 - - - - - - -
CO2 3 3 2 2 2 - - - - - - -
CO3 3 2 2 2 1 - - - - - - -
CO4 3 2 2 1 1 - - - - - - -
CO5 3 2 2 1 1 - -- - -- - -- --
Avg. 3 2.4 2.2 1.6 1.4 - - - - - - -

Shri G. S. Institute of Technology and Science

Department of Electronics and Instrumentation Engineering
 Academic year 2024-25 July Dec 2024
Batch 2021-25

B. Tech. IV Year SEM-A (4-YDC)

EE47002: POWER ELECTRONICS
HOURS PER CREDITS MAX. MARKS
WEEK
T P TU T P TU THEORY PRACTICAL TOTAL
MARKS
CW END SW END
3 - - 3 - - SEM SEM 100
30 70 - -

PRE-REQUISITE: Basic knowledge of Electronics and semiconductor devices.

COURSE OBJECTIVES:
1. To provide students a deep insight into the operational behaviour of practical power switching
devices with respect to their static and dynamic characteristics.
2. To learn the working principle of classified topologies of Thyristor based AC/DC, AC/AC,
DC/DC and DC/AC converters.
3. To design and analyse the operation of above converters considering their applications.
4. To understand design of firing circuits for Thyristor based line commutated converters.

COURSE OUTCOMES:
1. CO1: EE47002(T).1: Acquire knowledge about fundamental concepts and switches used in
power electronics.
2. CO2: EE47002(T).2: Ability to analyse various single phase and three phase line commutated
power converter circuits and understand their applications.
3. CO3: EE47002(T).3: Nurture the ability to identify basic requirements for line commutated
converter-based design application.
4. CO4: EE47002(T).4: To develop skills to build and troubleshoot power electronics circuits.
5. CO5: EE47002(T).5: Understand the firing circuit design for line commutated converters.
6. CO6: EE47002(T).6: Foster ability to understand the use of line commutated converters in
professional engineering.

COURSE CONTENTS:
THEORY:

UNIT-I
Static power devices: Thyristor family, two transistor analogy of SCR, construction, characteristics,
parameters, turn on and turn off methods, firing circuits, isolation and amplifier circuits,
synchronization circuits.

UNIT-II
Static power devices: Thyristor family, two transistor analogy of SCR, construction, characteristics,
parameters, turn on and turn off methods, firing circuits, isolation and amplifier circuits,
synchronization circuits.

UNIT-III
DC to DC converter: Basic principle of chopper circuits, various chopper circuits and their working,
step up chopper, performance analysis.

UNIT-IV
 Academic year 2024-25 July Dec 2024
Batch 2021-25

Inverters: CSI and VSI inverters, single phase inverters, principle of operation, voltage and frequency
control techniques.

UNIT-V
Industrial Application of Power Electronics, SMPS, UPS, AC and DC drives, Power Supplies.

ASSESMENT:
A. Continuous evaluation through two mid-term tests with a weightage of 30% of the total marks. It
includes class attendance as well as assignments on the course topics. B. The end-term theory
examination weight age is 70%.

TEXT BOOKS:
1. M H Rashid, “Power Electronics Circuits, Devices, and Applications”, Third edition
Pearson/Prentice Hall, 2009.
2. Ned Mohan, “Power Electronics: Converters, Applications, and Design”, Third edition, John
Wiley & Sons Inc, 2007.
3. Joseph Vithayathil, “Power Electronics Principles and applications”, Tata McGraw-Hill,
1995.

REFERENCE BOOKS:
1. C. M. Pauddar, “Semiconductor Power Electronics (Devices and Circuits)”, First edition, Jain
Brothers New Delhi, 1999.
2. M. H. Rashid, “Handbook of Power Electronics‖”, Pearson Education India, 2008.
3. M. D. Singh, K. B. Khanchandani, “Power Electronics”, Tata McGraw-Hill, 2008.

CO-PO Articulation Matrix

CO-PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 - - - - - - - - - -
CO2 3 3 3 1 - - - - - - - -
CO3 3 3 - - - - - - - - - -
CO4 3 3 3 - - - - - - - - -
CO5 3 3 3 - - - - - - - - -
Avg. 3 3 3 1 - - - - - - - -

LABORATORIES OBJECTIVES: Following are the objective of the course:

1. Show awareness about operating behaviour of various static switches used in converters.
2. Understand the basic requirements in design of power converters.
3. Analyse performance parameters of various power converters.

LABORATORY OUTCOMES: Students will be able to:

1. CO1: EE42007 (P).1: Recognize the functions of CRO, identify and select proper instruments
to observe and record performance on different experimental set ups of power electronics
laboratory.
2. CO2: EE42007 (P).2: Establish wiring and device connections to assemble experiments of
static switches, line commutated, DC-DC converters and record their performances.
3. CO3: EE42007 (P).3: Analyse and compare the performance of various firing pulse
generation circuits for triggering and Commutation circuit of SCR.
 Academic year 2024-25 July Dec 2024
Batch 2021-25

4. CO4: EE42007 (P).4: Apply professional quality textual and graphical tools to sketch and
computing results, incorporating accepted data analysis and synthesis methods, mathematical
software, and word‐processing tools.
5. CO5: EE42007 (P).5: Ability to work in individual and in group following engineering
practices. Ability to interact effectively on a social and interpersonal level, divide up and share
task responsibilities to complete assignments.

LIST OF EXPRIMENTS:
1. Verification of steady state characteristics of different static switches.
2. Phase control of TRIAC using DIAC and RC circuit in light dimming circuit.
3. Firing pulse generation using UJT based relaxation oscillator.
4. Observe the performance of a TCA-785 based triggering circuit used for single phase-
controlled converter.
5. Performance evaluation of single-phase uncontrolled converter for R, RL load
6. Performance evaluation of single-phase controlled converter for R, RL load.
7. Performance Analysis of step-down chopper.
8. Performance evaluation of current commutation circuit for SCR.
9. Performance evaluation of voltage commutation circuit for SCR.
10. Effect of duty cycle on the output voltage of buck-boost converter.

ASSESMENT:
A. Continuous evaluation of laboratory journals with a weightage of 30%. It includes lab attendance
as well as experiments performed in the lab. B. The end-term practical examination weightage is
70%.

CO-PO Articulation Matrix for LAB

CO-PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 2 3 3 3 3 - 3 3 2 - -
CO2 3 - 3 3 3 3 - 3 3 - -
CO3 3 2 - 3 3 3 - 3 3 2 - -
CO4 3 2 3 3 3 3 - 3 3 2 - -
CO5 3 - - 3 3 3 - 3 3 - - -
Avg. 3 2 3 3 3 3 - 3 3 2 - -

Shri G. S. Institute of Technology and Science

Department of Electronics and Instrumentation Engineering
 Academic year 2024-25 July Dec 2024
Batch 2021-25

B. Tech. IV Year SEM-A (4-YDC)

EI47055: VLSI DESIGN

HOURS PER CREDITS MAX. MARKS
WEEK
T P TU T P TU THEORY PRACTICAL TOTAL
MARKS
CW END SW END
3 2 - 3 1 - SEM SEM 200
30 70 40 60

PRE-REQUISITE: Knowledge of Digital Circuit and Basics of Semiconductors is required.

COURSE OBJECTIVES:
1. To nurture the students with CMOS digital logic design.
2. To provide the students with the knowledge of trade-off between speed, power and area in
CMOS digital VLSI design.
3. To provide enough knowledge to students for digital logic design with FSM.

COURSE OUTCOMES: After completion of course, the student will be able to:
1. CO1: Explain importance of MOS transistor in designing VLSI circuits.
2. CO2: Implement and analyse CMOS Inverter for static & dynamic characteristics.
3. CO3: Design and analyse Dynamic and Domino logic.
4. CO4: Design FSM using Mealy and Moore machines.
5. CO5: Classify memory systems and differentiate between custom and semi-custom design.

COURSE CONTENTS:
THEORY:

UNIT-I Review of MOS, PMOS, NMOS, MOS device design equations, Short Channel and Narrow
Channel Width Effects. MOS small signal and large signal model, MOS capacitances, Technology
Scaling.

UNIT-II Basics of CMOS: Analysis of different types of inverter circuit, CMOS inverter, transfer
characteristic, calculation of propagation delay, rise time, fall time, noise margin and power
dissipation for CMOS Inverter. Effect of threshold voltage and supply voltage on Delay and power
dissipation.

UNIT-III CMOS logic structures: Domino logic, NP Zipper Logic, CVSL, DVSL. Basics of VLSI
Design, implementation of Logic functions, rise time/ fall time/ delay time considerations. Fan-in,
fan-out, standard cell design, cell libraries.

UNIT-IV FSM Design: State machines, Mealy & Moore machines, state diagrams, state table
reduction techniques for state tables, transition tables, design of sequential circuits using FSMs,
VHDL coding for FSMs.

UNIT-V Memory based subsystem design, Static RAM, Dynamic Ram, Full custom and Semi-
custom design, Clocking strategies, Clocked system, Latch and Resistors, System timing, two phase
clocking, four phase clocking.
 Academic year 2024-25 July Dec 2024
Batch 2021-25

ASSESMENT: Continuous evaluation of students through: Class attendance, Assignments,

organizing Seminars/Quizzes and two mid Semester Tests Exam with weightage of 30% of total
marks. End semester theory exam. Weight age is 70% of total marks.

TEXT BOOKS:
1. Neil H. E. West and Kamran Eshraghain, “Principles of CMOS VLSI Design: A Systems
Perspective”, Second Edition, Pearson, 1993.
2. Wayne Wolf, “Modern VLSI Design: Systems on Silicon”, Second Edition, Prentice Hall,
1998.
3. Jan M Rabaey, Anantha Chandrakasan and Borivoje Nikolic, “Digital Integrated Circuits: A
Design Perspective”, Second Edition, Pearson, 2016.

REFERENCE BOOKS:
1. Charles H. Roth and Larry L. Kinney, “Fundamentals of Logic Design”, Seventh Edition, Cl
Engineering Publishers, 2013.
2. Adel S. Sedra and Kenneth C. Smith, “Microelectronic Circuits”, Seventh Edition, Oxford
University Press, 2017.
3. S. Brown and Z. Vranesic, “Fundamentals of Digital Logic with VHDL”, Third Edition, Mc-
Graw Hill, 2017.

CO-PO Articulation Matrix

CO-PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 1 - - - - - - - - - -
CO2 3 2 2 2 3 - - - - - - -
CO3 3 3 - 2 2 - - - - - - -
CO4 3 2 2 2 3 - - - - - - -
CO5 3 3 2 2 2 - - - - - - -
Avg. 3 2.2 2 2 2.5 - - - - - - -

LABORATORIES OBJECTIVES:
1. Demonstrate the ability to use Cadence EDA tool for CMOS circuit design.
2. Students will be given hands-on of Virtuoso schematic and layout of CMOS circuits.
3. Students will be provided with a hands-on Spectre simulator for simulation and Assura for
physical verification (DRC, LVS, and RCX) of CMOS circuits.

LABORATORY OUTCOMES: On completion of lab course, the student will be able to:
CO1: Able to use the Cadence EDA tools for CMOS circuits design.
CO2: Design CMOS logic circuits using Virtuoso Schematic editor of Cadence.
CO3: Able to use Spectre simulator to analyze functional and timings of logic circuits.
CO4: Design the layout of CMOS circuits using Virtuoso layout editor tool.
CO5: Demonstrate the use of Assura tool for physical verification of layout.

LIST OF EXPRIMENTS:
 Academic year 2024-25 July Dec 2024
Batch 2021-25

1. Introduction to Cadence Virtuoso EDA tools design flow.

2. To simulate the VI characteristics of NMOS and PMOS to obtain various performance
parameters.
3. To obtain voltage transfer characteristics of CMOS inverter and observe the effect to varying
W/L ratio on VTC.
4. To obtain the dynamic characteristics of CMOS inverter.
5. To design and verify performance parameters of 2 input NAND & NOR gates based on
inverter sizing.
6. To implement two input NAND & NOR gates using domino logic and compare its
performance with CMOS logic.
7. To implement and simulate 4-bit full adder using CMOS transistors.
8. Study the various design rules for layout using 180 nm technology.
9. Design the layout of CMOS inverter using 180nm technology & observe the effect of
parasitics on its performance.
10. Design the Layout of 4-bit Full adder using 180 nm technology.

ASSESMENT:
Evaluation of students through Continuous performance analysis of students based on experiment
performance, File preparation, internal viva and file submission with weightage of 40% of total marks
and End Semester practical Examination (external viva) with weightage of 60% of total marks.

CO-PO Articulation Matrix for LAB

CO-PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 2 3 - - - - - - - - -
CO2 3 2 3 2 1 - - - - - - -
CO3 3 3 2 2 2 - - - - - - -
CO4 3 2 2 2 1 - - - - - - -
CO5 3 3 2 2 2 - - - - - - -
Avg. 3 2.4 2.4 2 1.2 - - - - - - -

Shri G. S. Institute of Technology and Science

 Academic year 2024-25 July Dec 2024
Batch 2021-25

Department of Electronics and Instrumentation Engineering

B. Tech. IV Year SEM-A (4-YDC)
EI-47257: FIBER OPTICS & PHOTONICS (Elective-III)
HOURS PER CREDITS MAX. MARKS
WEEK
T P TU T P TU THEORY PRACTICAL TOTAL
MARKS
CW END SW END
3 - - 3 - - SEM SEM 100
30 70

PRE-REQUISITE: Fundamentals of Semiconductors and Basic Communication.

COURSE OBJECTIVES:
1. To introduce the students to various optical fiber modes and configurations.
2. To provide the essential knowledge of fiber optic communication system.
3. To impart the knowledge of optical sensors, materials for various applications.

COURSE OUTCOMES: After completion of course, the student will be able to:
1. CO1: To identify modes in optical fibres and define attenuation dispersion optical fibres and
also identify numerical aperture measurement techniques.
2. CO2: To classify various Optical sensors for measurement of parameters like temperature,
flow etc.
3. CO3: To design and implement fibre optic communication system for desired BER, link &
power budget and time budget.
4. CO4: To classify optoelectronics materials & their characteristics required for photonics
integrated circuits.
5. CO5: Identify the behaviour and functionality of different optoelectronic devices.

COURSE CONTENTS:
THEORY:

UNIT-I Optical fiber: Transmission characteristics, attenuation, modes, dispersion effects in optical
fibres material, waveguide dispersions, wavelengths for communication, Attenuation measurement,
Cut back method, Numerical Aperture measurement, multiple wavelength measurement, Fabrication
of Optical fiber.

UNIT-II Optical Instrumentation: Types of Optical fibre sensors, Intrinsic and extrinsic sensor,
measurement of Temperature, Flow, Displacement etc. using optical fiber sensors, OTDR, Optical
power meter, Optical spectrum analyzer.

UNIT-III Optical Communication: Optical Transmitter and Receiver, Basic optical data and voice
communication, Intensity modulation/Direct detection, BER, Link design power budget, rise time
budget, WDM and DWDM systems, Optical Networking, Optical modulators for WDM 40 G bit/s
optical network, Free Space communication systems. New Raman design rules for high-speed
network.

UNIT-IV Optoelectronic materials (III-V) and Technology: Growth and Characterization of Ternary
and Quaternary materials. Photonic Integrated Circuits: Modelling, Design & development and its
applications.
 Academic year 2024-25 July Dec 2024
Batch 2021-25

UNIT-V Semiconductor lasers, Light Emitting Diodes, strained quantum well-laser,

Distributed feedback laser, Distributed Bragg Reflector laser, and vertical cavity Surface Emitting
Laser, Semiconductor Optical Amplifiers, EDFA, Junction photodiode, PIN, APD, responsively,
quantum efficiency etc.

ASSESMENT: Continuous evaluation of students through: Class attendance, Assignments,

organizing Seminars/Quizzes and two mid Semester Tests Exam with weight age of 30% of total
marks. End semester theory exam. Weight age is 70%of total marks.

TEXT BOOKS:
1. John M. Senior, “Optical Fiber Communication: Principles and Practice”, Third Edition,
Pearson Education, 2014.
2. Gerd Keiser, “Optical Fiber Communications”, Fifth Edition, Mc-Graw Hill, 2017.
3. Bhattacharya Pallab, "Semiconductor Optoelectronic Devices”, Second Edition, Pearson
Education, 2017.

REFERENCE BOOKS:
1. C. K. Sarkar and D. C. Sarkar, “Opto Electronics and Fiber Optic Communication”, Second
Edition, New Age International Pvt. Ltd., 2012.
2. S. C. Gupta, “Textbook on Optical Fiber Communication and Its Applications”, Third Edition,
PHI.

CO-PO Articulation Matrix

CO-PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 2 - - - - - - - 1
CO2 3 2 1 - - - - - - - 2
CO3 2 2 3 - - - - - - - 3
CO4 2 1 3 - - - - - - - 1
CO5 3 1 2 1
Avg. 2.6 1.8 2.2 1.6
 Academic year 2024-25 July Dec 2024
Batch 2021-25

Shri G. S. Institute of Technology and Science

Department of Electronics and Instrumentation Engineering
B. Tech. IV Year SEM-A (4-YDC)
EI47322: (PROGRAM ELECTRIVE-IV)
VLSI TECHNOLOGY

HOURS PER CREDITS MAX. MARKS

WEEK
T P TU T P TU THEORY PRACTICAL TOTAL
MARKS
CW END SW END 100
3 - - 3 - - SEM SEM
30 70 - -

PRE-REQUISITE: - Basic Knowledge of Electronic Devices, Semiconductor materials.

COURSE OBJECTIVES:
1. To provide the students the in-depth knowledge of steps involved in chip fabrication
processes.
2. To encourage the students to learn about wafer preparation, oxidation and ion implantation
and photolithography.

COURSE OUTCOMES:
1. CO1: To describe crystal growth and wafer preparation methods.
2. CO2: To list different layering & oxidation methods in terms of chip fabrication.
3. CO3: To illustrate various patterning and doping methods.
4. CO4: To design Floor-planning using EDA tools along with layout design rules check and
stick diagrams.
5. CO5: To discuss various subsystem design and memories.

COURSE CONTENTS:
THEORY:

UNIT-I Crystal Growth and Wafer preparation: Wafer terminology, Different crystalline
orientations, CZ method, CMOS IC Design flow, Crystal Defects. Fabrication processes of FETs,
MOSFETs, and BIMOS etc

UNIT-II Layering: Epitaxial growth methods, Liquid phase epitaxy, Vapor phase epitaxy, Molecular
beam epitaxy, Oxidation, Types of oxidations, Horizontal and vertical tube furnace for oxidation,
Kinetics of oxidation, Thin film fabrication, Metallization; Physical Vapor Deposition, Sputtering.

UNIT-III Patterning: Lithography; Optical Lithography, Electron Lithography, X-ray Lithography,

Ion Lithography. Photo masking steps, Resists. Doping: Diffusion; Diffusion Models, Ion
Implantation; Implantation Equipment, Channelling.

UNIT-IV VLSI process techniques and Integration: Floor planning, layout, Design rules, stick
diagrams, Test generation, Logic simulation, Introduction to EDA tools. Contamination Control;
Clean rooms, HEPA, ULPA Filters and Class numbers.
 Academic year 2024-25 July Dec 2024
Batch 2021-25

UNIT-V Memory; NVRWM, Flash memories,6-Transistor RAMs Dynamic RAM, Read Write
Cycle, Brief review of subsystem design using memory and processors and their fabrication aspects,
Latch up in CMOS Circuits.

ASSESMENT:
Continuous evaluation of students through: Class attendance, Assignments, organizing
Seminars/Quizzes and two mid Semester Tests Exam with weight age of 30% of total marks. End
semester theory exam. Weight age is 70%of total marks.

TEXT BOOKS:
1. Sorab K. Gandhi, “VLSI Fabrication principles: Silicon and Gallium Arsenide”, Second
Edition, Wiley, 2008.
2. S. M. Sze, “VLSI Technology”, Second edition, McGraw Hill, 2017.
3. Peter Van Zant, “Microchip Fabrication, A Practical Guide to Semiconductor Processing”,
Sixth Edition, McGraw Hill, 2013.

REFERENCE BOOKS:
1. James D. Plummer, Micheal D. Deal and Peter B. Grifin, “Silicon VLSI Technology:
Fundamentals, Practice, Modeling”, Prentice Hall, 2000.
2. C. Y. Chang and Simon Sze, “VLSI Technology”, Mc-Graw Hill, 2000.

CO-PO Articulation Matrix

CO-PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 2 2 1 1 - - - - - - -
CO2 3 2 2 1 1 - - - - - - 1
CO3 3 2 3 2 1 - - - - - - 1
CO4 3 2 3 1 1 - - - - - - 2
CO5 3 3 2 2 1 - - - - - - 2
Avg. 3 2.2 2.4 1.4 1 - - - - - - 1.5