BHARATH INSTITUTE OF SCIENCE AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

QUESTION BANK
U20ECCJ12– DIGITAL ELECTRONICS

Bloom’s
Q.No Question Weightage CO
Level
UNIT I
PART – A
1 Differentiate decimal and Hexadecimal with an example. 2 CO1 2
Where relation between Binary and Hexadecimal is used?
2 2 CO1 2
Convert (43.2)8 to binary.
3 2 CO1 2
Convert(100011.010)2 to Hexadecimal.
4 2 CO1 3
5 Express the OR and NOR logic gates. 2 CO1 3
6 Explain about types of logic gates. 2 CO1 3
7 Define AXIOMS ofBoolean Algebra. 2 CO1 3
What is DeMorgan’s theorem ?
8 2 CO1 3

9 Draw standard three variable K- map. 2 CO1 3

What is standard four variable K- map?
10 2 CO1 3
PART – B
1 Simplify the Boolean expression using K-Map in sum of
products(SOP) form 𝐹 (𝐴, 𝐵, 𝐶, 𝐷) = Σ(0,1,2,5,8,9,10). 4 CO1 3

2 Simplify the Boolean expression using K-Map in

Product of sums(POS) form 𝐹 (𝐴, 𝐵, 𝐶, 𝐷) =
4 CO1 2
Σ(0,1,2,5,8,9,10).

3 Draw Boolean expression using K-Map in SOP form

𝐹(𝑤, 𝑥, 𝑦, 𝑧) = (1,3,7,11,15) and that has the don’t care
4 CO1 2
conditions 𝑑(𝑤, 𝑥, 𝑦, 𝑧) = (0,2,5).

4 Implement OR gate using only NAND gates. 4 CO1 2

5 Implement OR gate using only NOR gates. 4 CO1 2
6 Implement EXOR gate using only NAND gates 4 CO1 2
7 Implement EXOR gate using only NOR gates 4 CO1 3
8 Implement AND-OR-INVERT gates with function
𝐹(𝑥, 𝑦, 𝑧) = Σ(0,6). 4 CO1 3

9 Implement OR-AND- INVERTgates with function

𝐹(𝑥, 𝑦, 𝑧) = Σ(0,6). 4 CO1 3

10 Implement three variable exclusive-OR odd function 𝐹 =

𝐴⨁𝐵⨁𝐶 4 CO1 3

PART – C

Bharath Institute Of Higher Education and Research (BIHER) IQAC/ACAD/008

 BHARATH INSTITUTE OF SCIENCE AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Briefly explain the types of logic gates?.Expain with its

1 12 CO1 2
symbol, equation and truth tables.
Briefly explain AXIOMS, laws, theorems properties of 12
2 CO1 2
Boolean Algebra.
Simplify the Boolean expression using 5 variable K-Map 12
3 in SOP form 𝐹 (𝑤, 𝑥, 𝑦, 𝑧) = CO1 2
(0,2,4,6,9,13,21,23,25,29,31)
Simplify the Boolean expression using K-Map in SOP 12
form 𝐹 (𝑤, 𝑥, 𝑦, 𝑧) = (1,3,7,11,15) and that has the
4 CO1 2
don’t care conditions 𝑑(𝑤, 𝑥, 𝑦, 𝑧) = (0,2,5)

Simplify the Boolean expression using tabulation method 12

𝐹 = ∑(0,1,2,8,10,11,14,15) and verify the result using
5 CO1 3
K-map method.

Design and Implement the following function with 12

a).Two level NAND gates b).Two level NOR gates
6 CO1 3
𝐹(𝑥, 𝑦, 𝑧) = Σ(0,6)

Design and Implement AND-OR-INVERT and OR- 12

7 AND- INVERTgates with function 𝐹(𝑥, 𝑦, 𝑧) = Σ(0,6). CO1 3

Design and Implement three variable exclusive-OR odd 12

8 function 𝐹 = 𝐴⨁𝐵⨁𝐶. CO1 3

Design and Implement three variable exclusive-OR even 12

9 function 𝐹 = (𝐴⨁𝐵⨁𝐶)′. CO1 3

Explain parity generator and checker with its truth table 12

10 CO1 3
and logic circuit implementation.

Bloom’s
Q.No Question Weightage CO
Level
UNIT II
PART – A
Differentiate Analysis of a combinational and sequential
1 2 CO2 2
circuit.
Where Boolean function from a logic diagram is used?
2 2 CO2 2
Give the design procedure steps.
3 2 CO2 2
What is 4-bit adder-subtractor circuit?
4 2 CO2 3
Express decimal BCD adder Boolean function of output
5 2 CO2 3
carry.
6 Explain about magnitude comparator . 2 CO2 3
7 Define 3-to-8 line Decoder circuit. 2 CO2 3
What is 3-to-8 line Encoder circuit?
8 2 CO2 3

9 Draw 4-to-1 multiplexer symbol. 2 CO2 3

Bharath Institute Of Higher Education and Research (BIHER) IQAC/ACAD/008

 BHARATH INSTITUTE OF SCIENCE AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

What is implementation table for the Boolean function?

10 2 CO2 3
PART – B
1 Explain the analysis procedure of combinational circuit
4 CO2 3
design.
2 Explain the design procedure of combinational circuit
4 CO2 2
design.
3 Draw4 bit binary Adder-Subtractor circuit. 4 CO2 2
4 Draw decimal BCD adder circuit. 4 CO2 2
5 With a circuit explain a magnitude comparator . 4 CO2 2
6 Compare 3-to-8 line Decoder and encoder circuit. 4 CO2 2
7 Explain about 3-to-8 line Encoder circuit. 4 CO2 3
8 Explain about Multiplexer circuit. 4 CO2 3
9 Explain the SR Flip-Flop into D Flip-Flop Characteristic
4 CO2 3
& excitation table.
10 Implement the Boolean function 𝐹(𝐴, 𝐵, 𝐶 ) = ∑(1,3,5,6)
4 CO2 3
with a 4 × 1 multiplexer.
PART – C
Briefly explain the analysis procedure of combinational
1 12 CO2 2
circuit design with an example.
Briefly explain the design procedure of combinational 12
2 circuit design with an example. CO2 2

Design and implement 4 bit binary Adder-Subtractor 12

3 CO2 2
circuit.
Design and implement a 3-to-8 line Decoder circuit in 12
4 CO2 2
details.
Design and implement 3-to-8 line Encoder circuit in 12
5 CO2 3
details.
Illustrate 4-to-1 and 8-to-1 multiplexer with block 12
6 CO2 3
diagram.
Implement the Boolean function 𝐹(𝐴, 𝐵, 𝐶 ) = ∑(1,3,5,6) 12
7 CO2 3
with a 4 × 1 multiplexer.
Design and implement 4 bit binary BCD Adder- 12
8 CO2 3
Subtractor circuit.
Design and implement a 3-to-8 line Decoder circuit in 12
9 CO2 3
details.
Design and implement 3-to-8 line Decoder and Encoder 12
10 CO2 3
circuit in details.

Bloom’s
Q.No Question Weightage CO
Level
UNIT III
PART – A
1 Differentiate Flip-flop and latches. 2 CO3 2
Where Latch or Flip-flop can be used?
2 2 CO3 2

Bharath Institute Of Higher Education and Research (BIHER) IQAC/ACAD/008

 BHARATH INSTITUTE OF SCIENCE AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Give the types of flip-flops.

3 2 CO3 2
What is flip-flop triggering? What are its types?
4 2 CO3 3
5 Write the types of triggering. 2 CO3 3
Explain about What are the types of flip flop based on
6 triggering? 2 CO3 3

7 Define edge triggering flip flops. 2 CO3 3

What is Race Around Condition? How to eliminate it?
8 2 CO3 3

9 DrawSR Latch charecteristics table or state table. 2 CO3 3

What is JK Latch symbol?
10 2 CO3 3
PART – B
1 Explain JK Latch charecteristics table or state table. 4 CO3 3
2 Explain the D Latch charecteristics table or state table 4 CO3 2
3 Compare D and T Latches charecteristics table or state
4 CO3 2
table
4 Explain SR Latch charecteristics equation or state
4 CO3 2
equation
5 With a circuit explain JK Latch implementation of logic
4 CO3 2
circuits
6 Compare SR and JK Latches charecteristics equation or
4 CO3 2
state equation.
7 Explain about D flip flop state diagram. 4 CO3 3
8 Explain about T flip flop state diagram. 4 CO3 3
9 Explain the SR Flip-Flop into D Flip-Flop Characteristic
4 CO3 3
& excitation table.
10 Explain the SR Flip-Flop into T Flip-Flop Characteristic
4 CO3 3
& excitation table.
PART – C
Explain What is and what are the types of Latch or Flip-
1 flop storage elements?. What is triggering and various 12 CO3 2
types of triggering?. Differentiate Latch and flipflop.
Brieflyexplain SR Latch with its symbol, operation, truth 12
2 CO3 2
table and its logic circuit diagram.
Brieflyexplain JK Latch with its symbol, operation, truth 12
3 CO3 2
table and its logic circuit diagram.
Brieflyexplain D flip flop with its symbol, operation, 12
4 CO3 2
truth table and its logic circuit diagram.
Brieflyexplain T flip flop with its symbol, operation, truth 12
5 CO3 3
table and its logic circuit diagram.
Illustrate synthesis or conversion using SR flip flop into 12
6 CO3 3
D Flip-Flop with its input equations.
Illustrate synthesis or conversion using SR flip flop into 12
7 CO3 3
T Flip-Flop with its input equations.
Briefly explain synthesis or conversion using JK flip flop 12
8 CO3 3
into a SR Flip-Flop with its input equations.
9 Briefly explain Master slave JK FF flip-flop. 12 CO3 3
Bharath Institute Of Higher Education and Research (BIHER) IQAC/ACAD/008
 BHARATH INSTITUTE OF SCIENCE AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Briefly explain mealy and moore models of finite state 12

10 machines with its state table, state diagram and CO3 3
implementation.

Bloom’s
Q.No Question Weightage CO
Level
UNIT IV
PART – A
1 What are the primary and secondary units? 2 CO4 2
List the different type of architectures in VHDL
2 2 CO4 2
modelling
3 Give example of a concurrent signal assignment 2 CO4 2
4 What is event scheduling? 2 CO4 3
5 Write the entity for 8x3 encoder 2 CO4 3
6 Explain about the process statement 2 CO4 3
7 Define sensitivity list in process statement 2 CO4 3
8 Define transport delay 2 CO4 3
9 Define inertial delay 2 CO4 3
10 What are drivers in VHDL? 2 CO4 3
PART – B
1 Explain an entity in VHDL with an example. 4 CO4 3
2 Explain the transport and inertial delay in VHDL with
4 CO4 2
suitable examples.
3 Compare the architecture selection 4 CO4 2
4 Explain drivers in VHDL using an example 4 CO4 2
5 With an example explain guarded blocks 4 CO4 2
6 Compare signal assignment statement versus variable
4 CO4 2
assignment statement
7 Explain about object types 4 CO4 3
8 Explain about GENERIC statement in VHDL 4 CO4 3
9 Explain the If-THEN-ELSE statement in VHDL 4 CO4 3
10 Explain the CASE statement in VHDL 4 CO4 3
PART – C
Explain VHDL dataflow style modelling with 4:1
1 12 CO4 2
multiplexer
Explain VHDL Sequential style modelling with 4:1 12
2 CO4 2
multiplexer.
3 Explain the various data types in VHDL 12 CO4 2
4 With an example explain block statements 12 CO4 2
Explain VHDL Structural style modelling with 4:1 12
5 CO4 3
multiplexer
6 Illustrate with example the transport and inertial delay. 12 CO4 3
Bharath Institute Of Higher Education and Research (BIHER) IQAC/ACAD/008
 BHARATH INSTITUTE OF SCIENCE AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Explain the sequential statements inside the process with 12

7 CO4 3
example such as IF-THEN_ELSE and CASE statements
8 12 CO4 3
Explain the sequential statements inside the process with 12
9 CO4 3
example such as WHILE and WHEN statements
10 Classify the various data types in VHDL 12 CO4 3

UNIT V
PART – A
1 Write the VHDL entity for half adder 2 CO5 2
2 Write the VHDL entity 8x 3 encoder 2 CO5 2
3 What are the different modes of port in VHDL?. 2 CO5 3
4 Write the VHDL entity for 4-bit adder 2 CO5 3
5 Write the VHDL entity data selector 2 CO5 2
6 Write the entity for equality checker 2 CO5 2
7 Write the entity for shift register 2 CO5 2
8 Write the entity for counter 2 CO5 2
9 Write the entity for serial to parallel converter 2 CO5 2
10 Write the entity for twisted ring counter 2 CO5 2
PART – B
1 Explain the VHDL code for 2 bit comparator 4 CO5 2
2 Explain the VHDL code for SR Flip flop 4 CO5 2
3 Explain the VHDL code for D Flip flop 4 CO5 2
4 Explain the VHDL code for data selector 4 CO5 2
Explain the VHDL entity for full adder using behaviour
5 4 CO5 2
modelling
6 Explain the VHDL code for T Flip flop 4 CO5 2
Explain the VHDL entity for full adder using Structural
7 4 CO5 2
style modelling
Explain the VHDL code for data selector using structural
8 4 CO5 2
style modelling
Explain the implementation of all logic gate using
9 4 CO5 2
dataflow style modelling in VHDL
10 Explain the INOUT port statement with an example 4 CO5 3
PART – C
Explain the 4-bit ripple carry adder in VHDL with
1 12 CO5 2
structural style modelling
Explain the 4:1 multiplexer in VHDL with structural style 12
2 CO5 2
modelling
Explain the 8x3 decoder entity and architectural 12
3 CO5 3
description VHDL code
Explain the VHDL entity and architectural 12
4 CO5 3
descriptioncounter code
Explain the entity and architectural descriptionVHDL 12
5 CO5 3
twisted ring counter code
Bharath Institute Of Higher Education and Research (BIHER) IQAC/ACAD/008
 BHARATH INSTITUTE OF SCIENCE AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Explain the 4-bit shift register entity and architectural 12

6 CO5 2
description VHDL code
Explain the serial-parallel entity and architectural 12
7 CO5 3
descriptionVHDL code
Explain the 4-bit ripple carry adder in VHDL with 12
8 CO1 3
behaviour style modelling
Explain the 4:1 multiplexer in VHDL with behaviourl 12
9 CO1 3
style modelling
Explain the SR latch and SR FF entity and architectural 12
10 CO1 3
description VHDL code.

Bharath Institute Of Higher Education and Research (BIHER) IQAC/ACAD/008