In a master slave architecture, the TEA2164 Control IC achieves the slave function. This circuit provides an easy synchronization and smart solution for low power stand by operation.
In a master slave architecture, the TEA2164 Control IC achieves the slave function. This circuit provides an easy synchronization and smart solution for low power stand by operation.
In a master slave architecture, the TEA2164 Control IC achieves the slave function. This circuit provides an easy synchronization and smart solution for low power stand by operation.
In a master slave architecture, the TEA2164 Control IC achieves the slave function. This circuit provides an easy synchronization and smart solution for low power stand by operation.
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TEA2164
SWITCH MODE POWER SUPPLY PRIMARY CIRCUIT
. . . . . . .
POSITIVE AND NEGATIVE OUTPUT CURRENT UP TO 1.2A AND 1.7A A TWO LEVEL COLLECTOR CURRENT LIMITATION COMPLETE TURN OFF AFTER LONG DURATION OVERLOADS UNDER AND OVER VOLTAGE LOCK-OUT SOFT START BY PROGRESSIVE CURRENT LIMITATION DOUBLE PULSE SUPPRESSION BURST MODE OPERATION UNDER STANDBY CONDITIONS
DESCRIPTION In a master slave architecture, the TEA2164 control IC achieves the slave function. Primarily designed for TV receivers and monitors applications, this circuit provides an easy synchronization and smart solution for low power stand by operation. Located at the primary side the TEA2164 Control IC ensures : - the power supply start-up - the power supply control under stand-by conditions - the process of the regulation signals sent by the master circuit located at the secondary side - directbase drive of the bipolar switching transistor - the protection of the transistor and the power supply under abnormal conditions. For more details, refer to application note AN409.
POWERDIP16 (Plastic Package) ORDER CODE : TEA2164
PIN CONNECTIONS
GROUND I COPY LONG CAPACITOR OVERLOAD CAPACITO R SUBSTRATE SUBSTRATE PULSE INPUT OSCILLATOR TIMING RESISTOR OSCILLATOR TIMING CAPACITOR
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
V CC SUPPLY VOLTAGE OUTPUT STAGE POSITIVE SUPPLY VOLTAGE OUTPUT (BASE CURRENT) SUBSTRATE SUBSTRATE IC (max.)
SENSE
LOW FREQUENCY OSCILLATOR CAPACITOR FEEDBACK INPUT IS BURST MODE
2164-01.EPS
December 1992
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TEA2164 BLOCK DIAGRAM
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2164-02.EPS
TEA2164 Figure 1 : Simplified Application Diagram
ABSOLUTE MAXIMUM RATINGS
Symbol VCC V+ V VCC - V V+ - V Iout+ Iout Tj Tstag Parameter Positive Power Supply V16-V1 Positive Power Supply of the Output Stage V15-V1 Negative Power Supply V4, 5, 12, 13-V1 Total Power Supply V16-V4, 5, 12, 13 or V15-V4, 5, 12, 13 Positive Output Current Negative Output Current Operating Junction Temperature Storage Temperature Range Value 18 18 5 20 1.5 2 150 40, + 150 Unit V V V V A A C C 2164-01.TBL 2164-02.TBL
THERMAL DATA Symbol Rth(j-c) Parameter Junction Case Thermal Resistance Value 11 Unit C/W
MAXIMUM POWER DISSIPATION
2164-04.EPS
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2164-03.EPS
TEA2164 RECOMMANDED OPERATING CONDITIONS Symbol VCC V VCC V Iout+ Iout Fsw Ro Co C1 C2 Vin Toper Parameter Positive Power Supply Negative Power Supply (absolute value) (note 1) Total Power Supply Positive Output Current Negative Output Current Switching Frequency Oscillator Resistor Range Oscillator Capacitor Range Starting Oscillator Capacitor Range Repetitive Overload Protection Capacitor Input Pulses Amplitude (peak) (derivated pulses - time constant = 1 s) Operating Ambiant Temperature V CC12 4 13 14 1 IB < 0 5 IB > 0 12 4 13 14 1 capacitive coupling IB < 0 IB < 0 5 IB I
Min. 0
Typ. 10
Max. 14 5 18 1.2 1.7 50 150 2700 4.7 22 1 70
Unit V V V A A khz k pF F 2164-03.TBL 2164-04.TBL 2164-05.EPS
30 470 0.1 1 0.5 20
F V C
TEA2164
TEA2164
V CC-
ELECTRICAL OPERATING CHARACTERISTICS Tamb = 25oC, VCC = 10V, VCC- = 0V, potentials referenced to ground (Pin 1) (unless otherwise specified) Symbol POWER SUPPLY VCC (start) VCC (stop) VCC Vccmax Iccstart VCM1 VCM2 VCM VCM3 VCM3-VCM1 VC2 I3 disch I3 ch. To Ton(max) 4/15 Starting Voltage (VCC increasing) Stopping Voltage (VCC decreasing) Hysteresis (VCC start VCC stop) Overvoltage Lock-out Starting Positive Supply Current Pulse by Pulse Current Limitation Threshold Current Monitoring 2nd Threshold VCM = VCM2 VCM1 Repetitive Overcurrent Threshold (pin 11) (VCM3-VCM1) Lock-out Voltage on Pin 3 Capacitor C2 Discharge Current (synchronized mode) Capacitor C2 Charge Current Oscillator Initial Accuracy RT = 50 K, CT = 1 nF Maximum Duty Cycle (Tsyn = 1.05 To) 8 5 2 14.8 0.5 720 1200 300 9 6.2 2.8 15.5 0.8 840 1350 500 9.6 7.4 3.5 16.2 1.5 970 1500 700 V V V V mA mV mV mV Parameter Min. Typ. Max. Unit
CURRENT LIMITATION AND PROTECTION (pin 11)
REPETITIV E OVERCURRENT PROTECTION 700 20 2.4 10 50 19.3 60 900 50 3 20 80 21 70 1100 130 3.6 30 110 22.7 85 mV mV V A A s %
OSCILLATOR, MAX DUTY CYCLE, SYNCHRONIZATION
TEA2164 ELECTRICAL OPERATING CHARACTERISTICS (continued) Symbol Tsyn TO OUTPUT STAGE I14/I 2 IBON Ic Copy Current Gain Base Current Starting Pulse Burst Duty Cycle 1000 300 13 mA % Parameter Min. Typ. Max. Unit OSCILLATOR, MAX DUTY CYCLE, SYNCHRONIZATION (continued) Synchronization Window 1.0 1.5
VERY LOW FREQUENCY OSCILLATOR
I. FIELD OF APPLICATION The TEA2164 control circuit has been designed primarily for discontinuous mode flyback built with a master-slave architecture, whatever the field of application. But due to its capability to synchronize the transistor switching-off with an external signal (line flyback) and due to an adaptedburst-mode operation for a low power stand-by operation, the TEA2164 offers a smart solution for monitors and TV sets applications. Power supply main features : - maximum output power 140W (transistor forced gain : 3.5) Figure 2 : Master Slave Power Supply Architecture
- stand-by mode output power (1W Psb 6W ; efficiency > 50%) - operating frequency up to 50kHz - power-switch : bipolar transistor Adapted master-circuit : Monitor application Standard TV application TEA5170 TEA2028B TEA2029C TEA2128 TEA5170 TEA5170
Digital TV application
(TEA2028B, TEA2029C and TEA2128 are deflection processors with built-in PWM generator).
AUDIO OUTPUT STAGE
Muting Control
R P1 Remote Stand-by
MAINS INPUT P2 C
Synchronization
SCANNING DEVICE
VOLTAGE REGULATOR Remote Stand-by V CC
TEA2164
TEA5170
V CC INFRA-RED RECEIVER PWM
P1 : Output voltage adjustement in normal mode P2 : Output voltage adjustement in stand-by
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2164-06.EPS
Small signal primary ground Power primary ground Secondary ground (isolated from mains)
2164-05.TBL
TEA2164 II. GENERAL DESCRIPTION In a master slave architecture, the TEA2164 Control IC, located at the primary side of an off line power supply achieves the slave function ; whereas Figure 3 : System Description Waveforms the master circuit is located at the secondary side. The link between both circuits is realized by a small pulse transformer (Figure 3).
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2164-07.EPS
TEA2164 In the operation of the master-slave architecture, four majors cases must be considered : - normal operating - stand-by mode - power supply start-up - abnormal conditions : off load, short circuit, ... II.1. Normal Operating (master slave mode) In this configuration, the master circuit generates a pulse width modulatedsignal issued from the monitoring of the output voltage which needs the best accuracy (in TV applications : the horizontal deflection stage supplyvoltage). The master circuit power supply can be supplied by another output. The PWM signal are sent towards the primary side through small differentiating transformer. For the TEA2164 positive pulses are transistor switchingon commands ; and negative pulses are transistor switching-off commands (Figure 4). In this configuration, only by synchronizing the master oscillator, the switching transistor may be synchronized with an external signal. II.2. Stand-by Mode In this configuration the master circuit no longer Figure 4 : Master Slave Mode Waveforms sends PWM signals, the structure is not synchronized ; and the TEA2164 operates in burst mode. The average power consumption at the secondary side may be very low 1W P 6W (as it is consumed in TV set during stand by). By action on the maximum duty cycle control, a primary loop maintains a semi-regulation of the output voltages. Voltage on feed-back is applied on Pin 9. Burst period is externally programmed by capacitor C1. II.3. Power Supply Start-up After the mains have been switched-on, the VCC storage capacitor of the TEA2164 is charged through a high value resistor connected to the rectified high voltage. When Vcc reaches VCC start threshold (9V typ), the TEA2164 starts operating in burst mode. Since available output power is low in burst mode the output power consumption must remain low before complete setting-up of output voltage. In TV application it can be achieved by maintaining the TV in stand-by mode during startup (Figure 6).
Sync. Pulses Synchro.
PWM Signal SLAVE CIRCUIT MASTER CIRCUIT Pulse Input
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2164-08.EPS
Base Current
TEA2164 Figure 5 : Burst Mode Waveforms
Figure 6 : Power Supply Start-up
Tstart-up = Tch + T1
T1 : necessary time for voltage setting-up
d) Abnormal conditions : safety functions Overvoltage Protection When VCC exceeds VCC max, an internal flip-flop stops output conduction signals. The circuit will start again after the capacitor C1 discharge ; it means : after loss of synchronization or after Vcc stop crossing (Figure 7). In flyback converters, this function protects the power supply against output voltage runaway. Under Voltage Lock-out The TEA2164 control circuit stops operating when VCC goes under VCC stop. 8/15
Power Limitation, Current Protection, Long Duration Overload Protection - Output power limitation : by a pulse by pulse collector current limitation the TEA2164 limits the maximum output power. VCM1 is the corresponding voltage threshold, its detection is memorized up to the next period. - Current protection (transistor protection) Under particular conditions a hard overload or short circuit may induce a flux runaway in spite of the current limitation (VCM1). The TEA2164 control circuit features a second current protection, VCM2. When this threshold is reached an internal flip-flop memorizes it and
2164-10.EPS
Tch 1s (typ) T1 0.3s (typ)
2164-09.EPS
TEA2164 output conduction signals are inhibited. The circuit will send base drives again after capacitor C1 discharge (Figure 7). - Long duration overload protection : (Figure 8) An overload is detected when the sense-voltage on Pin 11 reaches VCM3 before a negative pulse has been applied to Pin 6. In this case the capacitor C2 (connected to Pin 3) is charged with I3 ch up to the end of the period and discharged with I3 disch until a next VCM3 detector. By this way in case of long duration overload, the capacitor Figure 7 : Overvoltages Lock-out keeps charging at each period and its voltage encreases gradually. When the voltage on Pin 3 exceeds VC2, the TEA2164 control circuit stops sending base drives and memorizes this event. No restart is allowed as long as Vpin 3 is higher than VC2 and VCC higher than 4.8V. * Remark : - The harder is the overload the faster is the protection - The capacitor keeps charging between two burst after VCM2 detection.
Figure 8 : Long Duration Overload Monitoring Circuit
III. SWITCHING OSCILLATOR AND SYNCHRONIZATION III.1. Switching oscillator When the TEA2164 control circuit operates in burst mode, the switching frequency is fixed by the free frequency oscillator. The period is determined by two external components CO and RO. III.2. Synchronization When the master-circuit starts to send pulses both Figure 11 : Free Frequency Running oscillators are not synchonuous. In order to avoid any erratic conduction of the power transistor, the first synchronization pulse will arrive simultanously with the sawtooth return of the TEA2164 oscillator. To get synchronization the free frequency must be higher than the synchronization frequency. TO < Tsync. < 1.50 TO
Figure 12 : Synchronization Pulse Shaper and Synchronization
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2164-16.EPS
2164-15.EPS
2164-14.EPS
TEA2164 Operation after synchronization
(1) NORMAL OPERATION T : synchronization window
(2) NEGATIVE PULSE MISSING Transistor turn-off is ensured by VCM1 current limi tation crossing or by an internal tON (max.) limitation set by a 2.5V threshold
Operation after synchronization
(3) ERRATIC POSITIVE PULSES
(4) Fsynchro < 0.65 Fo Signal S1 triggers burst oscillator capacitor discharge. The TEA2164 restarts in burst-mode 2164-19.EPS
P1 and P2 are masked due to the synchronization window Cases (2) (3) (4) do not occur in normal operating.
IV - MAXIMUM DUTY CYCLE LIMITATION Burst mode : The maximum duty cycle is controlled by the voltage on Pin 9 (Figure 13). Synchronized mode : Normally the maximum duty cycle is set by the master circuit. Oowever the maximum conducting time will never exceed the value given by the comparison of the oscillator wave-form with the 2.5V internal threshold. V - OUTPUT STAGE TEA2164 output stage has been designed to drive switching bipolar transistor. - Each base drive begins with a positive pulse IBON
that realizes an efficient transistor turn-on. - After the starting pulse I BON, the base current is proportional to the collector current. The current gain is easily fixed by a resistor R (Figure 14). - A fast and safe transistor turn-off is realized by a fast positive base current cut-off and by applying a negative base drive which draws stored carriers. A typical 0.7s delay prevents from cross-conduction of positive and negative output stages. Remark : In order to reduce power dissipation on the positive output stage with the low gain transistors, for high base currents the positive output stage operates in saturated mode (Figure 15). This can be achieved by using a resistor between VCC and V+.
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2164-17.EPS / 2164-18.EPS
TEA2164 Figure 13 : Maximum Duty Cycle Limitation
Figure 14 : Output Stage Architecture and Base Drive
IB V V CC 16 CURRENT MIRROR
I BON t
15
14 Virtual Ground 2 I COPY V 4-5-12-13 RB
IB
I Cmax
IC
t RS IC IB IC GF = GF IC IB RS = RB 1000 x R S V CM1 2164-21.EPS 2164-22.EPS
I Cmax
VI - MONITOR APPLICATIONS In most of monitor applications, the power supply must start-up under full load conditions and the stand -by mode is no longer useful.
The energy of the starting burst must be high enough to ensure start-up, then the capacitor C1 must be higher in these applications than on TV application (typ. : 1F).
Figure 15 : Power Supply Start-up and Normal Operation
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