Introduction to

CMOS VLSI
Design
Delay Part A

Lecture by Jay Brockman

University of Notre Dame Fall 2008
Modified by Peter Kogge Fall 2010,2011, 2015, 2018
Based on lecture slides by David Harris, Harvey Mudd College
http://www.cmosvlsi.com/coursematerials.html

Delay A Slide 1

Outline
 Delay Part A
– Capacitance
– Effective Resistance
– RC Delay
 Delay Part B
– Review
– Inverter Delay
– The Elmore Model
– Effect of Load Capacitance

Delay A CMOS VLSI Design Slide 2

1
 Capacitance
 Conductors separated by insulator have capacitance
 Gate to channel capacitor is very important
– Creates channel charge necessary for operation
 Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion

A Req
A

Delay A CMOS VLSI Design Slide 3

Gate Capacitance
 Approximate channel as “connected to source”
 Cgs = oxWL/tox = CoxWL = CpermicronW
– proportional to “width” ONLY
 Cpermicron = ox(L/tox) typically ~2 fF/m of gate width
– L and tox both scale with process
 Often just Cg

polysilicon
gate Cgs
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.90)
p-type body

Delay A CMOS VLSI Design Slide 4

2
 Caveat
 Statement that Cgs is proportional ONLY to width is
true ONLY as long as Length and tox scale together

 We will assume this for rest of course

 BUT: NOT TRUE for really small feature sizes!

Delay A CMOS VLSI Design Slide 5

Denoting “Width”
 Assume width of smallest transistor is Ws
 If actual width of a transistor is “W”
 Then relative width “k” is W/Ws
 Write “k” inside transistor

polysilicon
gate Cgs
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.90)
p-type body

Delay A CMOS VLSI Design Slide 6

3
 Diffusion Capacitance
 Csb, Cdb = “source/drain to bulk”
 Undesirable, called parasitic capacitance
 Capacitance depends on area and perimeter Cdb
– Comparable to Cg for contacted diffusion
– ½ Cg for uncontacted Cgs
Csb
– Varies with process
– Often just Cd
 “Contacted diffusion” occurs when there is a metal
contact “touching” the diffusion
– i.e. there’s a “wire” on the source or drain
 Appears on both source & drain
– But ignore when connected to Vdd or Gnd
• Capacitance is “shorted out”
Delay A CMOS VLSI Design Slide 7

Contacted vs. Uncontacted

Capacitance
 Transistor Layout
– Contacted Source/Drain – Physically Larger => more cap
– Uncontacted Source/Drain – Smaller
 Example nmos transistors in NAND

C C
Uncontacted S/D
C/2
Contacted S/D

Delay A CMOS VLSI Design Slide 8

4
Let’s Do An Example: How Many Diffusion
Caps Are There? And Where?

Y
A
B Answer: ____

Delay A CMOS VLSI Design Slide 9

OK- How Many “Don’t Count”?

Vdd Vdd

Vdd

Y
Vdd

Gnd

A Gnd

B Gnd

Delay A CMOS VLSI Design Slide 10

5
 OK- Which are Contacted?
Vdd
X X Vdd

Vdd

Y
Vdd

Gnd

A Gnd

B
X Gnd

Delay A CMOS VLSI Design Slide 11

OK- What are Their Values?

Contacted

Vdd

Y
Vdd

Gnd

A Gnd

B Assume:
• All transistors same size
• Contacted ~ C
• Uncontacted ~ C/2

Delay A CMOS VLSI Design Slide 12

6
OK – What’s the Final Model

C
Vdd

Y
Vdd

C Gnd
C
A Gnd

C/2
B Assume:
• All transistors same size
• Contacted ~ C
• Uncontacted ~ C/2

Delay A CMOS VLSI Design Slide 13

Final Model
Again this assumes
p nypes same size
as ntypes

Y
3C
A C/2
Gnd

Delay A CMOS VLSI Design Slide 14

7
 RC Delay Model
 Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
• Why?
 Actual Capacitance proportional to minimum width “k”
 Actiual Resistance
d
inversely proportional to width “k”
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d

Delay A CMOS VLSI Design Slide 15

Driving Another Gate

NMOS NMOS

Output of 1st gate “sees” aggregate input capacitance of 2nd Gate

Termed Load Capacitance CL
Delay A CMOS VLSI Design Slide 16

8
 Between Cells VDD

Vin Vout Vin Vout

VSS
Inverter “Stick Diagram”
VDD

G
S D
In Out
Vout
S D
G

VSS

Green: diffusion; Red: poly; Blue/gray: metal wire; black: contact

Delay A CMOS VLSI Design Slide 17

1st Inv Falling Output (1)

Vin Rp Vout

Vout

Rn CL
t t

Before t=0, input stable & capacitor fully charged

Delay A CMOS VLSI Design Slide 18

9
 Falling Output (2)

Vin Rp Vout

Rn CL
i
t t

After t-0, capacitor discharges through NMOS

Delay A CMOS VLSI Design Slide 19

Rising Output (1)

Vin Rp Vout

Rn CL
t t

Before t=0, input stable & capacitor fully discharged

Delay A CMOS VLSI Design Slide 20

10
 Rising Output (2)

Vin Rp Vout

Rn CL
i
t t

After t=0, capacitor charges through PMOS

Delay A CMOS VLSI Design Slide 21

Solving
 How long does it take to discharge the output from
starting voltage V0 to voltage V1?

Kirchhoff’s current law at output

Rp

Rn CL
IR IC

If V1 = V0/2, Time = RC ln(2) = 0.69*RC

REMEMBER THIS #!
Delay A CMOS VLSI Design Slide 22

11
 Definitions
 Waveform
– Rise time tr = time to rise from 20% of Vdd to crossing 80% of Vdd
– Fall time tf = time fall from 80% of Vdd to crossing 20% of Vdd
– Edge Rate trf = (tr + tf)/2
 Logic gate input to output
– Propagation delay tpd = max time from input crossing 50% of Vdd
to output crossing 50% of Vdd
• tpdr = delay when input is rising
– tpHL = delay when output goes from High to Low
• tpdf = delay when input is falling
– tpLH = delay when output goes from Low to High
• Delay tp = (tpHL + tpLH)/2
– Contamination delay tpd = min time from input crossing 50% of
Vdd to output crossing 50% of Vdd
• i.e with no load on output, in either direction
Delay A CMOS VLSI Design Slide 23

Delay Definitions
Vin Vout

Vin
Propagation delay
input 50% tp = (tpHL + tpLH)/2
waveform

t
tpHL tpLH
Vout
80%
output
50% signal slopes
waveform
20%
t
tf tr

Delay A CMOS VLSI Design Slide 24

12
RC Propagation Delay Estimation
Vin Vout

Vin
assume Vin rise time is 0

V0 = Vdd
Vout
V1 = Vdd/2

t
t0 t1

Delay A CMOS VLSI Design Slide 25

Effective Resistance
 Shockley models have limited value
– Not accurate enough for modern transistors
– Too complicated for much hand analysis
 Simplification: treat transistor in on state as resistor
– Replace Ids(Vds, Vgs) with Effective Resistance R
• Ids ~ Vds/R
– R averaged across switching of digital gate
 Too inaccurate to predict current at any given time
– But good enough to predict RC delay

Delay A CMOS VLSI Design Slide 26

13
 Switching Voltages

Vgs
Vgs
Vds
t

Vds = Vdd
Vds
Vds = Vdd/2

t
t0 t1

Delay A CMOS VLSI Design Slide 27

Approximating Output Resistance

(4.3.7)
 Want Effective Resistance that Fig. 4.20
has ~ same current as transistor
when VDS = Vdd/2
 No single R value matches
transistor through switching event
 Approach:
– Look at IV trajectory as input
Vgs rises high enough to start
transition
• While still being in saturation
– Compute average V/I on this
trajectory R = ln(2) * (3/4) * Vdd/Idsat
~ (1/2)*(Vdd/Idsat)
Delay A CMOS VLSI Design Slide 28

14
 Relating Back to Delay
 From before: R = ln(2) * (3/4) * Vdd/Idsat

 If we compute delay as ln(2) RC

– then R ~ (3/4) * Vdd/Idsat
 If we compute delay as “R’C” then use above

– I.e. choose effective R to include ln(2)

– OR: tpd = RC

Delay A CMOS VLSI Design Slide 29

Let’s Look at a Real Curve

X 10-4 VDD/2 3VDD/4 VDD
2.5
IDsat VGS = 2.5V
2
R1
Req
R2
1.5 VGS = 2.0V

1 VGS = 1.5V

0.5
VGS = 1.0V

0
0 0.5 1 1.5 2 2.5
VDS (V) 3 VDD 3 2.5V
Req    8.5K
4 I Dsat 4 220 A
Delay A CMOS VLSI Design Slide 30

15
 Approximating RON

Vdd
C = 50 ff
t = 0.27 ns
VDS R = t /(0.69 C) = 7.8 K
50%
Vdd/2

Delay A CMOS VLSI Design Slide 31

RC Values
 Capacitance Question: Why?
– C ≈ Cg ≈ Csb ≈ Cdb ≈ 2 fF/m of gate width
– Values similar across many processes for minimal gate
length.
VDD
 Resistance 0.6 μm: 5V
– IDsat ≈ 550 μA/μm 0.35 μm: 3.3 V
0.25 μm: 2.5 V
– VDD ∝ λ
0.18 μm: 1.8 V
– Req ≈ 0.75 VDD/Idsat ∝ λ 130 nm: 1.5 V
– Req ≈ 7 K*m in 0.6 μm process 90 nm: 1.2 V
– Req ≈ 2 K*m in 90 nm process
 Unit transistors
– May refer to minimum contacted device (4/2 )
– Or maybe 1 m wide device
– Doesn’t matter as long as you are consistent
Delay A CMOS VLSI Design Slide 32

16
 Drawing Equivalent Circuits
for Delay
 Model rise and fall as separate circuits
 Look at only the output of logic gate being modeled
– But consider capacitance from the gate it is driving
 Model transistors that turn “OFF” by an open
 Ignore all capacitors with both ends to a rail
 Model transistors that turn “ON” by their resistance
– If source is Vdd or Vgnd, model voltage on that
terminal as a “STEP Voltage”
 Ignore all capacitors with one end “floating”
 Lump ALL capacitors tied to same wire together
– Ignore which rail other side goes to
 Draw as equivalent RC “Ladder” driven by step voltage
Delay A CMOS VLSI Design Slide 33

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