Fall Semester: 2024-25

Lab Experiments
CSA2003 - Digital Logic and Computer Architecture
Slot - C12+C13+F11+F12+F13
Faculty Name - Dr. Daood Saleem

By: ABHISHEK KUMAR 23BAI10682

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 Table of Content

S. No. Experiment Name Page Date Remark

No.

1. Design and verify the truth table of all 8 basic logic gates. 4 - 13 12-07-24

2. To simplify the given expression and to realize it using basic 14 - 19 12-07-24

gates and Universal gate.
3. To Design and implement the circuit for the following 4-bit 20 - 27 13-07-24
Code conversion.
i) Binary to Gray Code
ii) Gray to Binary Code

4. To realize 28 - 35 13-07-24
a. Half Adder and Full Adder
b. Half Subtractor and Full Subtractor
by using Basic gates and NAND gates

5. a. Truth Table verification of 36 - 65 23-07-24

1) RS Flip Flop 2) D Flip Flop. 3) JK Flip Flop. 4) T Flip
Flop.
b. Conversion of one type of Flip Flop to another.

6. a. To design and set up a 4:1 Multiplexer (MUX) using only 66 - 71 23-07-24

NAND gates.
b. To design and set up a 1:4 Demultiplexer (DE-MUX)
using only NAND gates.

7. Implementation of a 3 bit SIPO and SISO shift register using 72 - 75 24-07-24

Flip Flops.
8. Implementation of a 3 bit PIPO and PISO shift register using 76 - 80 24-07-24
Flip Flops.
9. Design and verify the 4-bit synchronous up counter. 25-07-24

10. Design and verify the 4-bit asynchronous down counter. 25-07-24

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3
 Experiment No-1
Aim: Design and verify the truth table of all 8 basic logic gates.

Simulator used: Logisim

Theory, symbolic diagram and Truth Tables:

Theory:

What is a Logic Gate?

A logic gate is an electronic circuit designed by using electronic components like
diodes, transistors, resistors, and more. As the name implies, a logic gate is
designed to perform logical operations in digital systems like computers,
communication systems, etc.
Therefore, we can say that the building blocks of a digital circuit are logic gates,
which execute numerous logical operations that are required by any digital circuit.
A logic gate can take two or more inputs but only produce one output. The output
of a logic gate depends on the combination of inputs and the logical operation
that the logic gate performs.

Types of Logic Gates

A logic gate is a digital gate that allows data to be manipulated. Logic gates, use
logic to determine whether or not to pass a signal. Logic gates, on the other hand,
govern the flow of information based on a set of rules.
The logic gates can be classified into the following major types:
1. Basic Logic Gates
There are three basic logic gates:
1. AND Gate
2. OR Gate
3. NOT Gate
2. Universal Logic Gates
In digital electronics, the following two logic gates are considered as universal
logic gates:
1. NOR Gate
2. NAND Gate

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3. Derived Logic Gates
The following two are the derived logic gates used in digital systems:
1. XOR Gate
2. XNOR Gate

AND Gate :

The AND gate is an electronic circuit which gives a high output only if all its inputs
are high. The AND operation is represented by a dot (.) sign.

OR GATE :

The OR gate is an electronic circuit which gives a high output if one or more of its
inputs are high. The operation performed by an OR gate is represented by a plus
(+) sign.

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NOT GATE:

The NOT gate is an electronic circuit which produces an inverted version of the
input at its output. It is also known as an Inverter.

NAND GATE:

The NOT-AND (NAND) gate which is equal to an AND gate followed by a NOT gate.
The NAND gate gives a high output if any of the inputs are low. The NAND gate is
represented by a AND gate with a small circle on the output. The small circle
represents inversion.

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NOR GATE

The NOT-OR (NOR) gate which is equal to an OR gate followed by a NOT gate. The
NOR gate gives a low output if any of the inputs are high. The NOR gate is
represented by an OR gate with a small circle on the output. The small circle
represents inversion.

Exclusive-OR/ XOR GATE:

The 'Exclusive-OR' gate is a circuit which will give a high output if one of its inputs
is high but not both of them. The XOR operation is represented by an encircled
plus sign.

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EXCLUSIVE-NOR/Equivalence GATE:

The 'Exclusive-NOR' gate is a circuit that does the inverse operation to the XOR
gate. It will give a low output if one of its inputs is high but not both of them. The
small circle represents inversion.

BUFFFER GATE :

A buffer gate is a special type of logic gate that serves as a signal amplifier. Its
primary purpose is to strengthen a weak input signal so that it can drive a load
effectively.

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Simulation Diagrams:

1. AND GATE

2. OR GATE

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3. NOT GATE (INVERTER)

4. NOR GATE

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5. XNOR GATE

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6. XOR GATE

7. NAND GATE

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 8. BUFFER

Conclusion:
In this experiment, we explored basic logic gates and their behavior using Logisim
.The truth table of all 8 basic logic gates have been verified using Logisim.

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 Experiment No-2
Aim: To simplify the given expression and to realize it using basic gates and
Universal gate.

Given Expression: (A+B)(A’+C)(B+C)

Simulator used: Logisim

Theory, symbolic diagram and Minimization Technique:

Boolean Algebra simplification is not that difficult to understand if you realise that
the use of the symbols or signs of: “+” and “.” represent the operation of logical
functions.

Logical functions test whether a condition or state is either TRUE or FALSE but not
both at the same time. So depending on the result of that test, a digital circuit can
then decide to do one thing or another.

As we saw in the Laws of Boolean Algebra tutorial, that Boolean algebra is the
mathematics of logic and that the application of various switching theory rules
can be applied to simplify long or complex switching algebra notation, and which
can also be applied to logic gates and basic digital circuits.

Boolean Algebra Simplification

Boolean Algebra Simplification and how to simplify Boolean algebra expressions
using some basic rules applied to their variables, literals and terms.

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Having established the switching operation of the AND, OR, and NOT functions.
We can now look at simplifying some basic Boolean Algebra expressions to obtain
a final expression that has the minimum number of terms.
First let us start with something simple such as:
The Boolean Expression: A.(A + B)
Multiplying out the brackets gives us:

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Then we can see that the Boolean expression of A.(A + B) can be reduced to just
“A” which follows Boole’s Absorption Law.

Boolean Algebra Simplification Example No 2

By now you should have a basic idea of how to simplify Boolean algebra terms
using some basic Boolean Algebra Laws to reduce an algebraic expression to its
simplest form. So putting it all together in this final Boolean Algebra
Simplification example of:
Boolean Expression: (A + B’ + C’)(A +B’ + C)(A + B + C’)
Again, we will start by multiplying out the first brackets:

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hus the complex Boolean expression of: (A + B’ + C’)(A +B’ + C)(A + B + C’) has
been reduced down to the smaller expression of: A + (B’ C’)

Boolean Algebra Simplification Summary

A Boolean function is an algebraic expression formed using the AND, OR, and
NOT operators.
The Boolean variables of A, B, and C are known as the literals of the function and
although we have used the captial letters A, B, and C, literals can take on and
symbolic value. For example, X,Y,Z, or a, b, c. Thus any symbol can be used to
represent a logical variable that can have a value of 1 or 0.
There are several Boolean Algebra laws, rules and theorems available which
provides us with a means of reducing any long or complex expression or
combinational logic circuit into a much smaller one with the most common laws
presented in the following Boolean algebra simplification table.

While some of these laws and rules may seem self-evident, and others less so. It is
important to learn and understand them and their application when working on
combinational logic circuit reduction or simplification.

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Then Boolean algebra can be used to reduce any logic circuit to a simpler
equivalent circuit that functions identically to the original circuit, and in order to
prove the equality of the original and final Boolean expressions, truth tables could
be created for each to compare. If the truth tables match, then the final reduced
expression is correct.

GIVEN EXPRESSION : (A+B)(A’+C)(B+C)

Simplification using postulates:
1. Distribute the terms within the parentheses
(AA’+AC+A’B+BC)(B+C)
2. Apply the distributive property again:
(AA’+AC+A’B+BC)B + (AA’+AC+A’B+BC)C
3. Distribute each term:
AA’B+ABC+A’BB+BBC+AA’C+ACC+A’BC+BCC

We know AA’=1 and AA=A

0+ABC+A’B+BC+0+AC+A’BC+BC
ABC+A’B+BC+AC+A’BC+BC
4. Combine like terms:
ABC+A’BC+A’B+AC+BC [Since A+A=A]
(A+A’)BC+A’B+AC+BC
1.BC+A’B+AC+BC [A+A’=1]
BC+A’B+AC+BC
A’B+AC+BC

5. And now we have the simplified expression:

A’B+AC+BC

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Simulation Diagrams:

Conclusion:
The given expression has been simplified using basic postulates and the simplified
expression has been realized using Logisim . By simplifying expressions and
realizing them with logic gates, we gained practical insights into digital circuit
design.

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 Experiment-03
Aim: To Design and implement the circuit for the following 4-bit Code
conversion.

i) Binary to Gray Code

ii) Gray to Binary Code

Theory:
What is a Binary Code?

The Binary code is the numerical system used in digital electronics. It only consists of two
Symbols which are 0 and 1.In binary code each digit is represented by power of 2 with the
starting bit (right most bit) as 20 and bit as 21 and so on. The binary code is serves as the basis
for encoding text, number and various other types of data in the digital devices.

What is a Gray Code?

Gray Code system is a binary number system in which every successive pair of numbers differs
by only one bit. It is used in applications in which the normal sequence of binary numbers
generated by the hardware ,is read while the system changes from the initial state to the final
state. This could have serious consequences for the machine using the information. The Gray
code eliminates this problem since only one bit changes its value during any transition between
two numbers.

1. Converting Binary to Gray Code

Let 𝑏0,𝑏1,𝑏2,𝑎𝑛𝑑 𝑏3 b0,b1,b2,and b3 be the bits representing the binary numbers, where 𝑏0b0
is the LSB and 𝑏3b3 is the MSB, and Let 𝑔0,𝑔1,𝑔2,𝑎𝑛𝑑𝑔3g0,g1,g2,andg3 be the bits
representing the gray code of the binary numbers, where 𝑔0g0 is the LSB and 𝑔3g3 is the MSB.

Truth Table of Binary to Gray Code

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K-map for g0 K-map for g1

K-map for g2 K-map for g3

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Corresponding Minimized Boolean Expressions and Digital Circuit for Gray Code Bits

𝑔0=𝑏0𝑏1′+𝑏1𝑏0′=𝑏0⊕𝑏1

𝑔1=𝑏2𝑏1′+𝑏1𝑏2′=𝑏1⊕𝑏2

𝑔2=𝑏2𝑏3′+𝑏3𝑏2′=𝑏2⊕𝑏3

𝑔3=𝑏3

Logic Diagram

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Stimulated Diagram

2.Gray Code to Binary Code:

Converting gray code back to binary can be done in a similar manner. Let 𝑏0,𝑏1,𝑏2,𝑎𝑛𝑑𝑏3b0,b1
,b2,andb3 be the bits representing the binary numbers, where 𝑏0b0 is the LSB and 𝑏3b3is the
MSB, and

Let 𝑔0,𝑔1,𝑔2,𝑎𝑛𝑑𝑔3g0,g1,g2,andg3 be the bits representing the gray code of the binary
numbers, where 𝑔0g0 is the LSB and g3 is the MSB.

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Truth Table for Gray code to binary code

K-map for 𝑏0 K-map for𝑏1

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K-map for 𝑏2 K-map for𝑏3

Corresponding Minimized Boolean Expressions and Digital Circuit for binary Code Bits

b0=G0⊕G1⊕G2⊕G3

b1=G1⊕[G2⊕G3]

b2=G2⊕G3

b3=G3
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 Corresponding Digital Circuit

Stimulated Diagram:

Application of Code Converters – Binary to/from Gray Code

Given Below are the Applications of the Code Converters – Binary to/from Gray Code

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  Rotary Encoders: The Rotary encoders are device which is used to convey rotary
motions into digital signals. The code converters use to convert the Gray code output of
rotary encodes into binary.

 Control Systems: The Gray code converters are used in the Control system to integrate
between system using binary and gray code.

 Signal Processing: The Code converters are used in the signal processing to translate
between binary and Gray coded signals.

 Analog-to-Digital Conversion: The code converters are used in Ad to interface

between Gray coded ADC outputs and binary based DSP systems.

Conclusion

In this Experiment we have gone through Code Converters – Binary to/from Gray
Code, we have gone through the definition of the Code converters, Binary code
and gray code, then we have gone through Code conversion between Binary to
Gray code and vice versa.

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 Experiment - 04
Aim: To realize
a. Half Adder and Full Adder

b. Half Subtractor and Full Subtractor

by using Basic gates and NAND gates

Theory, symbolic diagram and Truth Tables:

Half Adder:

 It is a arithmetic combinational logic circuit designed to perform addition of

two single bits.

 It contains two inputs and produces two outputs.

 Inputs are called Augend and Added bits and Outputs are called Sum and
Carry.

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Simulation Diagrams:

Full Adder:

 To overcome the above limitation faced with Half adders, Full Adders are
implemented.

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  It is a arithmetic combinational logic circuit that performs addition of three
single bits.

 It contains three inputs (A, B, Cin) and produces two outputs (Sum and Cout).

 Where, Cin -> Carry In and Cout -> Carry Out

S = A'B'Cin + AB'Cin' + ABC + A'BCin

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Cout = BCin + AB + ACin

Stimulated Diagram

Half Subtractor

 It is a combinational logic circuit designed to perform the subtraction of two

single bits.

 It contains two inputs (A and B) and produces two outputs (Difference and
Borrow-output).

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Truth Table of Half Subtractor:

K-map Simplification for output variable ‘D’:

K-map Simplification for output variable ‘Bout‘ :

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Stimulated Diagram:

Full Subtractor:

 It is a Combinational logic circuit designed to perform subtraction of three

single bits.

 It contains three inputs(A, B, Bin) and produces two outputs (D, Bout).

 Where, A and B are called Minuend and Subtrahend bits.

 And, Bin -> Borrow-In and Bout -> Borrow-Out.

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Truth Table of Full Subtractor:

K-map Simplification for output variable ‘D’ :

D= A XOR B XOR Bin

K-map Simplification for output variable ‘Bout‘ :

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Stimulated Diagram:

Conclusion:
Half and full adders/subtractors are fundamental digital circuits. Half
adders/subtractors handle single-bit operations, producing sum/difference and
carry/borrow. Full adders/subtractors extend this to include carry-in/borrow-in for
multi-bit operations. Implementable using basic gates or NAND gates, they form
the basis for arithmetic in digital systems.

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 Experiment-05
Aim: a.) Truth Table verification of

1) SR Flip Flop 2) D Flip Flop. 3) JK Flip Flop. 4) T Flip Flop.

b.) Conversion of one type of Flip Flop to another.

Stimulator used: Logisim

Theory:
What is a Flip-Flop?

The flip-flop is a circuit that maintains a state until directed by input to change the
state. A basic flip-flop can be constructed using four-NAND or four-NOR gates. Flip-
flop is popularly known as the basic digital memory circuit. It has its two states as
logic 1(High) and logic 0(low) states. A flip flop is a sequential circuit which consist
of single binary state of information or data. The digital circuit is a flip flop which
has two outputs and are of opposite states. It is also known as a Bistable
Multivibrator.

Types of Flip-Flops

Given Below are the Types of Flip-Flop

 SR Flip Flop

 JK Flip Flop

 D Flip Flop

 T Flip Flop

S-R Flip Flop

In the flip flop, with the help of preset and clear when the power is switched ON,
the states of the circuit keeps on changing, that is it is uncertain. It may come to
set(Q=1) or reset(Q’=0) state. In many applications, it is desired to initially set or

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reset the flip flop that is the initial state of the flip flop that needs to be assigned.
This thing is accomplished by the preset(PR) and the clear(CLR).

Block Diagram of S-R Flip Flop

Circuit Diagram and Truth Table of S-R Flip Flop

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Operations of S-R Flip Flop

Given Below is the Operations of S-R Flip Flop

 Case 1(PR=CLR=1): The asynchronous inputs are inactive and the flip flop
responds freely to the S,R and the CLK inputs in the normal way.

 Case 2(PR=0 and CLR=1):This is used when the Q is set to 1.

 Case 3(PR=1 and CLR=0):This is used when the Q’ is set to 1.

 Case 4(PR=CLR=0): This is an invalid state.

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Characteristics Equation for SR Flip Flop

QN+1 = QNR’ + SR’

Stimulated Diagram

J-K Flip Flop

In JK flip flops, The basic structure of the flip flop which consists of Clock (CLK),
Clear (CLR), Preset (PR).

Block Diagram of J-K Flip Flop

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Circuit Diagram and Truth Table of J-K Flip Flop

Given Below is the Diagram of J-K Flip Flop with its Truth Table

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Stimulated Diagram

Operations of J-K Flip Flop

Given Below is the Operations of J-K Flip Flop

 Case 1 (PR=CLR=0 ):This condition is in its invalid state.

 Case 2 (PR=0 and CLR=1):The PR is activated which means the output in the
Q is set to 1. Therefore, the flip flop is in the set state.

 Case 3 (PR=1 and CLR=0):The CLR is activated which means the output in the
Q’ is set to 1. Therefore, the flip flop is in the reset state.

 Case 4 (PR=CLR=1):In this condition the flip flop works in its normal way
whereas the PR and CLR gets deactivated.

Race Around Condition in J-K Flip Flop

When the J and K both are set to 1, the input remains high for a longer duration of
time, then the output keeps on toggling. Toggle means that switching in the output
instantly i.e. Q=0, Q’=1 will immediately change to Q=1 and Q’=0 and this
continuation keeps on changing. This change in output leads to race around
condition.

Characteristics Equation for JK Flip Flop

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QN+1 = JQ’N + K’QN

D Flip Flop

The D Flip Flop Consists a single data input(D), a clock input(CLK),and two outputs:
Q and Q’ (the complement of Q).

Block Diagram of D Flip Flop

Circuit Diagram and Truth Table of D Flip Flop

Given Below is the Diagram of D Flip Flop with its Truth Table

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Operation of the D Flip-Flop

Given Below is the operation of D Flip-Flip

 Case 1 (PR=CLR=0):This conditions is represents as invalid state where both

PR(present) and CLR(clear) inputs are inactive.

 Case 2 (PR=0 and CLR=1):This state is set state in which PR is inactive (0) and
CLR is active(1) and the output Q is set to 1.

 Case 3 (PR=1 and CLR=0):This state is reset state in which PR is active (1) and
CLR is inactive (0) and the complementary output Q’ is set to 1.

 Case 4 (PR=CLR=1):In This state the flip flop behaves as normal, both PR and
CLR inputs are active(1).

Characteristics Equation for D Flip Flop

QN+1 = D

Stimulated Diagram

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T Flip Flop

The T Flip Flop consists of data input (T), a clock input (CLK), and two outputs: Q
and Q’ (the complement of Q).

Block Diagram of T Flip Flop

Circuit Diagram and Truth Table of T Flip Flop

Operation of the T Flip-Flop

Given Below is the Operation of T Flip-Flop

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  Case 1 (T=0):In this condition the flip-flop remains in its current state
regardless of clock input,Also the Output Q will remain unchanged unit the
value of T will not change.

 Case 2 (T=1):In this condition the flip flop will change when T input is 1,At
each rising or falling edge of the clock signal the output Q will be in
complementary state.

Characteristics Equation for T Flip Flop

QN+1 = Q’NT + QNT’ = QN XOR T

Stimulated Diagram:

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b) Conversion of Flip Flop to another

SR Flip Flop to JK flip Flop

As per the steps of conversion of flip-flops, the conversion process of SR flip-flop

into JK flip-flop is described below.

Step 1 - he excitation table for the conversion of SR flip-flop into JK flip-flop is given
below –

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Step 2 - Simplify the excitation for input expressions by using K-Map

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Step 3- Finally, draw the logic diagram of JK flip flop by using SR flip flop, which is
shown in figure-3 below.

Stimulated Diagram:

S-R Flip-Flop to T Flip-Flop:

Following is the characteristics table of T flip-flop and excitation table of S-R flip-
flop.

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Now, using K-map we get the expression for of S & R in terms of T.

S = TQn’ & R = TQn

Therefore, the circuit diagram for conversion of S-R flip-flop into T flip-flop is:

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Stimulated Diagram:

SK Flip Flop to D Flip Flop

Step-1:

We construct the characteristic table of D flip-flop and excitation table of S-R flip-
flop.

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Step-2

Using the K-map we find the boolean expression of S and R in terms of D.

S=D

R = D'

We construct the circuit diagram of the conversion of S-R flip-flop into D flip-flop.

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Stimulated Diagram

JK flip Flop to SR flip flop

The first step in converting a JK-to-SR flip-flop would be to write a JK-to-SR

conversion table as shown in Figure 1.

Simplify the logical expressions for the inputs

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Logic Diagram

Stimulated Diagram

JK Flip Flop to T Flip Flop

J and K are the actual inputs of the flip flop and T is taken as the external input for
conversion. Four combinations are produced with T and Qp. J and K are expressed
in terms of T and Qp. The conversion table, K-maps, and the logic diagram are
given below.

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Stimulated Diagram

JK flip flop to D flip flop

D is the external input and J and K are the actual inputs of the flip flop. D and Qp
make four combinations. J and K are expressed in terms of D and Qp. The four
combination conversion table, the K-maps for J and K in terms of D and Qp, and
the logic diagram showing the conversion from JK to D are given below.

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Stimulated Diagram

D flip flop to SR flip flop

D is the actual input of the flip flop and S and R are the external inputs. Eight
possible combinations are achieved from the external inputs S, R and Qp. But,
since the combination of S=1 and R=1 are invalid, the values of Qp+1 and D are
considered as “don’t cares”. The logic diagram showing the conversion from D to
SR, and the K-map for D in terms of S, R and Qp are shown below.

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Stimulated Diagram:

D Flip Flop to JK Flip Flop

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In this conversion, D is the actual input to the flip flop and J and K are the external
inputs. J, K and Qp make eight possible combinations, as shown in the conversion
table below. D is expressed in terms of J, K and Qp.

The conversion table, the K-map for D in terms of J, K and Qp and the logic diagram
showing the conversion from D to JK are given in the figure below.

Stimulated Diagram:

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D flip flop to T flip flop

In order to convert the given D flip-flop into a T-type, we need to obtain the
corresponding conversion table, as shown in Figure 9. Here, the information in the
excitation table of the D flip-flop is inserted as a part of the T flip-flop's truth table.

Having obtained the conversion table, the next step is to express the input, D, in
terms of T and Qn.

From Figure 10, we see that in order to convert the given D flip-flop into a T-type,
we need to drive its input pin (D) by the output of an XOR gate whose inputs are T
and Qn. This would lead to the new digital system which is shown in Figure 11(a).

If we must confine ourselves to only NOT, OR, and AND gates, we will need to
follow these steps:

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1. Use an AND gate to AND the user-defined input, T, and the negation of the
flip-flop's present-state Qn.

2. Use another AND gate to AND the present-state of the flip-flop with the
negation of T (obtained as an output of a NOT gate).

3. OR together the outputs of the two AND gates using a two-input OR gate.

This leads to the digital system shown in Figure 11(b).

Stimulated Diagram

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T flip flop to SR flip flop

In order to convert a given T flip-flop into SR-type, we need to combine the

information presented in the SR flip-flop's truth table and the information in the T
flip-flop's excitation table into a common table. This can be referred to as a T-to-SR
conversion table and is as shown in Figure 1.

Notice the don't care (X) entries in the last two rows of the conversion table's "T
input" column. These indicate that when both inputs (S and R) are driven high, the
output of the SR flip-flop is unpredictable (owing to the "race around condition").

Next, we should express the input of the given flip-flop in terms of the present-
state, Qn, and the input(s) of the desired flip-flop. This can be done by using a
suitable simplification technique, such as the K-map
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Diagram

Stimulated Diagram

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T flip flop to JK flip flop

We begin with the T-to-JK conversion table (see Figure 5), which combines the
information in the JK flip-flop's truth table and the T flip-flop's excitation table.

Next, we need to obtain the simplified Boolean expression for the T input in terms
of J, K, and Qn.

Figure 6: K-map simplification for the T input in terms of J, K, and Qn

Figure 6 shows the expression for the T input as JQn + KQn. This means that to
convert the T flip-flop into a JK flip-flop, the T input is driven by the output of a
two-input OR gate which has as inputs

1. J ANDed with the negation of the present-state Qn, i.e., Qn

2. K ANDed with the present-state, Qn

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Thus, we will need two AND gates and one OR gate, as shown in Figure 7.

Figure 7: T flip-flop designed to behave as a JK flip-flop

Stimulated Diagram:

T flip flop to D flip flop

We begin by writing the T-to-D conversion table (see Figure 9).

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Once this is done, we need to express the input, T, in terms of the user-defined
input, D, and the flip-flop's present-state, Qn. We will again use the K-map
simplification technique.

Figure 10: K-map simplification for the T input in terms of D and Qn

Figure 10 shows that, in order to make the given T flip-flop functionally equivalent
to a D flip-flop, we need to drive its input pin, T, with the output of an XOR gate
whose inputs are D and Qn. This will lead to the new digital system shown in Figure
11(a). Figure 11(b) shows a system which is functionally equivalent to that of
Figure 11(a) but is designed using only NOT, AND, and OR gates.

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Stimulated Diagram:

Conclusion
In this experiment we have gone through definition of the flip flop in brief with its
different types, we have also gone through conversion of flip and the Application
of the Flip Flop.

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 Experiment No-6 (a)
Aim:
A. To design and set up a 4:1 Multiplexer (MUX) using only NAND gates.

B.

Simulator used: Logisim

Theory, symbolic diagram and Truth Tables:

Understand the 4:1 MUX Function:

 Inputs:

o 4 Data inputs: D0,D1,D2,D3D_0, D_1, D_2, D_3D0,D1,D2,D3

o 2 Select inputs: S0,S1S_0, S_1S0,S1

 Output:

o 1 Output: YYY

The output YYY is determined by the select inputs S0S_0S0 and S1S_1S1 as
follows:

NAND Gate Basics:

 NAND Gate Function:

o The NAND gate output is the negation of the AND function. For
inputs A and B, the output Is ( A⋅B)’

 Inversion Using NAND Gates:

o To create NOT from NAND:

o NOT(A)=A NAND

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  AND Gate Using NAND:

o To create AND from NAND:

o A AND B=NOT(A NAND B)A

Build Basic Logic Gates Using NAND:

 NOT Gate: Connect both inputs of a NAND gate to the same signal.

 AND Gate: First use a NAND gate to get the NAND of the inputs, then use
a NOT gate (another NAND gate) to invert the result.

 OR Gate: Use De Morgan’s Theorem:

A OR B=NOT(NOT(A) AND NOT(B))

 Design the 4:1 MUX Circuit:

 Implement the MUX Logic:

1. Create Select Lines:

 Use NAND gates to implement the negation of select inputs.

2. Create the Multiplexer Logic:

 Combine the inverted select lines with the data inputs using
NAND gates to form the required AND and OR logic.

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Simulation Diagrams:

Conclusion:

Designing a 4:1 multiplexer (MUX) using only NAND gates involves a

fundamental understanding of digital logic and NAND gate functionality. By
leveraging NAND gates to create basic logic operations such as NOT, AND, and
OR, we can construct the entire multiplexer circuit.

The process begins with implementing the NOT operation, followed by creating
AND gates and combining them to realize the MUX’s functionality. This design
approach not only demonstrates the versatility of NAND gates but also provides a
deeper insight into how complex digital systems can be constructed from simpler
components.

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 Experiment No-6(b)
Aim: To design and set up a 1:4 Demultiplexer (DE-MUX) using only NAND
gates.

Simulator used: Logisim

Theory, symbolic diagram and Minimization Technique:

Steps to Design a 1:4 Demultiplexer Using NAND Gates

1. Understand the 1:4 Demultiplexer Function:

o Input:

 1 Data input: DDD

 2 Select inputs: S0S_0S0 and S1S_1S1

o Outputs:

 4 Outputs: Y0,Y1,Y2,Y3

o Behaviour:

 Based on the values of S0 and S1 , the data input D is routed to

one of the four outputs. Each output will be activated when the
corresponding select line combination is true.

2. Demultiplexer Logic:

o The demultiplexer can be described by the following equations:

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Y0 = D . S1’ . S0

Y1 = D1. S1’ . S0

Y2 = D.S1.S0’

Y3 = S.S1.S0

3. Construct the 1:4 Demultiplexer:

o Step 1: Implement the NOT Gates:

 Create NOT gates for S0 and S1 using NAND gates.

o Step 2: Implement the AND Gates:

 Use NAND gates to build AND gates for each of the four
demux output expressions.

 For example, to get D⋅S1‾⋅S0‾D

 First, create the negated select lines: S1’ S0’

 Then, use NAND gates to combine D,S1’ and S0’ , Y0

o Step 3: Implement the OR Gates:

 Combine the results of the AND gates to ensure each output is

properly directed based on the select lines.

Simulation Diagrams:

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Conclusion:

Designing a 1:4 Demultiplexer (DE-MUX) using only NAND gates illustrates the
fundamental versatility and power of NAND gates in digital logic design. Through
this process, we have demonstrated how complex digital functions can be
constructed from simple building blocks.

In this design, we successfully translated the demultiplexer’s functionality into a

circuit using NAND gates to perform inversion, AND, and OR operations. By
carefully implementing the demultiplexer logic and verifying its operation in
Logisim, we ensure that the data input is correctly routed to one of four outputs
based on the select lines.

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 Experiment No-7
Aim: Implementation of a 3 bit SIPO and SISO shift register using Flip Flops.

Simulator used: Logisim

Theory, symbolic diagram and Minimization Technique:

3-bit SIPO Shift Register

1. Open Logisim: Start Logisim and create a new project.

2. Add Components:

o 3 D Flip-Flops: These will store the bits of the shift register.

o 1 Clock: To drive the flip-flops.

o 1 Input Pin: For the serial input.

o 3 Output Pins: For the parallel outputs.

3. Connect the Components:

o Place the 3 D Flip-Flops in a row.

o Connect the Clock to the Clock input of all three D Flip-Flops.

o Connect the Input Pin (serial input) to the D input of the first D Flip-
Flop.

o Connect the Q output of the first D Flip-Flop to the D input of the

second D Flip-Flop.

o Connect the Q output of the second D Flip-Flop to the D input of the

third D Flip-Flop.

o Connect the Q outputs of all three D Flip-Flops to the 3 Output Pins.

4. Label the Components:

o Label the Input Pin as "Serial In".

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 o Label the Output Pins as "Q0", "Q1", and "Q2" corresponding to the
first, second, and third flip-flops respectively.

3-bit SISO Shift Register

1. Open Logisim: Start Logisim and create a new project if you haven't
already.

2. Add Components:

o 3 D Flip-Flops: These will store the bits of the shift register.

o 1 Clock: To drive the flip-flops.

o 1 Input Pin: For the serial input.

o 1 Output Pin: For the serial output.

3. Connect the Components:

o Place the 3 D Flip-Flops in a row.

o Connect the Clock to the Clock input of all three D Flip-Flops.

o Connect the Input Pin (serial input) to the D input of the first D Flip-
Flop.

o Connect the Q output of the first D Flip-Flop to the D input of the

second D Flip-Flop.

o Connect the Q output of the second D Flip-Flop to the D input of the

third D Flip-Flop.

o Connect the Q output of the third D Flip-Flop to the Output Pin (serial
output).

4. Label the Components:

o Label the Input Pin as "Serial In".

o Label the Output Pin as "Serial Out".

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Simulation Diagrams:

SIPO

SISO

Conclusion:

Implementing 3-bit SIPO (Serial-In, Parallel-Out) and SISO (Serial-In, Serial-Out)

shift registers using D Flip-Flops in Logisim is a straightforward process that
enhances understanding of digital logic design and sequential circuits.

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By following the steps outlined:

1. Setting up the Components: Arranging D Flip-Flops, clock sources, and

input/output pins appropriately.

2. Wiring Connections: Ensuring proper connections between the clock, serial

input, and flip-flops, while also correctly cascading the outputs for SISO and
connecting parallel outputs for SIPO.

3. Simulation and Testing: Using Logisim's simulation capabilities to observe

the behavior of the shift registers, confirming that bits are shifted correctly
either serially or parallelly.

This exercise provides practical experience with basic digital electronics concepts
and prepares one for more complex designs. It also demonstrates the versatility of
Logisim as an educational tool for visualizing and testing digital circuits.

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 Experiment No-8
Aim: To simplify the given expression and to realize it using basic gates and
Universal gate.

Simulator used: Logisim

Theory, symbolic diagram and Minimization Technique:

3-bit PIPO Shift Register

1. Open Logisim and create a new project.

2. Place D flip-flops:

o From the "Memory" library, drag three D flip-flops onto the

workspace. These will be used to store each bit of the 3-bit register.

3. Connect the clock signal:

o Place an input pin on the workspace and label it as the clock (CLK).

o Connect the CLK input to the clock input of all three D flip-flops.
This will synchronize the flip-flops to the same clock signal.

4. Create data inputs:

o Place three input pins on the workspace and label them as D0, D1, and
D2.

o Connect D0 to the data input (D) of the first flip-flop, D1 to the data
input of the second flip-flop, and D2 to the data input of the third flip-
flop.

5. Create data outputs:

o Place three output pins on the workspace and label them as Q0, Q1,
and Q2.

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 o Connect the output (Q) of the first flip-flop to Q0, the output of the
second flip-flop to Q1, and the output of the third flip-flop to Q2.

6. Enable control:

o If you want to have an enable signal, place an input pin and label it as
EN.

o Use AND gates to control the data inputs to the flip-flops, so the data
is only loaded when EN is high.

Your 3-bit PIPO shift register is now complete. The data at D0, D1, and D2 will be
loaded into the flip-flops on a clock edge and will be available at Q0, Q1, and Q2,
respectively.

3-bit PISO Shift Register

1. Open a new circuit in Logisim if not already done.

2. Place D flip-flops:

o From the "Memory" library, drag three D flip-flops onto the

workspace.

3. Connect the clock signal:

o Place an input pin on the workspace and label it as CLK.

o Connect the CLK input to the clock input of all three D flip-flops.

4. Create data inputs:

o Place three input pins and label them as D0, D1, and D2.

o Connect D0 to the data input (D) of the first flip-flop, D1 to the data
input of the second flip-flop, and D2 to the data input of the third flip-
flop.

5. Connect flip-flops for serial output:

o Connect the output (Q) of the first flip-flop to the data input (D) of the
second flip-flop.

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 o Connect the output of the second flip-flop to the data input of the third
flip-flop.

6. Create serial output:

o Place an output pin on the workspace and label it as Qout.

o Connect the output of the third flip-flop to Qout.

7. Enable parallel loading:

o Place an input pin and label it as Load.

o Use multiplexers (MUX) to choose between loading the parallel data

or shifting the data.

o For each flip-flop, place a 2-to-1 MUX with inputs connected to D0,
D1, and D2 for the load operation and the previous flip-flop's Q
output for the shift operation.

o Connect the select line of the MUX to the Load input.

Your 3-bit PISO shift register is now complete. The parallel data at D0, D1, and
D2 can be loaded into the flip-flops, and the data will shift out serially through
Qout on each clock pulse.

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Simulation Diagrams: (PIPO)

PISO

Conclusion:
In this guide, we have successfully implemented both a 3-bit Parallel-In Parallel-
Out (PIPO) and a 3-bit Parallel-In Serial-Out (PISO) shift register using D flip-
flops in Logisim. The PIPO shift register allows data to be loaded in parallel and
read out in parallel, providing a straightforward means of data storage and

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retrieval. Conversely, the PISO shift register enables parallel data loading with a
serial output, making it useful for converting parallel data to serial form for
transmission or processing.

By following the detailed steps for placing and connecting D flip-flops, input pins,
output pins, and additional control logic like enable and load signals, you should
now have a clear understanding of how to design these essential digital circuits.
Testing the circuits with clock pulses ensures their functionality, providing
valuable hands-on experience in digital design.

These shift registers are foundational components in many digital systems, and
mastering their implementation in Logisim will aid in understanding more complex
digital circuits and systems in future projects

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