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Comparator 1-Bit

Comparator 1bit

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132 views5 pages

Comparator 1-Bit

Comparator 1bit

Uploaded by

my.show7777
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DESIGN OF 1-BIT COMPARATOR USING DATAFLOW MODELLING STYLE

Q) Design 1-Bit Comparator using dataflow modelling style and write its VHDL code.
Simulate using XILINX ISE 14.5 Software.

Aim: To write and simulate the VHDL code for 1-bit comparator using dataflow modelling style
and simulate using Xilinx ISE 14.5 software and verifies its functionality.

Equipment Required:

1. Personal Computer
2. Xilinx ISE Software

Theory:

1-Bit Comparator - The Digital Comparator is another very useful combinational


logic circuit used to compare the value of two binary digits. A magnitude digital
Comparator is a combinational circuit that compares two digital or binary numbers in
order to find out whether one binary number is equal, less than or greater than the
other binary number. We logically design a circuit for which we will have two inputs
one for A and another for B and have three output terminals, one for A > B condition,
one for A = B condition and one for A < B condition.

A comparator used to compare two bits is called a single bit comparator. It consists of
two inputs each for two single-bit numbers and three outputs to generate less than,
equal to and greater than between two binary numbers
Block Diagram:

Logic Diagram:
Truth Table:

INPUTS OUTPUTS
A B G (A>B) L (A<B) E (A=B)
0 0 0 0 1
0 1 0 1 0
1 0 1 0 0
1 1 0 0 1

Output Expressions:

A>B output expression:

G = A AND (NOT B)

A<B output expression:

L= (NOT A) AND B

A=B output expression

E= A XNOR B
Procedure:

1. Click on the Xilinx ISE icon on the desktop of the PC. Project Navigator opens.
2. Create New Project from File Menu. Give the file name and choose HDL as Top Level
Source Type.
3. Create New Source by clicking on Project. Select VHDL Module and name the file.
Assign Input and Output pins.
4. VHDL code is presented on the screen. Now we just need to write the code in
architecture.
5. Select New Source by clicking on project source and then select Test Bench Waveforms
and name the file.
6. A new window will appears. For combinational circuits select combinatorial clock.
7. Set the input waveforms by clicking on the waveforms at different time intervals.
8. Select Behavioral Simulation from sources window.
9. Now in the process window click on Xilinx ISE Simulator. Check syntax and then
Simulate Behavioral Model.
10. Simulation window opens verify input and output waveforms according truth table.
11. View RTL Synthesis.

VHDL CODE:

Dataflow VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FULLADDER is
Port ( A,B : in STD_LOGIC;
G, L,E : out STD_LOGIC);
end FULLADDER;

architecture DATAFLOW of FULLADDER is


begin
G<= A AND (NOT B);
L<= (NOT A) AND B;
E<= A XNOR B;
end DATAFLOW;

Outputs:

Dataflow RTL Schematic:

Internal view of RTL SCHEMATIC

Simulation Waveform:

Result: The Truth table of 1-Bit comparator verified using Xilinx 14.5 software.

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